Tradeoff Analysis and Optimization of Power …...Tradeoff Analysis and Optimization of Power...
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Tradeoff Analysis and Optimization of Power Delivery Networks with On-Chip Voltage
Regulation
Zhiyu Zeng Xiaoji Ye Zhuo Feng* Peng LiZhiyu Zeng, Xiaoji Ye, Zhuo Feng*, Peng LiDepartment of ECE, Texas A&M University
*Department of ECE, Michigan Technological UniversityJ 1 2010Jun. 17, 2010
OutlineMotivation
– Multiple power islands [Lackey, ICCAD 2002]Overview of on chip voltage regulationOverview of on-chip voltage regulation
– Introduction to on-chip low-dropout voltage regulators (LDOs)Simulation for power delivery networks with on-chip LDOs
– Power delivery network modeling
– Simulation challenges
– GPU-CPU combined simulator: GSimGPU CPU combined simulator: GSimDesign for power delivery networks with on-chip LDOs
– Design aspects
– Design tradeoffs investigation
– Optimization formulation
– Experimental results of optimization scheme for two test circuits
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Experimental results of optimization scheme for two test circuitsConclusion
Motivation IPower is critical to IC designs
– Technology scaling leads to larger power consumption/density
P i i f hi h f– Power crisis of high-performance processors
– Growth in low-power SoCs for portable devices1.8
1 4
1.6
W/m
m2 )
1.2
1.4
wer
Den
sity
(W
2008 2010 2012 2014 2016 2018 2020 20220.8
1Po
3
Year
ITRS Roadmap 2009
Motivation IIPower consumption of CMOS circuits
– Active power: P = CV2f
L k b th h ld t– Leakage power: sub-threshold currentLow-power techniques
– Clock gating
– Power gating
– Dynamic voltage and frequency scaling (DVFS)
M lti l lt i l d (MVI)– Multiple voltage islands (MVI)
4clock gating power gating DVFS MVI
Motivation IIIMultiple voltage Islands
– High voltage for I/O buffers (1.8V), medium voltage for analog circuits (1 2-1 4V) low voltage for logic circuits (0 6-1V) [Hazuchacircuits (1.2 1.4V), low voltage for logic circuits (0.6 1V) [Hazucha, JSSC 2005]
– High voltage for critical circuit blocks, low voltage for non-critical blocksblocks
– Require multiple voltage supplies on chip
– On-board voltage regulator modules (VRMs): space and pins tl ff hi iticostly, off-chip parasitics
5
[Shah, ElectronicDesign.com, 2008]
OutlineMotivation
– Multiple power islandsOverview of on chip voltage regulationOverview of on-chip voltage regulation
– Introduction to on-chip LDOsSimulation for power delivery networks with on-chip LDOs
– Power delivery network modeling
– Simulation challenges
– GPU-CPU combined simulator: GSimGPU CPU combined simulator: GSimDesign for power delivery networks with on-chip LDOs
– Design aspects
– Design tradeoffs investigation
– Optimization formulation
– Experimental results of optimization scheme for two test circuits
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Experimental results of optimization scheme for two test circuitsConclusion
Voltage RegulatorsSwitching regulators:
– Pros: high power efficiency
C i d t h d t i t t d– Cons: inductors are hard to integrated on chip
Linear regulators:– Pros: easy for on-chip integration, small
size, low standby current
– Cons: power efficiency is constrained
Switching regulator [Kim, HPCA 2008]
by Vout/Vin ratio
– Low-dropout voltage regulator (LDO): linear regulator with lowest dropout voltage and improved power efficiency
– Capacitorless LDOs are attractive for on-chip voltage regulation. [Leung,
External capacitorless LDO [Milliken
7
JSSC 2003] [Milliken, TCASI 2007] External capacitorless LDO [Milliken, TCASI 2007]
On-Chip LDO BackgroundLDO Topology: [Milliken, TCASI 2007]
Vin
Iin
MVout
Iout
Mp
Rf1 Cout
Current Amplifier
Cf
If
ICDifferentiator
VG
+
- VrefRf2
out
Error Amp
CDifferentiator
Basic concepts:– Dropout voltage Vdrop
AmpVin
VoutDropout voltage Vdrop
– Dropout region and regulation region
– Power efficiency ε:( )
out out out out
in in out p in
I V I VI V I I V
ε = =+VΔ VΔ
out
8
– Line regulation and load regulation ( )in in out p in
out
in
VV
ΔΔ
out
out
VI
ΔΔ
[Lee, TI Application Report 1999]
Electrical Characteristics of LDOsResponse to Iout variation
1.4
1.405
1.41
0.25
0.3
1.38
1.385
1.39
1.395
1.4
Vou
t (V)
0.1
0.15
0.2
I out (A
)
VoutIout
Response to Vin variation0 1 2 3 4 5 6
x 10-8
1.365
1.37
1.375
Time (s)
0
0.05
p in
1 398
1.3985
1.399
1.3995
1.4
2
2.1
2.2
2.3
1.396
1.3965
1.397
1.3975
1.398
Vou
t (V)
1.6
1.7
1.8
1.9
Vin
(V)
Vin
Vout
9
0 0.5 1 1.5x 10
-7
1.395
1.3955
Time (s)
1.4
1.5
Benefits of On-Chip Voltage RegulationSuppressing high-frequency local droop
– LDOs provide strong local voltage regulationRemedying mid frequency global resonance
Off-chip network
On-chip networkRemedying mid-frequency global resonance
– The resonance is blocked at the input of voltage regulator
1 25
high-freqmid-freq
1.2
1.25without LDOswith 16 LDOs
1.1
1.15
Volta
ge (V
)
1
1.05
V
mid-frequency resonance
10
0 1 2 3 4 5 6 7x 10
-8Time (s)
Overview of This WorkSimulation for power delivery networks with on-chip voltage regulation
– Understand detailed electrical characteristics– Understand detailed electrical characteristics
– GPU-CPU combined simulator: Gsim
Tradeoff analysis for on-chip voltage regulation– Overall power efficiency
– Maximum voltage droopMaximum voltage droop
– LDO overhead
Optimization for on-chip voltage regulation– Optimization formulation
– Observation for two test circuits
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Observation for two test circuits
OutlineMotivation
– Multiple power islandsOverview of on chip voltage regulationOverview of on-chip voltage regulation
– Introduction to on-chip LDOsSimulation for power delivery networks with on-chip LDOs
– Power delivery network modeling
– Simulation challenges
– GPU-CPU combined simulator: GSimGPU CPU combined simulator: GSimDesign for power delivery networks with on-chip LDOs
– Design aspects
– Design tradeoffs investigation
– Optimization formulation
– Experimental results of optimization scheme for two test circuits
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Experimental results of optimization scheme for two test circuitsConclusion
Power Delivery Network with On-Chip LDOsSimulation challenges:
– Large on-chip grids with millions nodes. SPICE is not practical
H d d t th d LDO ( li ) i ti id– Hundreds to thousands LDOs (nonlinear): existing power grid solvers can not handle nonlinear devices
[Gupta DATE 2007][Gupta, DATE 2007]
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GSim Simulation FrameworkCircuit partitioning relaxation method
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GSim DetailsCircuit partition update scheme
– Through partition boundary voltages
Convergence– Check the average and maximum voltage changes at partition
boundaries
– Smooth voltage changes on the boundaries
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– Can be improved by multi-level Newton method
GSim Simulation ResultsGSim is very efficient
– Cost of on-chip power grid analysis is dominant. Over 50X speedup over CHOLMODover CHOLMOD
– LDOs are simulated individually, potential parellelism
– Fast convergence: average <3 iterations per step
Num. Nodes
Num. LDOs
Runtime (s) Num. IterationNodes LDOs
Total /Step CPU % GPU % Total /Step
2.25M 36 1810 1.6 22 78 2274 1.9
2 25M 144 1768 1 5 23 77 2000 1 72.25M 144 1768 1.5 23 77 2000 1.7
9M 64 7398 6.2 24 76 2864 2.4
9M 256 4500 3.7 27 73 1900 1.4
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OutlineMotivation
– Multiple power islandsOverview of on chip voltage regulationOverview of on-chip voltage regulation
– Introduction to on-chip LDOsSimulation for power delivery networks with on-chip LDOs
– Power delivery network modeling
– Simulation challenges
– GPU-CPU combined simulator: GSimGPU CPU combined simulator: GSimDesign for power delivery networks with on-chip LDOs
– Design aspects
– Design tradeoffs investigation
– Optimization formulation
– Experimental results of optimization scheme for two test circuits
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Experimental results of optimization scheme for two test circuitsConclusion
Design Aspects IDesign aspects for on-chip voltage regulation:
– Maximum voltage droop
O ll ffi i– Overall power efficiency
– LDO overhead
Maximum Voltage Droop Overall Power
EfficiencyOverhead
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Design Aspects IIIntermediate variables:
– Number of LDOs.
I t lt– Input voltage.Maximum voltage droop:
– Maximum voltage droop vs. number of LDOs
– Maximum voltage droop vs. input voltageOverall power efficiency:
– Overall power efficiency vs number of LDOsOverall power efficiency vs. number of LDOs
– Overall power efficiency vs. input voltageLDO overhead:
– Chip area
– Routing resources
– In proportion to number of LDOs
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In proportion to number of LDOs
Maximum Voltage Droop IMaximum voltage droop vs. number of LDOs
– More LDOs, stronger local voltage regulation
M LDO l t f d i t f h LDO– More LDOs, less amount of dynamic current for each LDO
– Increasing number of LDOs would lower maximum voltage droopMaximum Voltage Droop vs. Number of LDOs
90
100
mV)
70
80
ge D
roop
(
60
70
Volta
g
20
0 10 20 30 4050Number of LDOs
Maximum Voltage Droop IIMaximum voltage droop vs. input voltage
– In regulation region, voltage droop is stable
I d t i lt d i ith d i i t– In dropout region, voltage droop increases with decreasing input voltage
– Significantly lowering the input voltage is harmfulM i V lt D I t V lt
100
105
mV)
Maximum Voltage Droop vs. Input Voltage
85
90
95
e D
roop
(m
75
80
85
Volta
ge
21
1.4 1.5 1.6 1.770Input Voltage (V)
Power Efficiency IN∑Overall power efficiency
Power efficiency vs. number of LDOs
1
1
N okk
N ikk
P
Pε =
=
= ∑∑
Power efficiency vs. number of LDOs– Quiescent current Iq is small
– Reducing LDOs has little impact on power efficiencyPower Efficiency vs Number of LDOs
0.89Power Efficiency vs. Number of LDOs
cy
0.885
r Effi
cien
c
0.88
Pow
er
22
0 10 20 30 400.875Number of LDOs
Power Efficiency IIPower efficiency vs. input voltage
– Less Vin, larger
I th d t i LDO k i t
out
in
VV
– In the drop-out region, LDO works as a resistor
– Lowering input voltage significantly increases power efficiency
Power Efficiency vs Input Voltage1Power Efficiency vs. Input Voltage
cy
0.95
er E
ffici
enc
0 85
0.9
Pow
e
23
1.4 1.5 1.6 1.70.85Input Voltage (V)
Design TradeoffsPower efficiency vs. input voltage Voltage droop vs. # LDOs and input voltage LDO overhead vs. # LDOsLDO overhead vs. # LDOs
160
180Regulation Region Dropout Region
120
140
p (m
V)
Vin=1.65VVin=1.4V
80
100
120
Volta
ge D
roop N=4
N=9
60
80V
N=16
N=25
24
0.82 0.84 0.86 0.88 0.9 0.92 0.94 0.96 0.9840
Power Efficiency
Optimization for On-Chip Voltage Regulation Notations:
– N power islands, each has XkxYk LDOsYk
Objective function (maximize power efficiency):
/k k k kX Y X YN N
o iP Pε =∑∑ ∑∑ X
k
Subject to:
1 1 1 1
/ij iji j i j
P Pε= = = =
=∑∑ ∑∑
d
Xk
– Voltage droop constraint:
– Overhead constraint:
, 1, ,d mk kv v k N≤ =
N
X Y M≤∑Overhead constraint:
Optimization variables:
1k k
k
X Y M=
≤∑
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– number of LDOs (Xk,Yk) and input voltage (Vin)
Optimization Using APPSAsynchronous parallel pattern search (APPS) [Gray, TMS 2006]
– Solve unconstrained and bound-constrained optimization problems
Si l ti b d ti i ti– Simulation based optimizationOptimization formulation
– Objective function: ( ) 1 ( ) ( )df x P V P X Yε= − + +
– Constraints:
– Penalty function P(Vd) for voltage droop constraint:1 11 { , , }, 1 { , , }, 0N N inx x y y V≤ ≤ ≤… …
2( )d m d mV V i V V⎧ ∃
– Penalty function P(XY) for overhead constraint:
2( ) , :( )
0, others
d m d mi i i i
dV V i V V
P Vα⎧ − ∃ >
= ⎨⎩
y ( )2
1 1( ) ,
( )
N N
k k k kk k
N
X Y M X Y MP XY
β= =
⎧− >⎪⎪= ⎨
⎪
∑ ∑
26
10, k k
kX Y M
=
⎪ <⎪⎩
∑
Experimental Setups- OptimizationTwo test circuits:
– Circuit 1: low-voltage dominant
Ci it 2 hi h lt d i t– Circuit 2: high-voltage dominant
A B
CC
A
B
Domain J Vdd (V) Vm (V) Area
Circuit 1 Circuit 2
Circuit 1 Circuit 2A 2/3 1.4 70m 1 6B 1/2 1.2 60m 2 2C 1/3 1 0 50 6 1
27
C 1/3 1.0 50m 6 1
Experimental Results- Optimization ICircuit 1:
– Island C has the dominant current loads
I l d C h th ti ht t lt d t i t– Island C has the tightest voltage droop constraint
– Most of the LDOs are placed in island C
– Input voltage is low and overall power efficiency is lowp g p y
– The voltage regulators in A are pushed towards dropout region
– Voltage regulators in B and C are away from dropout region
– May need new voltage regulation topologies to increase the overall power efficiency [Amelifard, TCAD 2009]
Test M Num. LDOs Vd (V) Vin (V) ε % Runtime Circuit
( ) in ( )(h)
Total A B C A B C
1 50 48 4 8 36 61.8m 50.4m 45.2m 1.45 77.3 7.6
28
2 65 61 54 6 1 69.6m 50.0m 49.6m 1.50 90.7 8.2
Experimental Results- Optimization IICircuit 2:
– Domain A has the dominant current loads
M t f th LDO l d i i l d A– Most of the LDOs are placed in island A
– Input voltage is high and overall power efficiency is high
– The voltage regulators in A, B and C are all away from dropout g g , y pregion
Test Circuit
M Num. LDOs Vd (V) Vin (V) ε % Runtime (h)Circuit (h)
Total A B C A B C
1 50 48 4 8 36 61.8m 50.4m 45.2m 1.45 77.3 7.6
2 65 61 54 6 1 69 6m 50 0m 49 6m 1 50 90 7 8 2
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2 65 61 54 6 1 69.6m 50.0m 49.6m 1.50 90.7 8.2
OutlineMotivation
– Multiple power islandsOverview of on chip voltage regulationOverview of on-chip voltage regulation
– Introduction to on-chip LDOsSimulation for power delivery networks with on-chip LDOs
– Power delivery network modeling
– Simulation challenges
– GPU-CPU combined simulator: GSimGPU CPU combined simulator: GSimDesign for power delivery networks with on-chip LDOs
– Design aspects
– Design tradeoffs investigation
– Optimization formulation
– Experimental results of optimization scheme for two test circuits
30
Experimental results of optimization scheme for two test circuitsConclusion
ConclusionGsim for power delivery network simulation
– Fast GPU-CPU combined simulation
H dl li it f LDO i th t k– Handle nonlinearity of LDOs in the network
– Provide detailed electrical characteristics of LDOs in the network
Survey on design aspects of on-chip power regulation– Maximum voltage droop
– Overall power efficiencyOverall power efficiency
– LDO overhead
– Tradeoffs among these three aspects
Optimization scheme for on-chip power regulation– Optimization formulation
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– Key observations for two test circuits
Thanks!
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