Tracker Strip and Pixel FEDs

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Tracker Strip and Pixel FEDs. John Coughlan Tracker Readout Upgrade Meeting September 12 th 2007. Strip FED. 9U VME64x 96 optical fibres Analogue ORx 96 ADC channels Limited by I/O Component density 1 nsec timing Board mounted Digital FPGAs Xilinx Cluster Algorithms - PowerPoint PPT Presentation

Transcript of Tracker Strip and Pixel FEDs

  • Tracker Strip and Pixel FEDsJohn CoughlanTracker Readout Upgrade MeetingSeptember 12th 2007

  • Strip FED9U VME64x 96 optical fibresAnalogue ORx 96 ADC channelsLimited by I/O Component density1 nsec timingBoard mountedDigital FPGAs XilinxCluster AlgorithmsRaw input data rate >3 GB/s.Processed Output rate < 200 MB/sVME FPGAFront-End data processing FPGAPower DC-DCs on boardOutput to DAQEvent Builder FPGAModularFE Unit96 ADC channelsDouble Sided BoardOpto ReceiversTTC rx450 x boards + SlinksSynch APVCost Driven

  • Strip FED Board ManufactureBoard parameters:- 9U x 440 mm VME64x form factor- Optical/Analogue/Digital logic ; 96 ADC channels Double-sided (secondary side with half of analogue channels) 6,000 components (majority of passives 0402) (finest pitch < 20 thou) 25,000 tracks 37 BGAs (typical FPGA 676 pins on 1mm pitch). All BGAs located on primary side. 14 layer PCB (incl. 6 power & gnd) controlled impedanceHigh density components.Close up of analogue section on primary sideAlmost all components on board are Surface Mount.VALUE is in the COMPONENTSDesign for TESTMust have HIGH YIELD

  • Pixel FED9U VME64x36 optical fibresAnalogue ORx 36 ADC channelsLimited by SLINK output rate1 nsec timingDigital FPGAs AlteraInputs are ZSUnsynchronised Events on fibresROC 16 eventsBuild DAQ EventsTimestamp TTCEncoded header

  • Pixel FED9U VME64x boards+ Slink

    Mezzanine cards 9 Analogue,5 FPGA Altera cards(not ORx)Common Electrical SLINKP3 64 bits @ 80 MHz+ TTS throttle FMMs40 x 9U boards + SlinksReduces Motherboard complexity 10 layer(Micro vias for Alteras on mezz)Less risk. Testing, repairing easier. Spares

    Takes more spaceConnector reliabilitySignal integrity. Terminations

    Power

  • Strips and Pixel FEDsSame Form Factor 9U VME . 450 vs 32 boardsBoth Analogue & Digital designsSame Interfaces ORx, ADCsDifferent Constraints on Channel Count ; I/O vs Output rateSame TTC, SLINKSame fine clock skew 1 nsecOne board type in each system.No trigger functions.

    Minor differences, power supply, slink connectors, fpga config, vme monitor busDifferent PCB implementations - Motherboard vs Motherboard + MezzaninesMain Difference Digital Processing. (Altera vs Xilinx FPGAs) - Data Inputs. Raw & Synch vs ZS & Unsynch

  • FED LessonsGood Design and Robust Manufacturing.Design evolves in response to technology (ASICs in TDR) Invested a lot to get design right first time (2 board versions.)Protoype to production was a long process.Started at cutting edge finished with v. mature technology FPGAs (support)Cost estimates evolve ADCs, FPGAs, Manufacture. Got FPGAs right.Support of detector development v. underestimated , PMCs cf 9U FEDsPrototype support underestimated ~ 50 proto + pre-prodn 9U FEDsTender process takes a long time. (not needed for pxFED)Both ended up with local manufacturers. Good relationship essential.Quality Control critical. Early BGA failures. V. High production yield. (also pxFED) No problems ORx assemblyDoing board testing at Assembly Plant took effort but paid off- Need for Custom Test equipment Optical Testers

  • FED LessonsSystem interfaces came late. Electrical SLINK cards, FMMs. More elegant solutions.Choice of industry standard VME for mechanics, power was good oneVME bus as monitoring is poor , better Ethernet (late design change?)VME64x features not all used. (plug & play cost pxFED one unnecessary board iteration). Keep it simple.Think about practical issues cf prototypes with final system , FPGA configuration.Design issues with cooling. Tests in final configurations necessary.(Un)expected effects (temperature variation of optical inputs for pxFED encoding)-Boards are built, debugged and delivered. But Firmware is never finished.Custom protocols , SLINK, TTC, -> custom Firmware. Duplication of Firmware blocks (across CMS), SLINK, TTC, I2C, VME. Firmware Libraries? Commercial/VendorDuplication of test software? Software effort ? (costings)

  • Future FED Possible ImplementationFPGASwitchOff Detector sFEDSDRAMBufferSNAP 12Rear Transition ModuleSTTC10G SerialBackplaneDAQCrate Event Builder12 x 3 GbpsFEATCA Crate 8UCntrl/MonPowerORxFPGAsMGBTsGBT PHYMACSparsification1 per ORxORx and FPGA on Mezzanine?

    ORxORxORxORxORxORxORxMezzanine PrototypeGBTIndustry StandardsATCA cratesIndustry Protocols Data TransmissionSerial PCIe More use of Commercial Firmware cores. Data protocols, memory

    COTS Carrier Motherboards+ CMS Mezzanines,Transition cards

  • Future FED-FECIntegrate FEC functions on FED

    FPGASwitchOff Detector sFEDSDRAMBufferMPT 12Rear Transition ModuleSTTCTriggerThrottle10G SerialBackplaneDAQCrate Event Builder12 x 3 GbpssTTCFPGAsMGBTsGBT RecvMACZS1 per ORxsAPVORxORxORxORxORxOTxATCA Crate 8U Cntrl/MonEthernetPowerORxORx and FPGA on Mezzanine?Digital Inputs

    Zero Suppressed FE Data Inputs?Constraint Data Volumes on output

  • Final System IdeasNew sDAQ (sFEDs connected direct to Filter via Super Event Builder Network)New sTTC (Broadcasting Filter Addresses to FEDs)CratesJust Mechanics, Power, Cooling. -> Control/Monitoring via Ethernet.Serial Backplane based crates (Telecom ATCA , VME46?). Less Slots (but wider)Better Power & Cooling ?Better control & monitoring ?FED Event Builder Crate

  • Future FEDsCommon Tracker FED h/w probably technically feasible. Practical?Common CMS FED ? Common SLINK, Common FECGo to Digital Input DataZero Suppressed at FE tbdLarge systems channel counts. Large form factors (cost driven).Constraints on Channel count?Not considered Tracker Trigger

    Use of Emerging Industry Crate Standards e.g. Telecomms ATCA (VME)Exploit Industry Data Protocols e.g. Serial PCIe (SLINK)More use COTS Vendor Firmware cores, Industry standardsUse common COTS ATCA Carrier boards with custom CMS Mezzanines (cost effective)

  • Spare Slides

    outline of coverage

    time-plan- What is an FPGA- And why are they important for HEPquestions- any time