TPS92692 LED Controller with Spread Spectrum Frequency Modulation · Triangle wave spread spectrum...

VCTRL

TPS92692-Q1

VIN

VREF

FLT

SS

DM

RT

COMP

IMON

IADJ

DIM/PWM

VCC

GATE

IS

GND

SLOPE

OV

CSP

CSN

PDRV

RAMP

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9

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20

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VIN LED +

LED í�

L

CIN

CVREF

CSS

CDM

RT

CCOMP

CIMON

RADJ2

RADJ1RDIM2

RDIM1

RSLP

RIS

CVCC

ROV1

ROV2

COUT

CRAMP

RCS

QM

QDIMD

DDIM

PAD

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS92692, TPS92692-Q1SLVSDD9 –MARCH 2017

TPS92692, TPS92692-Q1 High Accuracy LED Controller WithSpread Spectrum Frequency Modulation

1

1 Features1• Wide Input Voltage: 4.5 V to 65 V• Better than ± 4% LED Current Accuracy over

–40°C to 150°C Junction Temperature Range• Spread Spectrum Frequency Modulation for

Improved EMI• Comprehensive Fault Protection Circuitry with

Current Monitor output and Open Drain Fault FlagIndicator

• Internal Analog Voltage to PWM Duty CycleGenerator for stand-alone Dimming Operation

• Compatible with Direct PWM Input with over1000:1 Dimming Range

• Analog LED Current Adjust Input (IADJ) with over15:1 Contrast Ratio

• Integrated P-Channel Driver to enable Series FETDimming and LED Protection

• TPS92692-Q1: Automotive Q100 Grade 1Qualified

2 Applications• TPS92692-Q1: Automotive Exterior Lighting

Applications• Driver Monitoring Systems (DMS)• LED General Lighting Applications• Exit Signs and Emergency Lighting

3 DescriptionThe TPS92692 and TPS92692-Q1 are high accuracypeak current mode based controllers designed tosupport step-up/down LED driver topologies. Thedevice incorporates a rail-to-rail current amplifier tomeasure LED current and spread spectrum frequencymodulation technique for improved EMI performance.

This high performance LED controller canindependently modulate LED current using eitheranalog or PWM dimming techniques. Linear analogdimming response with over 15:1 range is obtainedby varying the voltage across the high impedanceanalog adjust (IADJ) input. PWM dimming of LEDcurrent is achieved by directly modulating theDIM/PWM input pin with the desired duty cycle or byenabling the internal PWM generator circuit. ThePWM generator translates the DC voltage atDIM/PWM pin to corresponding duty cycle bycomparing it to the internal triangle wave generator.The optional PDRV gate driver output can be used todrive an external P-Channel series MOSFET.

The TPS92692 and TPS92692-Q1 devices supportcontinuous LED status check through the currentmonitor (IMON) output. The devices also include anopen drain fault indicator output to indicate LEDovercurrent, output overvoltage and outputundervoltage conditions.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)TPS92692-Q1

HTSSOP (20) 5.10 mm × 6.60 mmTPS92692

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

4 Typical Boost LED Driver

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2

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Product Folder Links: TPS92692 TPS92692-Q1

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Typical Boost LED Driver...................................... 15 Revision History..................................................... 26 Pin Configuration and Functions ......................... 37 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 47.2 ESD Ratings.............................................................. 57.3 Recommended Operating Conditions....................... 57.4 Thermal Information .................................................. 57.5 Electrical Characteristics........................................... 67.6 Typical Characteristics .............................................. 9

8 Detailed Description ............................................ 138.1 Overview ................................................................. 138.2 Functional Block Diagram ....................................... 14

8.3 Feature Description................................................. 158.4 Device Functional Modes........................................ 22

9 Application and Implementation ........................ 259.1 Application Information............................................ 259.2 Typical Applications ................................................ 34

10 Power Supply Recommendations ..................... 4611 Layout................................................................... 47

11.1 Layout Guidelines ................................................. 4711.2 Layout Example .................................................... 48

12 Device and Documentation Support ................. 4912.1 Related Links ........................................................ 4912.2 Community Resources.......................................... 4912.3 Trademarks ........................................................... 4912.4 Electrostatic Discharge Caution............................ 4912.5 Glossary ................................................................ 49

13 Mechanical, Packaging, and OrderableInformation ........................................................... 49

5 Revision History

DATE REVISION NOTESMarch 2017 * Initial release.



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1

2

3

4

5

6

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19

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17

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Thermal Pad

VIN

VREF

FLT

SS

DM

RT

COMP

IMON

VCC

GATE

IS

GND

SLOPE

OV

CSP

CSN

9IADJ

10DIM/PWM

12

11

PDRV

RAMP

3

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6 Pin Configuration and Functions

PWP Package20-Pin HTSSOP with PowerPAD™

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

COMP 7 I/O Transconductance error amplifier output. Connect compensation network to achieve desired closed-loop response.

CSN 13 I Current sense amplifier negative input (–). Connect directly to the negative node of LED currentsense resistor, RCS.

CSP 14 I Current sense amplifier positive input (+). Connect directly to the positive node of LED currentsense resistor, RCS.

DIM/PWM 10 I

External analog to PWM dimming command or direct PWM dimming input. The external analogdimming command between 1 V and 3 V is compared to the internal PWM generator trianglewaveform to set LED current duty cycle between 0% and 100%. With PWM generator disabled, adirect PWM dimming command can be applied to control the LED current duty cycle and frequency.The analog or PWM command is used to generate an internal PWM signal that controls the GATEand PDRV outputs. Setting the internal PWM signal to logic level low, turns off switching, idles theoscillator, disconnects the COMP pin, and sets PDRV to VCSP. Connect to VREF when not used forPWM dimming.

DM 5 I/OTriangle wave spread spectrum modulation frequency, fm, programming pin. Connect a capacitor toGND to set the spread spectrum modulating frequency. Connect directly to GND to disable spreadspectrum modulation of switching frequency.

FLT 3 OOpen-drain fault indicator. Connect to VREF with a resistor to create active low fault signal output.Internal LED short circuit protection and auto-restart timer can enabled by directly connecting thepin to SS input.

GATE 19 O N-channel MOSFET gate driver output. Connect to gate of external main switching N-channelMOSFET.

GND 17 — Analog and Power ground connection pin. Connect to circuit ground to complete return path.

IADJ 9 I

LED current reference input. Connect this pin to VCC with a 100-kΩ series resistor to set theinternal reference voltage to 2.42 V and the current sense threshold, V(CSP-CSN) to 170.7 mV. Thepin can be modulated by an external voltage source from 140 mV to 2.25 V to implement analogdimming.

IMON 8 O LED current report pin. The LED current sensed by CSP/CSN input is reported as VIMON = 14 × ILED× RCS. Bypass with a 1-nF ceramic capacitor connected to GND.

IS 18 I Switch current sense input. Connect to the switch sense resistor, RIS to set the switch current limitthreshold based on the internal 250 mV reference.

OV 15 I Output voltage input. Connect a resistor divider from output voltage to GND to set outputovervoltage and under-voltage protection thresholds.

PDRV 12 O Series dimming P-channel FET gate driver output. Connect to gate of external P-channel MOSFETto implement series FET PWM dimming and fault disconnect.



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4




Pin Functions (continued)PIN

I/O DESCRIPTIONNAME NO.

RAMP 11 I/O

Programming input for internal PWM generator. Connect a capacitor to GND to set the trianglewave frequency for PWM generator circuit. Connect a 249-kΩ resistor to GND to disable the PWMgenerator and to set a fixed reference for direct external PWM dimming input. Do not allow this pinto float.

RT 6 I/OOscillator frequency programming pin. Connect a resistor to GND to set the switching frequency.The internal oscillator can be synchronized by coupling an external clock pulse through a seriescapacitor with a value of 100 nF.

SLOPE 16 I/O Slope compensation input. Connect a resistor to GND to set the desired slope compensation rampbased on inductor value, input and output voltages.

SS 4 I/O Soft-start programming pin. Connect a capacitor to GND to extend the start-up time. Switching canbe disabled by shorting this pin to GND.

VCC 20 — VCC (7.5 V) bias supply pin. Locally decouple to GND using a ceramic capacitor (with a valuebetween 2.2-µF and 4.7-µF). Locate close to the controller.

VIN 1 — Input supply for the internal regulators. Bypass with a low-pass filter using a series 10-Ω resistorand 10- nF capacitor connected to GND. Locate the capacitor close to the controller.

VREF 2 — VREF (5 V) bias supply pin. Locally decouple to GND using a ceramic capacitor (with a valuebetween 2.2-µF and 4.7-µF) located close to the controller.

Thermal Pad — The GND pin must be connected to the exposed thermal pad for proper operation. This PowerPADmust be connected to PCB ground plane using multiple vias for good thermal performance.

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND unless otherwise noted(3) Continuous sustaining voltage(4) All output pins are not specified to have an external voltage applied.

7 Specifications

7.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1) (2)

MIN MAX UNIT

Input voltage

VIN, CSP, CSN –0.3 65 VDIM/PWM –0.3 14 VIS, RT, FLT –0.3 8.8 VOV, SS, RAMP, DM, SLOPE, VREF, IADJ –0.3 5.5 VCSP to CSN (3) –0.3 0.3 V

Output voltage (4)

VCC, GATE –0.3 8.8 VPDRV VCSP – 8.8 VCSP VCOMP –0.3 5.0 V

Source currentIMON — 100 µAGATE (pulsed < 20 ns) — 500 mAPDRV (pulsed < 10 µs) — 50 mA

Sink currentGATE (pulsed < 20 ns) — 500 mAPDRV (pulsed < 10 µs) — 50 mA

Operating junction temperature, TJ –40 150 °CStorage temperature, Tstg 165 °C



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5




(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD RatingsVALUE UNIT

TPS92692-Q1 IN PWP (HTSSOP) PACKAGE

V(ESD)Electrostaticdischarge

Human-body model (HBM), per AEC Q100-002, all pins (1) ±2000V

Charged-device model (CDM), per AEC Q100-011All pins except 1, 10, 11, and 20 ±500Pins 1, 10, 11, and 20 ±750

TPS92692 IN PWP (HTSSOP) PACKAGE

V(ESD)Electrostaticdischarge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2) ±2000V

Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (3) ±500

7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITVIN Supply input voltage 6.5 14 65 VVIN, crank Supply input, battery crank voltage 4.5 VVCSP, VCSN Current sense common mode 6.5 60 VƒSW Switching frequency 80 800 kHzƒm Spread spectrum modulation frequency 0.1 12 kHzfRAMP Internal PWM ramp generator frequency 100 2000 HzVIADJ Current reference voltage 0.14 VIADJ(CLAMP) VTA Operating ambient temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

7.4 Thermal Information

THERMAL METRIC (1)TPS92692 TPS92692-Q1

UNITPWP (HTSSOP) PWP (HTSSOP)20 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance 40.8 40.8 °C/WRθJC(top) Junction-to-case (top) thermal resistance 26.1 26.1 °C/WRθJB Junction-to-board thermal resistance 22.2 22.2 °C/WψJT Junction-to-top characterization parameter 0.8 0.8 °C/WψJB Junction-to-board characterization parameter 22.0 22.0 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 2.3 °C/W



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(1) All voltages are with respect to GND unless otherwise noted

7.5 Electrical Characteristics–40°C ≤ TJ ≤ 150°C, VIN = 14 V, VIADJ = 2.1 V, VRAMP = 500 mV, VDIM/PWM = 3 V, VOV = 500 mV, CVCC = 1 µF, CVREF = 1 µF,CCOMP = 2.2 nF, RCS = 100 mΩ, RT = 20 kΩ, no load on GATE and PDRV (unless otherwise noted) (1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITINPUT VOLTAGE (VIN)IIN(STBY) Input stand-by current VPWM = 0 V 1.8 2.5 mAIIN(SW) Input switching current VCC = 7.5 V, CGATE = 1 nF 5.1 6.6 mABIAS SUPPLY (VCC)VCC(REG) Regulation voltage No load 7.0 7.5 8.0 V

VCC(UVLO) Supply undervoltage protectionVCC rising threshold, VIN = 8 V 4.5 4.9 VVCC falling threshold, VIN = 8 V 3.7 4.1 VHysteresis 400 mV

ICC(LIMIT) Supply current limit VCC = 0 V 30 36 46 mAVDO LDO dropout voltage ICC = 20 mA, VIN = 5 V 300 mVREFERENCE VOLTAGE (VREF)VREF Reference voltage No load 4.77 4.96 5.15 VIREF(LIMIT) Current limit VREF = 0 V 30 36 46 mAOSCILLATOR (RT)

ƒSW Switching frequencyRT = 40 kΩ 175 200 225 kHzRT = 20 kΩ 341 390 439 kHz

VRT RT output voltage 1 V

VSYNCSYNC rising threshold VRT rising 2.5 3.1 VSYNC falling threshold VRT falling 1.8 2 V

tSYNC(MIN) Minimum SYNC clock pulse width 100 nsSPREAD SPECTRUM FREQUENCY MODULATION (DM)

IDM

Triangle wave generator sink current 10 µATriangle wave generator sourcecurrent 10 µA

VDM(TR)Triangle wave voltage peak (High) 1.15 VTriangle wave voltage valley (Low) 850 mV

VDM(EN)Spread spectrum modulation enablethreshold 700 mV

VDM(CLAMP) Internal clamp voltage VPWM = 0 V, RRAMP = 200 kΩ 1.25 VGATE DRIVER (GATE)RGH Gate driver high side resistance IGATE = –10 mA 5.4 11.2 Ω

RGL Gate driver low side resistance IGATE = 10 mA 4.3 10.5 Ω

CURRENT SENSE (IS)

VIS(LIMIT) Current limit thresholdVDIM/PWM = 5 V, RRAMP = 249 kΩ 230.6 250 270 mVVDIM/PWM = 0 V, RRAMP = 249 kΩ 665 700 735 mV

tIS(BLANK) Leading edge blanking time 88 118 158 nstIS(FAULT) Current limit fault time 35 µstILMT(DLY) IS to GATE propagation delay VIS pulsed from 0 V to 1 V 78 ns



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7




Electrical Characteristics (continued)–40°C ≤ TJ ≤ 150°C, VIN = 14 V, VIADJ = 2.1 V, VRAMP = 500 mV, VDIM/PWM = 3 V, VOV = 500 mV, CVCC = 1 µF, CVREF = 1 µF,CCOMP = 2.2 nF, RCS = 100 mΩ, RT = 20 kΩ, no load on GATE and PDRV (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITPWM COMPARATOR AND SLOPE COMPENSATION (SLOPE)DMAX Maximum duty cycle 90 %VSLOPE Adaptive slope compensation VCSP = 24 V 410 mV

VSLOPE(MIN)Minimum slope compensation outputvoltage VCSP = 0 V 72 mV

VLV IS to COMP level shift voltage No slope compensation added 1.42 1.60 1.82 VILV IS level shift bias current No slope compensation added 17 µACURRENT SENSE AMPLIFIER (CSP, CSN)

V(CSP-CSN) Current sense thresholdsVCSP = 14 V, VIADJ = 3 V 163.4 170.7 177.6 mVVCSP = 14 V, VIADJ = 1.4 V 95.83 100.5 103.85 mV

CS(BW) Current sense unity gain bandwidth 500 kHzGCS Current sense amplifier gain G = VIADJ/V(CSP-CSN) 14

K(OCP)Ratio of over-current detectionthreshold to analog adjust voltage K (OCP) = V(OCP-THR)/VIADJ 1.46 1.5 1.61

ICSP(BIAS) CSP bias current VCSN = 14.1 V, VCSP = 14 V 107 µAICSN(BIAS) CSN bias current VCSN = 14.1 V, VCSP = 14 V 110 µAFAULT INDICATOR (FLT)R(FLT) Open-drain pull down resistance 241 Ω

t(FAULT_TMR) Fault timer 24 36 48 msCURRENT MONITOR (IMON)

IIMON(SRC) IMON source current V(CSP-CSN) = 150 mV,VIMON = 0 V 144 µA

VIMON(CLP) IMON output voltage clamp 3.2 3.7 4.2 VVIMON(OS) IMON buffer offset voltage –7.2 0 8.5 mVANALOG ADJUST (IADJ)VIADJ(CLP) IADJ internal clamp voltage IIADJ = 1 µA 2.29 2.40 2.55 VIIADJ(BIAS) IADJ input bias current VIADJ < 2.2 V 10.5 nARIADJ(LMT) IADJ current limiting series resistor VIADJ > 2.6 V 12 kΩERROR AMPLIFIER (COMP)gM Transconductance 121 µA/VICOMP(SRC) COMP current source capacity VIADJ = 1.4 V, V(CSP-CSN) = 0 V 130 µAICOMP(SINK) COMP current sink capacity VIADJ = 0 V, V(CSP-CSN) = 0.1 V 130 µAEA(BW) Error amplifier bandwidth Gain = –3 dB 5 MHzVCOMP(RST) COMP pin reset voltage 100 mVRCOMP(DCH) COMP discharge FET resistance 246 Ω

SOFT-START (SS)ISS Soft-start source current 7 10 12.8 µA

VSS(UVP_EN)Soft-start voltage threshold to enableoutput under-voltage protection 2.4 V

VSS(RST) Soft-start pin reset voltage 50 mVRSS(DCH) SS discharge FET resistance 240 Ω

OUTPUT VOLTAGE INPUT (OV)VOVP(THR) Overvoltage protection threshold 1.195 1.228 1.262 VVUVP(THR) Undervoltage protection threshold 81.7 100 115.1 mV

t(UVP-BLANK)Undervoltage protection blankingperiod 4 µs

IOVP(HYS) OVP hysteresis current 12 20 27.5 µA



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8




Electrical Characteristics (continued)–40°C ≤ TJ ≤ 150°C, VIN = 14 V, VIADJ = 2.1 V, VRAMP = 500 mV, VDIM/PWM = 3 V, VOV = 500 mV, CVCC = 1 µF, CVREF = 1 µF,CCOMP = 2.2 nF, RCS = 100 mΩ, RT = 20 kΩ, no load on GATE and PDRV (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITINTERNAL PWM RAMP GENERATOR (RAMP)

IRAMPRamp generator source current 7.75 10 12.73 µARamp generator sink current 8.24 10 12.41 µA

VRAMPRamp signal peak (high) 3 VRamp signal valley (low) 1 V

PWM INPUT (DIM/PWM)

VPWM(HIGH)Schmitt trigger logic level (highthreshold) VRAMP = 2.0 V 2.0 2.2 V

VPWM(LOW)Schmitt trigger logic level (lowthreshold) VRAMP = 2.0 V 1.8 2.0 V

RPWM(PD) PWM pull-down resistance 10 MΩ

tDLY(RISE) PWM rising to PDRV delay CPDRV = 1 nF 294 nstDLY(FALL) PWM falling to PDRV delay CPDRV = 1 nF 326 nsSERIES P-CHANNEL PWM FET GATE DRIVE OUTPUT (PDRV)VPDRV(OFF) P-channel gate driver off-state voltage VCSP = 14 V 14 VVPDRV(ON) P-channel gate driver on-state voltage VCSP = 14 V 7.4 VIPDRV(SRC) PDRV sink current Pulsed 50 mARPDRV(L) PDRV driver pull up resistance 82 Ω

THERMAL SHUTDOWNTSD Thermal shutdown temperature 175 °CTSD(HYS) Thermal shutdown hysteresis 25 °C



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Junction Temperature (oC)

VC

C U

nder

volta

ge L

ocko

ut T

hres

hold

s (V

)

-40 -20 0 20 40 60 80 100 120 140 1603.85

3.95

4.05

4.15

4.25

4.35

4.45

4.55

4.65

4.75

4.85

D004

RisingFalling

Frequency (kHz)

RT (

k:)

50 150 250 350 450 550 650 750 80010

20

30

40

50

607080

100

D005


VC

C D

ropo

ut V

olta

ge (

mV

)

-40 -20 0 20 40 60 80 100 120 140 160100

200

300

400

500

600

D002 Junction Temperature (oC)

VC

C C

urre

nt L

imit

(mA

)

-40 -20 0 20 40 60 80 100 120 140 16030

32

34

36

38

40

42

44

D003


VC

C R

egul

atio

n V

olta

ge (

V)

-40 -20 0 20 40 60 80 100 120 140 1607.46

7.47

7.48

7.49

7.5

7.51

7.52

7.53

7.54


Ref

eren

ce V

olta

ge (

V)

-40 -20 0 20 40 60 80 100 120 140 1604.935

4.94

4.945

4.95

4.955

4.96

4.965

4.97

4.975

D020

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7.6 Typical CharacteristicsTA = 25°C, VIN = 14 V, VIADJ = 2.2 V, CVCC = 1 µF, CCOMP = 2.2 nF, RCS = 100 mΩ, RT = 20 kΩ, VPWM = 5 V, no load on GATEand PDRV (unless otherwise noted)

Figure 1. VCC Regulation Voltage vs Junction Temperature Figure 2. VREF Reference Voltage vs Junction Temperature

VIN = 5 V, IVCC= 20 mA

Figure 3. VCC Dropout Voltage vs Junction Temperature

Figure 4. VCC Current Limit vs Junction Temperature

Figure 5. VCC UVLO Threshold vs Junction Temperature Figure 6. Timing Resistance (RT) vs Switching Frequency



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VCSP (V)

V(C

SP

-CS

N) T

hres

hold

(m

V)

0 5 10 15 20 25 30 35 40 45 50 55 60 65169.8

170

170.2

170.4

170.6

170.8

171

171.2


V(C

SP

-CS

N) T

hres

hold

(m

V)

-40 -20 0 20 40 60 80 100 120 140 160168

169

170

171

172

173

174

D011


IS C

urre

nt L

imit

Thr

esho

ld (

mV

)

-40 -20 0 20 40 60 80 100 120 140 160248.5

249

249.5

250

250.5

251


Lead

ing

Edg

e B

lank

ing

Per

iod

(ns)

-40 -20 0 20 40 60 80 100 120 140 160105

110

115

120

125

130

135

D009


Sw

itchi

ng F

requ

ency

(kH

z)

-40 -20 0 20 40 60 80 100 120 140 160382

384

386

388

390

392

394

396

398


Max

imum

Dut

y C

ycle

(%

)

-40 -20 0 20 40 60 80 100 120 140 16089.7

89.8

89.9

90

90.1

90.2

90.3

D007

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Typical Characteristics (continued)TA = 25°C, VIN = 14 V, VIADJ = 2.2 V, CVCC = 1 µF, CCOMP = 2.2 nF, RCS = 100 mΩ, RT = 20 kΩ, VPWM = 5 V, no load on GATEand PDRV (unless otherwise noted)

RT= 20 kΩ

Figure 7. Switching Frequency vs Junction Temperature

Figure 8. Maximum Duty Cycle vs Junction Temperature

Figure 9. Current Limit Threshold vs Junction Temperature Figure 10. Leading Edge Blanking Period vs JunctionTemperature

VIADJ> 2.6 V

Figure 11. V(CSP-CSN) Threshold vs VCSP Voltage

VIADJ> 2.6 V

Figure 12. V(CSP-CSN) Threshold vs Junction Temperature



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VIADJ (V)

V(C

SP

-CS

N) T

hres

hold

(m

V)

0 0.28 0.56 0.84 1.12 1.4 1.68 1.96 2.24 2.52 2.8 30

20

40

60

80

100

120

140

160

180

200


IAD

J V

olta

ge C

lam

p (V

)

-40 -20 0 20 40 60 80 100 120 140 1602.395

2.396

2.397

2.398

2.399

2.4

2.401

2.402

2.403

D017

V(CSP-CSN) (mV)

VIM

ON (

V)

0 30 60 90 120 150 180 210 240 270 3000

0.5

1

1.5

2

2.5

3

3.5

4

D014 Junction Temperaure (oC)

IMO

N O

utpu

t Vol

tage

Cla

mp

(V)

-40 -20 0 20 40 60 80 100 120 140 1603.64

3.66

3.68

3.7

3.72

3.74

3.76

D015


V(C

SP

-CS

N) T

hres

hold

(m

V)

-40 -20 0 20 40 60 80 100 120 140 16099

99.25

99.5

99.75

100

100.25

100.5

100.75

101


Bia

s C

urre

nt (P

A)

-40 -20 0 20 40 60 80 100 120 140 16095

100

105

110

115

120

125

D013

CSPCSN

11





VIADJ= 1.4 V

Figure 13. V(CSP-CSN) Threshold vs Junction Temperature

VCSP= VCSN = 14 V

Figure 14. CSP/CSN Input Bias Current vs JunctionTemperature

Figure 15. VIMON vs V(CSP-CSN) Figure 16. VIMON(CLP) vs Junction Temperature

Figure 17. V(CSP-CSN) Threshold vs VIADJ Figure 18. VIADJ Voltage Clamp vs Junction Temperature



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OV

P D

etec

tion

Thr

esho

ld (

V)

-40 -20 0 20 40 60 80 100 120 140 1601.222

1.223

1.224

1.225

1.226

1.227

1.228

1.229

1.23

1.231

1.232


OV

P H

yste

resi

s C

urre

nt (P

A)

-40 -20 0 20 40 60 80 100 120 140 16019

19.2

19.4

19.6

19.8

20

20.2

20.4

20.6

20.8

21

D019

12





Figure 19. OVP Detection Threshold vs JunctionTemperature

Figure 20. OVP Hysteresis Current vs Junction Temperature



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13




8 Detailed Description

8.1 OverviewThe TPS92692 and TPS92692-Q1 devices feature all of the functions necessary to implement a compact LEDdriver based on step-up or step-down power converter topologies. The devices implement a fixed-frequency,peak current mode control technique to achieve constant output current and fast transient response. Theintegrated low offset, rail-to-rail current sense amplifier provides the flexibility required to power a single stringconsisting of 1 to 20 series connected LEDs while maintaining better than 4% current accuracy over theoperating temperature range. The LED current regulation threshold is set by the analog adjust input, IADJ andcan be externally programmed to implement analog dimming with over 15:1 linear dimming range. The highimpedance IADJ input simplifies LED current binning and thermal protection.

The TPS92692 and TPS92692-Q1 devices incorporate an internal PWM generator that can be programmed toimplement pulse width modulation (PWM) dimming of LED current. The PWM duty cycle can be varied from 0%to 100% by modulating the analog voltage on DIM/PWM input from 1 V to 3 V. The PWM dimming frequency isexternally programmable and is set by the capacitor connected to RAMP input. As an alternative, the TPS92692and TPS92692-Q1 devices can also be configured to implement direct PWM dimming based on the duty cycle ofexternal PWM signal by connecting a 249-kΩ resistor across RAMP pin and GND. The internal PWM signalcontrols the GATE and PDRV outputs which control the external n-channel switching FET and p-channeldimming FET connected in series with LED string, respectively.

The current monitor output, IMON, reports the instantaneous status of LED current measured by the rail-to-railcurrent sense amplifier. This feature indicates instantaneous current as a result of LED short circuit and cableharness failure, independent of LED driver topology. An open-drain fault indicator is also provided to report faultsincluding cycle-by-cycle current limit, output overvoltage, and output undervoltage conditions. LED driverprotection with auto-restart (hiccup) mode is enabled by connecting the fault pin (FLT) to the SS pin. Otherprotection features include VCC undervoltage protection and thermal shutdown. A remote signal can force thedevice in to shutdown by pulling down on the SS pin.



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Standby

7.5 V LDO Regulator

UVLO (4.1 V)

Thermal Limit

Internal References

Clock

Oscillator

+

+

+

SS

Max Duty

10 �A

+

+

LEB

LEB

+

1.23 V

36 ms

Timer

10 �A

20 �A

Fau

lt

CSP

VIN

RT

SS

DIM/PWM

COMP

CSP

CSN

IMON

IADJ

GND

GATE

VCC

OV

IS

PDRV

Standby

8 k �

Fault

PWMComp

3.7 V

+

2.4 V

12 k �

Fault

Reset Logic

50 mV100 mV

Current Sense Amplifier

Gain = 14

+

VREF5 V LDO Regulator

Slope Generator

SLOPE

Triangle Wave Generator

RAMP

Spread Spectrum Modulator

DM

7 V

100 �A

OvercurrentDetector

Fault

700 mV

250 mV

S0

S1

PWM

FLT

3 V

1 V VIN CSP1.4 V

+

OvervoltageFault

100 mV

Undervoltage Fault

Undervoltage Fault

+2.4 V SS_DONE

SS_DONE

35 �s

Timer

PWM

PWM

QS

R

14




8.2 Functional Block Diagram



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OscillatorRT

CSYNCRT

ClockfSYNC

� ��

10

T 1.047SW

1.432 10R

f

u :

15




8.3 Feature Description

8.3.1 Internal Regulator and Undervoltage Lockout (UVLO)The device incorporates a 65-V input voltage rated linear regulators to generate the 7.5 V (typ) VCC bias supply,the 5 V (typ) VREF reference supply and other internal reference voltages. The device monitors the VCC output toimplement UVLO protection. Operation is enabled when VCC exceeds the 4.5-V (typ) threshold and is disabledwhen VCC drops below the 4.1-V (typ) threshold. The UVLO comparator provides 400 mV of hysteresis to avoidchatter during transitions. The UVLO thresholds are internally fixed and cannot be adjusted. An internal currentlimit circuit is implemented to protect the device during VCC pin short-circuit conditions. The VCC supply powersthe internal circuitry and the N-channel gate driver output, GATE. Place a bypass capacitor in the range of 2.2 µFto 4.7 µF across the VCC output and GND to ensure proper operation. The regulator operates in dropout wheninput voltage VIN falls below 7.5 V forcing VCC to be lower than VIN by 300 mV for a 20-mA supply current. TheVCC is a regulated output of the internal regulator and is not recommended to be driven from an external powersupply.

The VREF supply is internally used to generate voltage thresholds for the RAMP generator circuit and to powersome digital circuits. This supply can be used in conjunction with a resistor divider to set voltage levels for theIADJ pin and DIM/PWM pin to set LED current and PWM dimming duty cycle. It can also be used to biasexternal circuitry requiring a reference supply. The supply current is internally limited to protect the device fromoutput overload and short-circuit conditions. Place a bypass capacitor in the range of 2.2 µF to 4.7 µF across theVREF output to GND to ensure proper operation.

The TPS92692 and TPS92692-Q1 devices incorporate features that simplify compliance with the CISPR andautomotive EMI requirements. The devices have optional spread spectrum frequency modulation circuit that canbe externally configured to reduce peak and average conducted and radiated EMI. The internal programmableoscillator has a range of 80 kHz to 800 kHz and can be tuned based on the EMI requirements. The devices areavailable in HTSSOP-20 package with an exposed pad to aid in thermal dissipation.

8.3.2 OscillatorThe switching frequency is programmable by a single external resistor connected between the RT pin and GND.To set a desired frequency, ƒSW (Hz), the resistor value can be calculated from Equation 1.

(1)

Figure 6 shows a graph of switching frequency versus resistance, RT. TI recommends a switching frequencysetting between 80 kHz and 700 kHz for optimal performance over input and output voltage operating range andfor best efficiency. Operation at higher switching frequencies requires careful selection of N-channel MOSFETcharacteristics as well as detailed analysis of switching losses.

Figure 21. Oscillator Synchronization Through AC Coupling

The internal oscillator can be synchronized by AC coupling an external clock pulse to RT pin as shown inFigure 21. The positive going synchronization clock at the RT pin must exceed the RT sync threshold and thenegative going synchronization clock at the RT pin must exceed the RT sync falling threshold to trip the internalsynchronization pulse detector. TI recommends that the frequency of the external synchronization pulse is within±20% of the internal oscillator frequency programmed by the RT resistor. TI recommends a minimum couplingcapacitor of 100 nF and a typical pulse width of 100 ns for proper synchronization. In the case where externalsynchronization clock is lost the internal oscillator takes control of the switching rate based on the RT resistor tomaintain output current regulation. The RT resistor is always required whether the oscillator is free running orexternally synchronized.



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GATE

GND

CVCC

VCC

GATE_IN

+

+

0.85 V

1.15 V

10 �A

10 �A

CDM

1 V

1.15 V

0.85 V

DM QS

R

DMMOD

10 AC (F)

2 f 0.3 VP

u u

16




Feature Description (continued)8.3.3 Spread Spectrum Frequency ModulationThe TPS92692 and TPS92692-Q1 devices provide a frequency dithering option that is enabled by connecting acapacitor from the DM pin to GND. A triangle waveform centered at 1 V is generated across the CDM capacitor.The triangle waveform modulates the oscillator frequency by ± 15% of the nominal frequency set by an externaltiming resistor, RT. The CDM capacitance value sets the rate of the low frequency modulation. To achievemaximum attenuation in average EMI scan set modulation frequency ranging from 100 Hz to 1.2 kHz. The lowmodulating frequency has little impact on the quasi-peak EMI scan. Set the modulation frequency to 10 KHz orhigher to achieve attenuation for quasi-peak EMI measurements. The modulation frequency higher than thereceiver resolution bandwidth (RBW) of 9 kHz only impacts the quasi-peak EMI scan and has little impact on theaverage measurement. The device simplifies EMI compliance by providing the means to tune the modulationfrequency based on measured EMI signature. Equation 2 calculates the CDM capacitance required to set themodulation frequency, fMOD (Hz).

(2)

Figure 22. Frequency Dither Operation

Connect the DM pin to GND to disable frequency dither circuit operation. Internal frequency dithering is notsupported when the devices are synchronized based on an external clock signal.

8.3.4 Gate DriverThe TPS92692 and TPS92692-Q1 devices contain a N-channel gate driver that switches the output VGATEbetween VCC and GND. A peak source and sink current of 500 mA allows controlled slew-rate of the MOSFETgate and drain node voltages, limiting the conducted and radiated EMI generated by switching.

Figure 23. Push-Pull N-Channel Gate Driver Circuit



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+

CFDM

RFS

RFS

RCS

CFCMCFCM

CSP

CSN

Common Mode Filter Capacitors

Differential Mode Filter Capacitor

CC(GATE) G SWI Q f u

17




Feature Description (continued)The gate driver supply current ICC(GATE) depends on the total gate drive charge (QG) of the MOSFET and theoperating frequency of the converter, ƒSW, . Choose a MOSFET with a low gate chargespecification to limit the junction temperature rise and switch transition losses.

It is important to consider the MOSFET threshold voltage when operating in the dropout region when the inputvoltage, VIN, is below the VCC regulation level. TI recommends a logic level device with a threshold voltage below5 V when the device is required to operate at an input voltage less than 7 V.

8.3.5 Rail-to-Rail Current Sense AmplifierThe internal rail-to-rail current sense amplifier measures the average LED current based on the differentialvoltage drop between the CSP and CSN inputs over a common mode range of 0 V to 65 V. The differentialvoltage, V(CSP-CSN), is amplified by a voltage-gain factor of 14 and is connected to the negative input of thetransconductance error amplifier. Accurate LED current feedback is achieved by limiting the cumulative inputoffset voltage, (represented by the sum of the voltage-gain error, the intrinsic current sense offset voltage, andthe transconductance error amplifier offset voltage) to less than 5 mV over the recommended common-modevoltage, and temperature range.

Figure 24. Current Sense Amplifier Input Filter Options

An optional common-mode or differential mode low-pass filter implementation, as shown in Figure 24, can beused to smooth out the effects of large output current ripple and switching current spikes caused by diodereverse recovery. TI recommends a filter resistance in the range of 10 Ω to 100 Ω to limit the additional offsetcaused by amplifier bias current mismatch to achieve the best accuracy and line regulation.

8.3.6 Transconductance Error AmplifierThe internal transconductance amplifier generates an error signal proportional to the difference between the LEDcurrent sense feedback voltage and the external IADJ input voltage. The output of the error amplifier isconnected to an external compensation network to achieve closed-loop LED current regulation. In most LEDdriver applications a simple integral compensation circuit consisting of a capacitor connected from COMP outputto GND provides a stable response over wide range of operating conditions. TI recommends a capacitor valuebetween 10 nF and 100 nF as a good starting point. To achieve higher closed-loop bandwidth a proportional-integral compensator, consisting of a series resistor and a capacitor network connected across the COMP outputand GND, is required. Based on the converter topology, tune the compensation network to achieve a minimum of60° of phase margin and 10 dB of gain margin. The Application and Implementation section includes asummarized detailed design procedure.



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� �� CSP O6SL

SW SLP

0.494 V V 1V 278 10 D

f R

u � � u u u

u

L(PK)IS

250mVI (A)

R

+ IS

700 mV

250 mV

S0

S1

35 �s

TIMER

PWM

150 nsLEBILIM

ILIMComparator

18




Feature Description (continued)8.3.7 Switch Current SenseThe IS input pin monitors the main MOSFET current to implement peak current mode control. The GATE outputduty cycle is derived by comparing the peak switch current, measured by the RIS resistor, to the internal COMPvoltage threshold. An internal slope signal, VSL, generated by slope compensation circuit is added to themeasured sense voltage, VIS, to prevent subharmonic oscillations for duty cycles greater than 50%. An internalblanking circuit prevents MOSFET switching current spike propagation and premature termination of duty cycleby internally shunting the IS input for 150 ns after the beginning of the new switching period. For additional noisesuppression connect an external low-pass RC filter with resistor values ranging from 100 Ω to 500 Ω and a 1000pF capacitor. The external RC filter ensures proper operation when operating in the dropout region (VIN less than7 V).

Figure 25. Switch Current Limit Circuit

Cycle-by-cycle current limit is accomplished by a redundant internal comparator. The current limit threshold is setbased on the status of internal PWM signal. The current limit threshold is set to 250 mV (typ) when PWM signalis high and to 700 mV (typ) when PWM signal is low. The transition between the two thresholds work inconjunction with slope compensation and the error amplifier circuit to allow for higher inductor currentimmediately after the PWM transition and to improve LED current transient response during PWM dimming.Refer to the DIM/PWM Input section for details on PWM Dimming operation.

The device immediately terminates the GATE and PDRV output when the IS input voltage, VIS, exceeds thethreshold value. Upon a current limit event, the SS and COMP pin are internally grounded to reset the state ofthe controller. The GATE output is enabled after the expiration of the 35-µs internal fault timer and a new start-upsequence is initiated through the SS pin. Equation 3 calculates the peak inductor current in the current limit.

(3)

8.3.8 Slope CompensationPeak current mode based regulators are subject to sub-harmonic oscillations for duty cycle greater than 50%. Toavoid this instability problem, the control scheme is modified by the addition of an artificial ramp to the sensedswitch current waveform. The slope of the artificial ramp required is dependent on the input voltage, VIN, outputvoltage, VO, inductor, L, and switch current sense resistor, RIS. The devices incorporate an adaptive slopecompensation technique that modifies the slope of the artificial ramp generated based on the input voltage, VINand output voltage measured at CSP pin, VCSP, thus greatly simplifying the design for common LED drivertopologies, such as boost, buck-boost, and boost-to-battery. The magnitude of the internal ramp signal can becalculated as follows:

where• D is the converter duty cycle (4)



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DIMPWM(INT)

V 1D

2

�

DIMDIM

10 Af (Hz)

2 2 V CP

u u

VREF

IADJ

RADJ2

RADJ1

VREF

IADJ

RADJ2

RNTC

ÅW��

IADJRADJ

CADJPWM Signal

19




Feature Description (continued)The resistor, RSLOPE provides the flexibility to set the slope of the internal artificial ramp based on the inductancevalue, L and the LED driver topology. The Application and Implementation section includes detailed calculationsfor the resistor, RSLOPE, based on the LED driver topology. The SLOPE pin cannot be left floating.

8.3.9 Analog Adjust InputThe voltage across the LED current sense resistor, V(CSP–CSN), is regulated to the analog adjust input voltage,VIADJ, scaled by the current sense amplifier voltage gain of 14. The LED current can be linearly adjusted byvarying the voltage on IADJ pin from 140 mV to 2.25 V using either a resistor divider from VREF or a voltagesource. The IADJ pin can be connected to VREF through an external resistor to set LED current based on the 2.4-V internal reference voltage. This device offers different methods to set the IADJ voltage. Figure 27 shows howthe IADJ input can be used in conjunction with a NTC resistor to implement thermal foldback protection. A PWMsignal in conjunction with first- or second-order low-pass filter can be used to program the IADJ voltage as shownin Figure 28).

Figure 26. Static ReferenceSetting Resistor Divider From

VCC

Figure 27. Thermal Fold-backCircuit Using External NTC

Resistor

Figure 28. Analog DimmingAchieved By Low-pass Filtering

External PWM Signal

8.3.10 DIM/PWM InputThe TPS92692 and TPS92692-Q1 devices incorporate a PWM generator circuit to facilitate analog voltage toPWM duty cycle translation. The dimming frequency is set by connecting a capacitor from RAMP pin to GND.The dimming frequency, fDIM, can be calculated as follows:

(5)

The internal PWM signal can be varied from 0% to 100% by setting the DIM/PWM pin voltage between 1 V and 3V. Equation 6 describes the relationship between DIM/PWM pin voltage, VDIM and internal PWM duty cycle,DPWM(INT).

(6)

For improved dimming accuracy, use the VREF pin and a resistor divider to set the DIM/PWM pin voltage, VDIM,and the corresponding duty cycle. The device can be configured to step the duty cycle between 100% and theprogrammed value by diode connecting the external control signal, VCTRL, to the DIM/PWM pin, as shown inFigure 29. The external control signal, of amplitude 3-V, is usually generated by the command module and isbased on the light output required by the application.



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5V LDO Regulator

VREF

RAMP

RRAMP

+ PWM

3 V

1 V

VPWM(EXT)

CVREF

DIM/PWM


5V LDO Regulator

1 V

3 V

VREF

RAMP

CRAMP

+ PWM

3 V

1 V

VCTRL DDIM

RDIM2

RDIM1

CVREF

DIM/PWM

20




Feature Description (continued)

Figure 29. PWM Dimming Using Internal PWM Generator

The devices can be configured to be compatible with external PWM signal, VPWM(EXT), where the LED current ismodulated based on the duty cycle, DPWM(EXT). To enable direct PWM, it is required to disable the internaltriangle wave generator by connecting a 249-kΩ resistor from RAMP pin to GND. In this case, the internalcomparator threshold is set to 2.49-V and the internal PWM duty cycle, DPWM(INT), is controlled by the externalPWM command. The RAMP pin cannot be left floating.

Figure 30. Direct PWM Dimming

The internal PWM signal, VPWM controls the GATE and PDRV outputs. Forcing VPWM in a logic low state turns offswitching, parks the oscillator, disconnects the COMP pin, and sets the PDRV output to VCSP in order to maintainthe charge on the compensation network and output capacitors. On the rising edge of the PWM voltage (VPWMset to logic level high), the GATE and PDRV outputs are enabled to ramp the inductor current to the previoussteady-state value. The COMP pin is connected and the error amplifier and oscillator are enabled only when theswitch current sense voltage VIS exceeds the COMP voltage, VCOMP, thus immediately forcing the converter intosteady-state operation with minimum LED current overshoot. When dimming is not required, connect theDIM/PWM pin to the VCC pin. An internal pull-down resistor sets the input to logic-low and disables the devicewhen the pin is disconnected or left floating.



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OV1 OV2O(UV)

OV1

R RV 0.1

R

� u

� �IADJ

(CSP CSN),OCPV

V 1.514�

u

21




Feature Description (continued)8.3.11 Series P-Channel FET Dimming Gate Driver OutputThe PDRV output is a function of the internal PWM signal and is capable of sinking and sourcing up to 50 mA ofpeak current to control a high-side series connected P-channel dimming FET. The PDRV switches between VCSPand (VCSP– 7 V) based on the status of PWM signal to completely turn-off and turn-on the external P-channeldimming FET. The series dimming FET is required to achieve high contrast ratio as it ensures fast rise and falltimes of the LED current in response to the PWM input. Without any dimming FET, the rise and fall times arelimited by the inductor slew rate and the closed-loop bandwidth of the system. Leave the PDRV pin unconnectedif not used.

8.3.12 Soft-StartThe soft-start feature helps the regulator gradually reach the steady-state operating point, thus reducing startupstresses and surges. The devices clamp the COMP pin to the SS pin, separated by a diode, until LED currentnears the regulation threshold. The internal 10-µA soft-start current source gradually increases the voltage on anexternal soft-start capacitor CSS connected to the SS pin. This results in a gradual rise of the COMP voltage fromGND.

The internal 10-µA current source turns on when VCC exceeds the UVLO threshold. At the beginning of the soft-start sequence, the SS pull-down switch is active and is released when the voltage VSS drops below 50 mV. TheSS pin can also be pulled down by an external switch to stop switching. When the SS pin is externally driven toenable switching, the slew-rate on the COMP pin is controlled by the compensation capacitor. In this case, thestartup duration and LED current transient is controlled by tunning the compensation network. It is essential toensure that the softstart duration is longer than the time required to charge the output capacitor when selectingthe soft-start capacitor, CSS and the compensation capacitor, CCOMP.

8.3.13 Current Monitor OutputThe IMON pin voltage represents the LED current measured by the rail-to-rail current sense amplifier across theexternal current shunt resistor. The linear relationship between the IMON voltage and LED current includes theamplifier gain-factor of 14 (see Feature Description section). The IMON output can be connected to an externalmicrocontroller or comparator to facilitate LED open, short, or cable harness fault detection and mitigation. TheIMON voltage is internally clamped to 3.7 V.

8.3.14 Output Overvoltage ProtectionThe TPS92692 and TPS92692-Q1 devices include a dedicated OV pin which can be used for either input oroutput overvoltage protection. This pin features a precision 1.228 V (typ) threshold with 20-µA (typ) of hysteresiscurrent. The overvoltage threshold limit is set by a resistor divider network from the input or output terminal toGND. When the OV pin voltage exceeds the reference threshold, the GATE pin is immediately pulled low, thePDRV output is disabled, and the SS and COMP capacitors are discharged. The GATE and PDRV outputs areenabled and a new startup sequence is initiated after the voltage drops below the hysteresis threshold set by the20-µA source current and the external resistor divider.

8.3.15 Output Short-circuit ProtectionThe device monitors the output of the current sense amplifier and the output voltage via OV pin to determineLED Short-circuit fault. The device signals an output overcurrent fault when the voltage across the current senseamplifier, (V(CSP-CSN)), exceeds the regulation set point based on the IADJ pin voltage, VIADJ. The overcurrent faultthreshold is calculated as follows:

(7)

The device also indicates a short-circuit condition when the voltage across the OV pin and GND falls below 100mV. In this case, the output voltage, VO, is below the undervoltage fault threshold determined based on theresistor divider connected to the OV pin.

(8)



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22




Feature Description (continued)The devices indicate a fault by forcing the open-drain fault indicator FLT pin to GND and initiating a 36-ms timer.The devices do not internally initiate any protection action and continue to operate until externally disabled bypulling SS pin to GND. This provides maximum design flexibility to enable user defined fault protection by usingeither the fault indicator output, FLT, or the analog IMON output based on the LED driver topology and endapplication.

The undervoltage fault detection circuit is internally disable based on the SS pin voltage and internal PWMstatus. The fault blanking circuit is designed to prevent false undervoltage detection during the startup sequenceand PWM dimming operation.

8.3.16 Thermal ProtectionInternal thermal shutdown circuitry is implemented to protect the controller in the event the maximum junctiontemperature is exceeded. When activated, typically at 175°C, the controller is forced into a shutdown mode,disabling the internal regulator. This feature is designed to prevent overheating and damage to the device.

8.3.17 Fault Indicator (FLT)The devices include an open-drain output to indicate fault conditions. The FLT pin goes low under the followingconditions:• Overvoltage across the LED string (VOV> 1.24 V)• Under voltage across the LED string (VOV< 100 mV)• Overcurrent across the LED string (14 × V(CSP-CSN) > 1.5 × VIADJ)• Cycle-by-cycle switch current limit condition (VIS > 250 mV)

The FLT pin goes high when the fault conditions ends or when the internal 36-ms timer expires. The status of theFLT under different fault conditions is summarized in the Device Functional Modes section.

8.4 Device Functional ModesThe following table summarizes the device behavior under fault condition.

Table 1. Fault DescriptionsFAULT DETECTION ACTION

Input undervoltage(UVLO)

VCC(RISE) < 4.5 V The device enters the standby state when the VCC voltage falls below the UVLOthreshold. In standby state, GATE and PDRV outputs are disabled and the SS andCOMP capacitors are discharged. FLT pin remains in high-impedance state.VCC(FALL) < 4.1 V

Switch current limit VIS > 250 mV

Cycle-by-cycle current limit is activated when the IS pin voltage exceeds 250 mV. TheGATE and PDRV outputs are disabled, the SS and COMP pin capacitors are dischargedand FLT pin is forced to ground. An internal 35-μs timer is activated. Soft-start sequenceis initiated after expiration of the 35 μs timer period.

Thermal protection TJ > 175°C

Internal thermal shutdown circuitry is activated when the junction temperature exceeds175 °C. The controller is forced into a shutdown mode, disabling the internal regulators.A startup sequence is initiated when the junction temperature falls below 155˚C. TheFLT pin remains in a high-impedance state.

Programmable outputovervoltage protection VOV > 1.228 V

When the OV pin voltage exceeds 1.228 V, GATE and PDRV outputs are disabled, SSand COMP capacitors are discharged, and the FLT pin is forced to GND. A soft-startsequence is initiated once the output voltage drops below the hysteresis threshold set bythe 20 μA current source.

Fixed LED Overcurrentprotection

V(CSP-CSN) > V((CSP-CSN),OCP)

The FLT pin is forced to ground for 36-ms when the LED current exceeds 1.5 times theregulation set point. The FLT pin is released after timer expires. Under sustained short-circuit condition, the FLT pin transitions between a high-impedance state and grounduntil the fault is cleared. Device continues to operate while in this condition.

Output undervoltageprotection VOV < 100 mV

The FLT pin is forced to ground for 36-ms when OV pin voltage drops below 100 mV.The FLT pin is released after timer expires. Under sustained short-circuit condition, theFLT pin transitions between the high-impedance state and ground until fault is cleared.Device continues to operate while in this condition.

Programmable LEDovercurrent protection VIMON > VIADJ

Current monitor output (IMON) can be used to externally program current limit. TheIMON output can be connected to an external microcontroller or comparator to facilitateLED open, short, or cable harness fault detection.



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T(FAULT_TMR)

ILED

SS/FLT

GATE

PDRV

ISS = 10�A

Overcurrent Detected

T(FAULT_TMR) T(FAULT_TMR)

2.4 VVSS(UVP_EN)

Fault Cleared

T(FAULT_TMR)

VCSP

SS/FLT

GATE

PDRV

ISS = 10�A 2.4 VVSS(UVP_EN)

UndervoltageDetected

T(FAULT_TMR) T(FAULT_TMR)

Fault Cleared

SS

FLT

CSS

23




Device Functional Modes (continued)Table 1. Fault Descriptions (continued)

FAULT DETECTION ACTIONCOMP pin short toground VCOMP < 1.6 V Switching is disabled when COMP voltage falls below 1.6 V. The FLT pin remains a in

high-impedance state.

VREF pin short toground VREF < 2.0 V

The device enters standby when the VCC voltage falls below the UVLO threshold. In thestandby state, GATE and PDRV outputs are disabled and the SS and COMP capacitorsare discharged. The FLT pin will remain in a high-impedance state.

8.4.1 Hiccup Mode Short-circuit ProtectionConnecting the FLT pin to the SS pin enables hiccup mode operation under output short-circuit conditions.

Figure 31. Hiccup Mode Short-Circuit Protection

On detection of output short-circuit fault, the FLT pin forces the SS pin to GND (VSS < 50 mV) and disablesGATE and PDRV outputs for 36-ms. Upon timer expiration, the FLT pin is released and a new soft startsequence is initiated. Under sustained fault conditions the device operates in hiccup mode, attempting to recoverafter every 36-ms period.

Figure 32. Output Overcurrent Fault Protection Figure 33. Output Undervoltage Fault Protection

8.4.2 Fault Indication ModeThe FLT pin output can be setup to indicate fault status to a microcontroller and aid in fault diagnostics andprotection. In case of a fault, the FLT pin is forced low when biased through an external resistor connected eitherto reference voltage output, VREF, or an external bias supply. When connected to VREF, the FLT pin is drivenlow when the device enters standby mode during UVLO, thermal shutdown, or VREF short-circuit conditions. TheFault Indicator (FLT) section lists fault diagnostics and system level faults.



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SS

FLT

TPS92692

CSS

RFLT

BIAS

GPIO1

GPIO2

Microcontroller

SS

FLT

TPS92692

CSS

RFLT

VREF

GPIO1

GPIO2

Microcontroller

24




Figure 34. FLT Pin Interface With Microcontroller Figure 35. FLT Pin Interface With Microcontroller



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VCTRL

TPS92692-Q1

VIN

VREF

FLT

SS

DM

RT

COMP

IMON

IADJ

DIM/PWM

VCC

GATE

IS

GND

SLOPE

OV

CSP

CSN

PDRV

RAMP

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VIN LED +

LED í�

L

CIN

CVREF

CSS

CDM

RT

CCOMP

CIMON

RADJ2

RADJ1RDIM2

RDIM1

RSLP

RIS

CVCC

ROV1

ROV2

COUT

CRAMP

RCS

QM

QDIMD

DDIM

PAD

25




9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe TPS92692 and TPS92692-Q1 controllers are suitable for implementing step-up or step-down LED drivertopologies including boost, buck-boost, SEPIC, and flyback. Use the following design procedure to selectcomponent values for the TPS92692-Q1 device. This section presents a simplified discussion of the designprocess for the boost and buck-boost converter. The expressions derived for the buck-boost topology can bealtered to select components for a 1:1 coupled-inductor SEPIC converter. The design procedure can be easilyadapted for flyback and similar converter topologies.

Figure 36. Boost LED Driver



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TPS92692-Q1

VIN

VREF

FLT

SS

DM

RT

COMP

IMON

IADJ

DIM/PWM

VCC

GATE

IS

GND

SLOPE

OV

CSP

CSN

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20

19

18

17

16

15

14

13

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6

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26




Application Information (continued)

Figure 37. Buck-Boost LED Driver

Figure 38. SEPIC LED Driver



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Application Information (continued)9.1.1 Duty Cycle ConsiderationsThe switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. Insteady state, the duty cycle is derived using expression:

Boost:

(9)

Buck-Boost:

(10)

The minimum duty cycle, DMIN, and maximum duty cycle, DMAX, are calculated by substituting maximum inputvoltage, VIN(MAX), and the minimum input voltage, VIN(MIN), respectively in the previous expressions. The minimumduty cycle achievable by the device is determined by the leading edge blanking period and the switchingfrequency. The maximum duty cycle is limited by the internal oscillator to 90% (typ) to allow for minimum off-time.It is necessary for the operating duty cycle to be within the operating limits of the device to ensure closed-loopLED current regulation over the specified input and output voltage range.

9.1.2 Inductor SelectionThe choice of inductor sets the continuous conduction mode (CCM) and discontinuous conduction mode (DCM)boundary condition. Therefore, one approach of selecting the inductor value is by deriving the relationshipbetween the output power corresponding to CCM-DCM boundary condition, PO(BDRY) and inductance, L. Thisapproach ensures CCM operation in battery-powered LED driver applications that are required to supportdifferent LED string configurations with a wide range of programmable LED current set points. The CCM-DCMboundary condition can be estimated either based on the lowest LED current and the lowest output voltagerequirements for a given application or as a fraction of maximum output power, PO(MAX).

(11)

(12)

Boost:

(13)

Buck-Boost:

(14)

Select inductor with saturation current rating greater than the peak inductor current, IL(PK), at the maximumoperating temperature.

Boost:

(15)

Buck-Boost:

(16)



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Application Information (continued)9.1.3 Output Capacitor SelectionThe output capacitors are required to attenuate the discontinuous or large ripple current generated by switchingand achieve the desired peak-to-peak LED current ripple, ΔiLED(PP). The capacitor value depends on the totalseries resistance of the LED string, rD and the switching frequency, ƒSW.The capacitance required for the targetLED ripple current can be calculated based on following equations.

Boost:

(17)

Buck-Boost:

(18)

When choosing the output capacitors, it is important to consider the ESR and the ESL characteristics as theydirectly impact the LED current ripple. Ceramic capacitors are the best choice due to their low ESR, high ripplecurrent rating, long lifetime, and good temperature performance. When selecting ceramic capacitors, it isimportant to consider the derating factors associated with higher temperature and DC bias operating conditions.TI recommends an X7R dielectric with voltage rating greater than maximum LED stack voltage. An aluminumelectrolytic capacitor can be used in parallel with ceramic capacitors to provide bulk energy storage. Thealuminum capacitors must have necessary RMS current and temperature ratings to ensure prolonged operatinglifetime. The minimum allowable RMS output capacitor current rating, ICOUT(RMS), can be approximated:

Boost and Buck-Boost:

(19)

9.1.4 Input Capacitor SelectionThe input capacitors, CIN, smooth the input voltage ripple and store energy to supply input current during inputvoltage or PWM dimming transients. The series inductor in the Boost and SEPIC topologies provides continuousinput current and requires a smaller input capacitor to achieve desired input ripple voltage, ΔvIN(PP). The Buck-Boost and Flyback topologies have discontinuous input current and require a larger capacitor to achieve thesame input voltage ripple. Based on the switching frequency, ƒSW, and the maximum duty cycle, DMAX, the inputcapacitor value can be calculated as follows:

Boost:

(20)

Buck-Boost:

(21)

X7R dielectric-based ceramic capacitors are the best choice due to their low ESR, high ripple current rating, andgood temperature performance. For applications using PWM dimming, TI recommends an aluminum electrolyticcapacitor in addition to ceramic capacitors to minimize the voltage deviation due to large input current transientsgenerated in conjunction with the rising and falling edges of the LED current.



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Application Information (continued)

Figure 39. VIN Filter

Decouple VIN pin with a 0.1-µF ceramic capacitor, placed as close as possible to the device and a series 10-Ωresistor to create a 150-kHz low-pass filter.

9.1.5 Main Power MOSFET SelectionThe power MOSFET is required to sustain the maximum switch node voltage, VSW, and switch RMS currentderived based on the converter topology. TI recommends a drain voltage VDS rating of at least 10% greater thanthe maximum switch node voltage to ensure safe operation. The MOSFET drain-to-source breakdown voltage,VDS, is calculated using the following expressions.

Boost:

(22)

Buck-Boost:

(23)

The voltage, VO(OV), is the overvoltage protection threshold and the worst-case output voltage under faultconditions. The worst case MOSFET RMS current for Boost and Buck-Boost topology is dependent on maximumoutput power, PO(MAX), and is calculated as follows:

(24)

Select a MOSFET with low total gate charge, Qg, to minimize gate drive and switching losses. The MOSFET RDSresistance is usually a less critical parameter because the switch conduction losses are not a significant part ofthe total converter losses at high operating frequencies. The switching and conduction losses are calculated asfollows:

(25)

(26)

CRSS is the MOSFET reverse transfer capacitance. IL is the average inductor current. IGATE is gate drive outputcurrent, typically 500 mA. The MOSFET power rating and package is selected based on the total calculated loss,the ambient operating temperature, and maximum allowable temperature rise.

9.1.6 Rectifier Diode SelectionA Schottky diode (when used as a rectifier) provides the best efficiency due to its low forward voltage drop andnear-zero reverse recovery time. TI recommends a diode with a reverse breakdown voltage, VD(BR), greater thanor equal to MOSFET drain-to-source voltage, VDS, for reliable performance. It is important to understand theleakage current characteristics of the Schottky diode, especially at high operating temperatures because itimpacts the overall converter operation and efficiency.

Use Equation 27 to calculate the current through the diode, ID.

(27)



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30




Application Information (continued)The diode power rating and package is selected based on the calculated current, the ambient temperature andthe maximum allowable temperature rise.

9.1.7 LED Current ProgrammingThe LED current is set by the external current sense resistor, RCS, and the analog adjust voltage, VIADJ. Thecurrent sense resistor is placed in series with the LED load. The CSP and CSN inputs of the internal rail-to-railcurrent sense amplifier are connected to the RCS resistor to enable closed-loop regulation. When VIADJ > 2.5 V,the internal 2.4-V reference sets the V(CSP-CSN) threshold to 170.7 mV and the LED current is regulated to:

(28)

The LED current can be programmed by varying VIADJ between 140 mV to 2.25 V. The LED current can becalculated using:

(29)

TI recommends a low-pass common-mode filter consisting of 10-Ω resistors in series with CSP and CSN inputsand 0.01-µF capacitors to ground to minimize the impact of voltage ripple and noise on LED current accuracy(see Figure 24 section). A 0.1-µF capacitor across CSP and CSN is included to filter high-frequency differentialnoise.

9.1.8 Switch Current Sense ResistorThe switch current sense resistor, RIS, is used to implement peak current mode control and to set the peakswitch current limit. The value of RIS is selected to protect the main switching MOSFET under fault conditions.The RIS can be calculated based on peak inductor current, iL(PK), and switch current limit threshold, VIS(LIMIT).

(30)

Figure 40. IS Input Filter

The use of a 1-nF and 100-Ω low-pass filter is optional. If used, the recommended resistor value is less than 500Ω in order to limit its influence on the internal slope compensation signal.

9.1.9 Slope CompensationThe magnitude of internal artificial ramp, VSL, is set by slope resistor RSLP. The device compensates for thechanges in input voltage, VIN and output voltage sensed by CSP pin, VCSP to achieve stable inner current loopoperation over wide range of operating conditions. The value of RSLP is determined by the inductor, L and theswitch current sense resistor, RIS and is independent of input and output voltage for Boost, Boost-to-Battery andBuck-Boost topologies.

(31)



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Application Information (continued)9.1.10 Feedback CompensationThe open-loop response is the product of the modulator transfer function (shown in Equation 32) and thefeedback transfer function. Using a first-order approximation, the modulator transfer function can be modeled asa single pole created by the output capacitor, and in the boost and buck-boost topologies, a right half-plane zerocreated by the inductor, where both have a dependence on the LED string dynamic resistance, rD. The ESR ofthe output capacitor is neglected in the analysis. The small-signal modulator model also includes a DC gainfactor that is dependent on the duty cycle, output voltage, and LED current.

(32)

The Table 2 summarizes the expression for the small-signal model parameters.

Table 2. Small-Signal Model ParametersDC GAIN (G0) POLE FREQUENCY (ωP) ZERO FREQUENCY (ωZ)

Boost

Buck-Boost

The feedback transfer function includes the current sense resistor and the loop compensation of thetransconductance amplifier. A compensation network at the output of the error amplifier is used to configure loopgain and phase characteristics. A simple capacitor, CCOMP, from COMP to GND (as shown in Figure 41) providesintegral compensation and creates a pole at the origin. Alternatively, a network of RCOMP, CCOMP, and CHF, shownin Figure 42, can be used to implement proportional and integral (PI) compensation to create a pole at the origin,a low-frequency zero, and a high-frequency pole.

The feedback transfer function is defined as follows.

Feedback transfer function with integral compensation:

(33)

Feedback transfer function with proportional integral compensation:

(34)

The pole at the origin minimizes output steady-state error. High bandwidth is achieved with the PI compensatorby placing the low-frequency zero an order of magnitude less than the crossover frequency. Use the followingexpressions to calculate the compensation network.



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Figure 41. Integral Compensator Figure 42. Proportional Integral Compensator

Boost and Buck-Boost with integral compensator:

(35)

Boost and Buck-Boost with proportional integral compensator:

(36)

(37)

(38)

The loop response is verified by applying step input voltage transients. The goal is to minimize LED currentovershoot and undershoot with a damped response. Additional tuning of the compensation network may benecessary to optimize PWM dimming performance.

9.1.11 Soft-StartThe soft-start time (tSS) is the time required for the LED current to reach the target set point. The required soft-start time is programmed using a capacitor, CSS, from SS pin to GND, and is based on the LED current, outputcapacitor, and output voltage.

(39)

9.1.12 Overvoltage and Undervoltage ProtectionThe overvoltage threshold is programmed using a resistor divider, ROV2 and ROV1, from the output voltage, VO, toGND for Boost and SEPIC topologies, as shown in Figure 36 and Figure 38. If the LEDs are referenced to apotential other than GND, as in the Buck-Boost, the output voltage is sensed and translated to ground by using aPNP transistor and level-shift resistors, as shown in Figure 37. The overvoltage turn-off threshold, VO(OV), is:

Boost:

(40)



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33




Buck and Buck-Boost:

(41)

The overvoltage hysteresis, VOV(HYS) is:

(42)

The corresponding undervoltage fault threshold, VO(UV) is:

(43)

9.1.13 Analog to PWM Dimming ConsiderationsThe analog to PWM duty cycle translation is based on the internal PWM generator, configured by connecting acapacitor across RAMP pin and GND, as shown in Figure 29. The minimum PWM duty cycle is programmed bysetting the voltage on DIM/PWM pin, VDIM using a resistor divider from VREF pin to GND.

(44)

(45)

The device is designed to support a minimum PWM duty cycle of 4% with better than 5% accuracy fromDIM/PWM input to PDRV output in this operating mode. To avoid excess loading of the VREF LDO output, TIrecommends a resistor network with sum of resistors RDIM1 and RDIM2 greater than 10 kΩ. A bypass capacitor of0.1-µF prevents noise coupling and improves performs for low dimming values.

9.1.14 Direct PWM Dimming ConsiderationsThe device can be configured to implement dimming function based on external PWM command by disabling theinternal ramp generator, as explained in DIM/PWM Input section. The internal comparator reference is set to 2.49V by connecting a 249-kΩ resistor, RRAMP, from the RAMP pin to GND. The internal PWM duty cycle is controlledby an external 5-V or 3.3-V signal, generated by a command module or a microcontroller.

9.1.15 Series P-Channel MOSFET SelectionWhen PWM dimming, the device requires another P-channel MOSFET placed in series with the LED load. Selecta P-channel MOSFET with gate-to-source voltage rating of 10-V or higher and with a drain-to-source breakdownvoltage rating greater than the output voltage. Ensure that the drain current rating of the P-channel MOSFETexceeds the programmed LED current by at least 10%.

It is important to consider the FET input capacitance and on-resistance as it impacts the accuracy and efficiencyof the LED driver. TI recommends a FET with lower input capacitance and gate charge to minimize the errorscaused by rise and fall times when PWM dimming at low duty cycles.



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34



9.2 Typical Applications

9.2.1 Typical Boost LED Driver

Figure 43. Boost LED Driver With High-Side Current Sense



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9.2.1.1 Design RequirementsTable 3 shows the design parameters for the boost LED driver application.

Table 3. Design ParametersPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICSInput voltage range 7 14 18 VInput UVLO setting 4.5 V

OUTPUT CHARACTERISTICSLED forward voltage 2.8 3.2 3.6 VNumber of LEDs in series 14

VO Output voltage LED+ to LED– 39.2 44.8 50.4 VILED Output current 350 500 mARR LED current ripple ratio 4%rD LED string resistance 3 Ω

PO(MAX) Maximum output power 25 WfPWM PWM dimming frequency 240 HzDPWM Analog to PWM duty cycle set point (low

brightness mode)8 %

SYSTEMS CHARACTERISTICSPO(BDRY) Output power at CCM-DCM boundary

condition6 W

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9.2.1.2 Detailed Design ProcedureThis procedure is for the boost LED driver application.

9.2.1.2.1 Calculating Duty Cycle

Solve for D, DMAX, and DMIN:

(46)

(47)

(48)

9.2.1.2.2 Setting Switching Frequency

Solve for RT:

(49)

The closest standard resistor of 20 kΩ is selected.



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9.2.1.2.3 Setting Dither Modulation Frequency

Solve for CDM:

(50)

The closest standard capacitor is 27 nF.

9.2.1.2.4 Inductor Selection

The inductor is selected to meet the CCM-DCM boundary power requirement, PO(BDRY). In most applications,PO(BDRY) is set to be 1/3 of the maximum output power, PO(MAX). The inductor value is calculated for typical inputvoltage, VIN(TYP), and output voltage, VO(TYP):

(51)

The closest standard inductor is 22 µH.

For best results, ensure that the inductor saturation current rating is greater than the peak inductor current, IL(PK).

(52)

9.2.1.2.5 Output Capacitor Selection

The specified peak-to-peak LED current ripple, ΔiLED(PP), is:

(53)

The output capacitance required to achieve the target LED current ripple is:

(54)

Four 4.7-µF, 100-V rated X7R ceramic capacitors are used in parallel to achieve a combined output capacitanceof 18.8 µF.

9.2.1.2.6 Input Capacitor Selection

The input capacitor is required to reduce switching noise conducted through the input wires and reduced theinput impedance of the LED driver. The capacitor required to limit peak-to-peak input ripple voltage ripple,ΔvIN(PP), to 20 mV is given by:

(55)

Two 4.7-µF, 50-V X7R ceramic capacitors are used in parallel to achieve a combined input capacitance of 9.4-µF.

9.2.1.2.7 Main N-Channel MOSFET Selection

Ensure that the MOSFET ratings exceed the maximum output voltage and RMS switch current.

(56)

(57)

A N-channel MOSFET with a voltage rating of 100-V and a current rating of 4 A is required for this design.



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9.2.1.2.8 Rectifying Diode Selection

Select a diode should be selected based on the following voltage and current ratings:

(58)

(59)

A 100-V Schottky diode with low reverse leakage current is suitable for this design. The package must be able tohandle the power dissipation resulting from continuous forward current, ID, of 0.5 A.

9.2.1.2.9 Programming LED Current

The LED current can be programmed to match the LED string configuration by using a resistor divider, RADJ1 andRADJ2, from VREF to GND for a given sense resistor, RCS, as shown in Figure 43. To maximize the accuracy, theIADJ pin voltage is set to 2.1 V for the specified maximum LED current of 500-mA. The current sense resistor,RCS, is then calculated as:

(60)

A standard resistor of 0.3 Ω is selected. Table 4 summarizes the IADJ pin voltage and the choice of the RADJ1and RADJ2 resistors for different current settings.

Table 4. Design RequirementsLED CURRENT IADJ VOLTAGE (VIADJ) RADJ1 RADJ2

100 mA 420 mV 6.34 kΩ 68.1 kΩ350 mA 1.47 V 29.4 kΩ 68.1 kΩ500 mA 2.1 V 49.9 kΩ 68.1 kΩ

9.2.1.2.10 Setting Switch Current Limit

Solve for current sense resistor, RIS:

(61)

A standard value of 0.06 Ω is selected.

9.2.1.2.11 Programming Slope Compensation

The artificial slope is programmed by resistor, RSL.

(62)

A standard resistor of 100 kΩ is selected.

9.2.1.2.12 Deriving Compensator Parameters

The modulator transfer function for the Boost converter is derived for nominal VIN voltage and corresponding dutycycle, D, and is given by the following equation. (See Feedback Compensation section for more information.)

(63)

The proportional-integral compensator components CCOMP and RCOMP are obtained by solving the followingexpressions:

(64)



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3 3REF DIMDIM2 DIM1

DIM

V V 4.96 1.16R R 10 10 32.76 10

V 4.96

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38




(65)

The closet standard capacitor of 18-nF and resistor of 4.12-kΩ is selected. The high frequency pole location isset by a 1-nF CHF capacitor.

9.2.1.2.13 Setting Start-up Duration

The soft-start capacitor required to achieve start-up in 8 ms is given by:

(66)

The closet standard capacitor of 100 nF is selected.

9.2.1.2.14 Setting Overvoltage Protection Threshold

The overvoltage protection threshold of 62 V and hysteresis of 3 V is set by the ROV1 and ROV2 resistor divider.

(67)

(68)

The standard resistor values of 150 kΩ and 3.01 kΩ are chosen.

9.2.1.2.15 Analog-to-PWM Dimming Considerations

The PWM dimming frequency is set by the CRAMP capacitor.

(69)

The closet standard capacitor of 10 nF is selected.

The PWM duty cycle of 8% programmed by setting the DIM/PWM voltage using resistor divider, RDIM1 and RDIM2connected from VREF pin to GND.

(70)

The value of resistor, RDIM1 is set as of 10-kΩ. The resistor RDIM2 is calculated using the following equation:

(71)


A P-channel MOSFET with a voltage rating of 100-V and a current rating of 1 A is required to enable series FETdimming for this design.

9.2.1.3 Application CurvesThese curves are for the boost LED driver.



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39




Ch1: Switch node voltage;Ch2: Switch current sense voltage;Ch4: LED current; Time: 1 µs/div

Figure 44. Normal Operation

Ch1: Dither modulation voltage;Ch4: LED current; Time: 400 µs/div

Figure 45. Spread Spectrum Frequency Modulation

Ch1: Input voltage; Ch2: Soft-start (SS) voltage;Ch3: Input current;Ch4: LED current; Time: 4 ms/div

Figure 46. Startup Transient

Ch1: Dim/PWM voltage;Ch2: RAMP pin voltage;Ch4: LED current; Time: 2 ms/div

Figure 47. Analog-to-PWM Dimming Transient

Ch1: External PWM input signal;Ch2: PDRV voltage;Ch4: LED current; Time: 2 ms/div

Figure 48. Direct PWM Dimming Transient

Ch1: External PWM input voltage;Ch3: Switch sense current resistor voltage;Ch4: LED current; Time: 4 µs/div

Figure 49. PWM Dimming Transient (Zoomed)



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40




Ch1: FLT output;Ch2: CSP pin voltage;Ch4: LED current; Time: 100 ms/div

Figure 50. LED Open-Circuit Fault


Figure 51. LED Short-Circuit Fault

Figure 52. Conducted EMI Scan (SSFM Disabled)Figure 53. Conducted EMI Scan (SSFM Enabled)



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4.12kR11

33uH

L2

100V

1

3

2

D1

0.1

R1

4

Q1

10µFC4 GND

GND

0.01 µFC1

0.01 µFC11

10µFC2

10µFC3

1

2

J1

4.7µF1210

C12

GND

3

1

2

Q2

150kR3

2

1

3

J2

GND

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1

3

2

40V

D3VBAT1

10µFC16

10µFC17

GND

0.06R10

100

R8

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0.01 µFC28

10.0R12

10.0R13

GND

100V

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VCC

0.1µF

C3620.0k

R15

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C23

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C32

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R16

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C24

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R14

VREF2

FLT3

VIN1

SS4

DM5

RT6

COMP7

IMON8

IADJ9

DIM/PWM10 RAMP 11

PDRV 12

CSN 13

CSP 14

OVP 15

SLOPE 16

GND 17

IS 18

GATE 19

VCC 20

DAP21

U1

TPS92692Q0.1µFC34

1000pF

C22

1000pFC21

249kR23

PWM Input

10µFC9

10µFC10

GND


41



9.2.2 Typical Buck-Boost LED Driver

Figure 54. Buck-Boost LED Driver



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� � � �

10 103

T 1.047 1.0473SW

1.432 10 1.432 10R 20.05 10

f 390 10

u u u

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42




9.2.2.1 Design RequirementsBuck-Boost LED drivers provide the flexibility needed in applications that support multiple LED loadconfigurations. For such applications, it is necessary to modify the design procedure presented in to account forthe wider range of output voltage and LED current specifications. This design is based on the maximum outputpower PO(MAX), set by the lumen output specified for the lighting application. The design procedure for a batteryconnected application with 3 to 9 LEDs in series and maximum 15 W output power is outlined in this section.

Table 5. Design ParametersPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICSInput voltage range 7 14 18 VInput UVLO setting 4.5 V

OUTPUT CHARACTERISTICSLED forward voltage 2.8 3.2 3.6 VNumber of LEDs in series 3 7 11

VO Output voltage LED+ to LED– 8.4 22.4 39.6 VILED Output current 100 500 1500 mAΔiLED(PP) LED current ripple 5%rD LED string resistance 0.9 2.1 3.3 Ω

PO(MAX) Maximum output power 12.6 WDPWM Direct PWM dimming range fPWM = 240 Hz 4% 100%SYSTEMS CHARACTERISTICSPO(BDRY) Output power at CCM-DCM boundary

condition3 W

ΔvIN(PP) Input voltage ripple 70 mVVO(OV) Output overvoltage protection threshold 45 VVOV(HYS) Output overvoltage protection hysteresis 3 VtSS Soft-start period 8 msfSW Switching frequency 390 kHz

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Calculating Duty Cycle

Solving for D, DMAX, and DMIN:

(72)

(73)

(74)

9.2.2.2.2 Setting Switching Frequency

Solving for RT resistor:

(75)

9.2.2.2.3 Setting Dither Modulation Frequency

Solve for CDM:



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43




(76)

The closest standard capacitor is 27 nF.

9.2.2.2.4 Inductor Selection

The inductor is selected to meet the CCM-DCM boundary power requirement, PO(BDRY). Typically, the boundarycondition is set to enable CCM operation at the lowest possible operating power based on minimum LED forwardvoltage drop and LED current. In most applications, PO(BDRY) is set to be 1/3 of the maximum output power,PO(MAX). The inductor value is calculated for maximum input voltage, VIN(MAX), and output voltage, VO(MAX):

(77)

The closest standard value of 33 µH is selected. The inductor ripple current is given by:

(78)

Ensure that the inductor saturation rating exceeds the calculated peak current which is based on the maximumoutput power using Equation 79.

(79)

9.2.2.2.5 Output Capacitor Selection

Select the output capacitance to achieve the 5% peak-to-peak LED current ripple specification. Based on themaximum power, the capacitor is calculated in Equation 80.

(80)

This design requires a minimum of three, 10-µF, 50-V and one 4.7-µF, 100-V, X7R ceramic capacitors in parallelto meet the LED current ripple specification over the entire range of output power. Additional capacitance may berequired based on the derating factor under DC bias operation.

9.2.2.2.6 Input Capacitor Selection

The input capacitor is calculated based on the peak-to-peak input ripple specifications, ΔvIN(PP). The capacitorrequired to limit the ripple to 70 mV over range of operation is calculated using:

(81)

A parallel combination of four 10-µF, 50-V X7R ceramic capacitors are used for a combined capacitance of 40µF. Additional capacitance may be required based on the derating factor under DC bias operation.

9.2.2.2.7 Main N-Channel MOSFET Selection

Calculating the minimum transistor voltage and current rating:

(82)



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66 6 3

SLIS

L 33 10R 274.4 10 274.4 10 150.7 10

R 0.06

�u

u u u u u

IS(LIMIT)IS

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44




(83)

This application requires a 100-V N-channel MOSFET with a current rating exceeding 3 A.

9.2.2.2.8 Rectifier Diode Selection

Calculating the minimum Schottky diode voltage and current rating:

(84)

(85)

This application requires a 100-V Schottky diode with a current rating exceeding 1.5 A. TI recommends a singlehigh-current diode instead of paralleling multiple lower-current-rated diodes to ensure reliable operation overtemperature.

9.2.2.2.9 Programming LED Current

The LED current can be programmed to match the LED string configuration by using a resistor divider, RADJ1 andRADJ2, from VREF to GND for a given sense resistor, RCS, as shown in Figure 54. To maximize the accuracy, theIADJ pin voltage is set to 2.1 V for the specified LED current of 1.5 A. The current sense resistor, RCS, is thencalculated as:

(86)

A standard resistor of 0.1 Ω is selected. Table 5 summarizes the IADJ pin voltage and the choice of the RADJ1and RADJ2 resistors for different current settings.

Table 6. Design RequirementsLED CURRENT IADJ VOLTAGE (VIADJ) RADJ1 RADJ2

100 mA 140 mV 2.0 kΩ 68.1 kΩ500 mA 700 mV 11.2 kΩ 68.1 kΩ1.5 A 2.1 V 50 kΩ 68.1 kΩ

9.2.2.2.10 Setting Switch Current Limit and Slope Compensation

Solving for RIS:

(87)

A standard resistor of 0.06 Ω is selected.

9.2.2.2.11 Programming Slope Compensation

The artificial slope is programmed by resistor, RSL.

(88)


9.2.2.2.12 Deriving Compensator Parameters

A simple integral compensator provides a good starting point to achieve stable operation across the wideoperating range. The modulator transfer function with the lowest frequency pole location is calculated based onmaximum output voltage, VO(MAX), duty cycle, DMAX, LED dynamic resistance, rD(MAX), and minimum LED stringcurrent, ILED(MIN). (See Table 2 for more information.)



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33OV2

OV1O(OV)

1.228 R 1.228 150 10R 4.16 10

V 0.7 45 0.7

u u u u

� �

OV(HYS) 3OV2 6 6

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45




(89)

The compensation capacitor needed to achieve stable response is:

(90)

A 100 nF capacitor is selected.

A proportional integral compensator can be used to achieve higher bandwidth and improved transientperformance. However, it is necessary to experimentally tune the compensator parameters over the entireoperating range to ensure stable operation.

9.2.2.2.13 Setting Startup Duration

Solving for soft-start capacitor, CSS, based on 8-ms startup duration:

(91)

A 100-nF soft-start capacitor is selected.

9.2.2.2.14 Setting Overvoltage Protection Threshold

Solving for resistors, ROV1 and ROV2:

(92)

(93)

The closest standard values of 150 kΩ and 4.12 kΩ along with a 60-V PNP transistor are used to set the OVPthreshold to 45 V with 3 V of hysteresis.

9.2.2.2.15 Direct PWM Dimming Consideration

A 60-V, 2-A P-channel FET is used to achieve series FET PWM dimming.

9.2.2.3 Application CurvesThese curves are for the buck-boost LED driver.



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VIADJ (V)

LED

Cur

rent

(m

A)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.20

200

400

600

800

1000

1200

1400

1600

D021

3 LEDs

LED Current (mA)

Effi

cien

cy (

%)

100 200 300 400 500 700 1000 200040

50

60

70

80

90

100

D022

3 LEDs5 LEDs7 LEDs9 LEDs

46




VIN = 14 V

Figure 55. LED Current vs IADJ Voltage

VIN = 14 V

Figure 56. Efficiency


Figure 57. LED Open-Circuit Fault


Figure 58. LED Short-Circuit Fault

10 Power Supply RecommendationsThis device is designed to operate from an input voltage supply range between 4.5 V and 65 V. The input couldbe a car battery or another preregulated power supply. If the input supply is located more than a few inches fromthe TPS92692 or TPS92692-Q1 device, additional bulk capacitance or an input filter may be required in additionto the ceramic bypass capacitors to address noise and EMI concerns.



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47




11 Layout

11.1 Layout Guidelines• The performance of the switching regulator depends as much on the layout of the PCB as the component

selection. Following a few simple guidelines will maximize noise rejection and minimize the generation of EMIwithin the circuit.

• Discontinuous currents are the most likely to generate EMI. Therefore, take care when routing these paths.The main path for discontinuous current in the devices using a buck regulator topology contains the inputcapacitor, CIN, the recirculating diode, D, the N-channel MOSFET, Q1, and the sense resistor, RIS. In theTPS92692 and TPS92692-Q1 devices using a boost regulator topology, the discontinuous current flowsthrough the output capacitor COUT, diode, D, N-channel MOSFET, Q1, and the current sense resistor, RIS. Indevices using a buck-boost regulator topolog. Be careful when laying out both discontinuous loops. Ensurethat these loops are as small as possible. In order to minimize parasitic inductance, ensure that theconnection between all the components are short and thick. In particular, make the switch node (where L, D,and Q1 connect) just large enough to connect the components. To minimize excessive heating, large copperpours can be placed adjacent to the short current path of the switch node.

• Route the CSP and CSN together with Kelvin connections to the current sense resistor with traces as shortas possible. If needed, use common mode and differential mode noise filters to attenuate switching and diodereverse recovery noise from affecting the internal current sense amplifier.

• Because the COMP, IS, OV, DIM/PWM, and IADJ pins are all high-impedance inputs that couple externalnoise easily, ensure that the loops containing these nodes are minimized whenever possible.

• In some applications, the LED or LED array can be far away from the TPS92692 and TPS92692-Q1 devices,or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array islarge or separated from the rest of the regulator, place the output capacitor close to the LEDs to reduce theeffects of parasitic inductance on the AC impedance of the capacitor.

• The TPS92692 and TPS92692-Q1 devices have an exposed thermal pad to aid power dissipation. Addingseveral vias under the exposed pad helps conduct heat away from the device. The junction-to-ambientthermal resistance varies with application. The most significant variables are the area of copper in the PCBand the number of vias under the exposed pad. The integrity of the solder connection from the deviceexposed pad to the PCB is critical. Excessive voids greatly decrease the thermal dissipation capacity.



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VIN

FLT

SS

VREF

RT

COMP

DM

IMON

INP

UT

CO

NN

VCC

IS

GND

GATE

OVP

CSP

SLOPE

CSN

VINLED+

LED+GND

BU

CK

-BO

OS

T

BO

OS

T

VIA TO BOTTOM GROUND PLANE

IADJ

DIM

PDRV

RAMP

TPS92692Q

48




11.2 Layout Example

Figure 59. Layout Recommendation



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49




12 Device and Documentation Support

12.1 Related LinksThe table below lists quick access links. Categories include technical documents, support and communityresources, tools and software, and quick access to sample or buy.

Table 7. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICALDOCUMENTS

TOOLS &SOFTWARE

SUPPORT &COMMUNITY

TPS92692 Click here Click here Click here Click here Click hereTPS92692-Q1 Click here Click here Click here Click here Click here

12.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.3 TrademarksPowerPAD, E2E are trademarks of Texas Instruments.

12.4 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.



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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS92692PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 92692

TPS92692PWPT ACTIVE HTSSOP PWP 20 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 92692

TPS92692QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 92692Q

TPS92692QPWPTQ1 ACTIVE HTSSOP PWP 20 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 92692Q

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

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PACKAGE OPTION ADDENDUM

www.ti.com 29-Mar-2017

Addendum-Page 2

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS92692, TPS92692-Q1 :

• Catalog: TPS92692

• Automotive: TPS92692-Q1

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

http://focus.ti.com/docs/prod/folders/print/tps92692.html

http://focus.ti.com/docs/prod/folders/print/tps92692-q1.html

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS92692PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

TPS92692PWPT HTSSOP PWP 20 250 180.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

TPS92692QPWPRQ1 HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

TPS92692QPWPTQ1 HTSSOP PWP 20 250 180.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jul-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS92692PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0

TPS92692PWPT HTSSOP PWP 20 250 213.0 191.0 55.0

TPS92692QPWPRQ1 HTSSOP PWP 20 2000 367.0 367.0 38.0

TPS92692QPWPTQ1 HTSSOP PWP 20 250 213.0 191.0 55.0

PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jul-2017

Pack Materials-Page 2

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http://www.ti.com/lit/SLMA002

http://www.ti.com/lit/SLMA004

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