Tools - Implementation Options - Chapter15 slide 1 FPGA Tools Course Implementation Options.

Tools - Implementation Options - Chapter15 slide 1

FPGA Tools Course

Implementation Options


Objectives

• Enable the designer to quickly and easily improve implementation results.


Outline

• The Options Window• Implementation Options• Summary


Customizing Xilinx Software

• So far, only the “Push Button” implementation has been discussed.

• Using Timing Constraints is the most effective way of improving design performance.

• The “Push Button” flow is designed to not optimize for speed, area, or CPU time.– This gives the tools the most flexibility to meet your timing

specifications.

• Consider using some of the Implementation Options to help meet performance goals.– Alliance users: use the Options menu accessible by using the

command: Design -> Implement -> Options – Foundation users: use the Options menu accessible by using the

command: Implementation -> Options


Options Window

• The Options menu is used for all Xilinx FPGAs

• UCF file location goes here• Implementation, Simulation,

and Configuration menus vary by FPGA family

• Program Option Templates can be edited and re-used

• The Implementation Template allows you to control the optimization, map, placement, and routing of your design.

Design -> Implement -> Options


Options Window

• The Simulation Template allows you to back-annotate the design by distributing physical design data back to the logic design for post place and route simulation.

• The Configuration Template allows control of the configuration parameters, such as startup sequence and readback capabilities.


Options Window

• The Produce Timing Simulation Data switch enables back-end simulation.

• The Produce Configuration Data switch enables the generation of a bit stream for configuring the FPGA.

• These options can be turned off to save compile time.


Outline

• The Options Window

• Implementation Options• Summary


Logic Optimization Options

• Trim Unconnected Signals (default is On) – Turn off to estimate the resources

required for partially finished design

• Replicate Logic (default is on)– Reduces the fan out of a single

driver to reduce delay– Increases the CLB count

• Generate 5-I/P Functions (default is off)– Reduces the logic level delay, but

may increase the CLB count

Design -> Implement -> Options -> Edit Template



• CLB Packing Strategy (default is fit device)– This option partitions logic more

densely by disabling signal sharing between logic elements in a CLB

– Fit Device - packs logic elements that do not share common signals into the same CLBs.

– Off - causes only logic with common inputs to be packed in the same CLB. This option can increase the speed of a design, while increasing the CLB count.



• Pack CLB Registers for...(default is Structure)– Structure - the mapper will look at the

register bit names for similarities and try to map register bits in an ordered manner

– Minimum Area - produces a denser design

• Pack I/O Registers/Latches into IOBs for... (default is Off)– This option controls the packing of flip-

flops or latches into an IOB.– Normally, the mapper packs registers

and latches within an IOB only if such packing is specified by the design entry method.


Place and Route Options • Place and Route Effort Level

(default is 2)– Higher effort provides better place and

route results at the expense of longer run time

– 80% of performance is obtained through placement

– If design does not meet performance needs, consider using MPPR

• Use Timing Constraints… (default is Auto)– Deselecting this option ignores all

timing constraints– This reduces implementation time at

the expense of design performance


Place and Route Options • Run_Routing Passes (default is

Auto)– This option sets the maximum number of

routing passes that the router runs in a design

– Auto runs the router until specific exit conditions are met

*At a PAR Effort Level of 3, 4, or 5, the router runs until it routes to 100% completion, or until it decides it cannot complete routing*At levels 1 or 2, the router stops after a predetermined number of passes

– With all settings, the router exits immediately after it routes all connections and meets all constraints


Place and Route Options

• Run_Delay-Based Cleanup Passes (default is 0)– Use this option to further optimize

routing of an already routed design

– The router computes delay times between sources and loads on the routed nets, and reroutes to minimize the net delays

• Use the Re-entrant Router to finish routing designs or to meet timing constraints


Timing Report Options

• Logic Level Timing Report is created after MAP but before PAR to save run time– Uses block delays and estimated

net delays to determine if timing constraints are realistic

• Post Layout Timing Report is created after PAR– This timing report provides a brief

analysis of the designs’ performance

• To obtain a detailed analysis, use the Timing Analyzer tool.


Timing Report Options

• Limit Report to_Paths per Timing Constraint– Use this option to set the maximum

number of reported paths for each timing constraint

• Advanced Design Analysis…– This provides a custom report useful

when there are no timing constraints associated with the design


Timing Report Options• Report Paths in Timing Constraints

– This generates a report of the paths and path delays covered by all timing constraints

– The number of paths listed is limited by the number specified with the Limit Report to_Paths per Timing Constraint option

• Report Paths Failing Timing Constraints– This option generates an error report– The error report lists timing errors and

associated net and path delay information– Paths failing are broken down into

individual net and component delays


Outline

• The Options Window• Implementation Options

• Summary


Summary

• If design performance is insufficient and timing constraints have not been met, consider modifying some of the Implementation Options

• CLB and IOB resource usage can be modified by choosing a different packing strategy.

• Placement is responsible for 80% of design performance.

• Choosing a higher Place and Route Effort Level will force the tools to spend more time finding a better placement.

• Delay Based Clean-up is a very effective way of decreasing the delays of unconstrained nets.


Questions

• What is the difference between the Post Layout Timing Report and the Logic Level Timing Report?

• List three ways to increase speed of critical paths or overall design speed.

• Why should the number of routing passes be limited?

Tools - Implementation Options - Chapter15 slide 1 FPGA Tools Course Implementation Options.

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