Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager.

Tools - Design Manager - Chapter 6 slide 1 Version 1.5

FPGA Tools Training Class

Design Manager


In this Chapter, You Will Learn

• How to invoke the Design Manager and set up for implementation

• How to implement your design in an FPGA • We’ll start with a low speed, or “push-button” flow

– Options for high-speed/large designs will be shown tomorrow


Outline

• Design Flow• Design Manager Implementation

– Design Manager Windows

– Design flow to implement the design

– Checking results

– Configuring or programming the FPGA

• Foundation Implementation• Summary


Introducing Xilinx Software

• Xilinx’ Design Manager IMPLEMENTS your design– Places and Routes your netlist to create a data file to program your FPGA or CPLD– Open Framework to major EDA Tools – Generate your netlist with common synthesis or schematic tools– Simulate with common tools such as MTI or Cadence Verilog

• Xilinx’ Foundation CREATES your design– Contains Synthesis, Schematic, and Simulation tools– Also contains Design Manager

• Use Design Manager with Foundation and/or EDA tools


Alliance Software Package

• Alliance Software Package contains Design Manager– Use with standard EDA tools including Synopsys, Synplicity, Exemplar,

MTI, Cadence, and Mentor Tools

– Available on UNIX or PC

Schematic, Cores HDL Code

Design Implementation

Static Timing Analysis,In-Circuit TestingDesign Manager

Design Manager

Functional Simulation

Design Iteration

Third Party Simulation

Functional and TimingVHDL, Verilog or Gate

Level

Third Party Design Entry

Synthesis or Schematic


Xilinx EDA Alliance

• A team effort between Xilinx and EDA vendors to simplify and shorten the ASIC design cycle.

• Major Design Entry and Simulation vendors:– Cadence, Mentor Graphics, Viewlogic, Model Technologies,

OrCad– Synopsys, Synplicity, Synario, Exemplar, ABEL, Aldec

• Support of industry standard file formats– VHDL, Verilog, and EDIF netlist formats– SDF Standard Delay file– VITAL library support

• Current lists of Alliance Members, supported products, and contacts are available on the Xilinx WEB site– From www.xilinx.com -> Products -> Software: Alliance

Series


• Foundation Software Package contains Design Manager and Foundation Synthesis, Schematic Entry, and Simulation tools– Available on PC for NT and Windows

Foundation Software Package


Design IterationSchematic, Cores

HDL Code Simulation

Static Timing Analysis,In-Circuit Testing

Design Entry

Design Verification


Design Manager

Foundation


Design Tools

• Standard CAE entry and verification tools• Xilinx software implements the design

– The design is optimized for best performance and minimal size

– Graphical User Interface and Command Line Interface

– Easy access to other Xilinx programs

– Manages and tracks design revisions


Back Anno.Schematic, Cores

HDL Code


Simulation

Static Timing Analysis,In-Circuit Testing

Design Entry

Design Verification

Design Manager

Design Manager

Foundation or Alliance


Design Flow for Implementation

1. Invoke Design Manager

2. Start a Project or Open a Project

3. Set up for Implementation

4. Implement the Design

5. Check Timing Results

6. Download the FPGA/CPLD

Invoke Foundation Project Manager


Design Manager Engine

Timing Analyzer Static Timing Analysis

NGDBUILD Merge Hierarchical Design

MAPLogical to Physical translation

Groups LUTs and FFs Into CLBs

BITGEN Generates configuration file

Timing Analyzer Static Timing Estimates

PARLayout of Physical DesignRoutes Physical Design

UCFUser Constraint File

Configuration Program the FPGA or CPLD

XNF or EDIF netlist


Design Flow Programs• What’s under the hood?• Translate (NGDBUILD)

– Merges hierarchical EDIF or XNF files into one file

– Contains logical components: combinatorial gates, RAMS, Flip-Flops, etc.

• MAP – Maps logical components to physical components found in Xilinx FPGA

* Look-Up tables, Flip-Flops, Three-State Buffers, etc.– Packs physical components into COMPS (IOBs, CLBs, etc)

• Timing Analyzer– Use before PAR to analyze timing constraints and estimate design performance– Use after PAR to analyze design performance

• PAR– Places COMPS on FPGA and routes the FPGA

• BITGEN– Creates file to configure FPGA


Outline

• Design Flow

• Design Manager Implementation– Design Manager Windows



– Configuring, or programming the FPGA



Foundation or Alliance

• Procedure for both Alliance and Foundation users are given

• Most steps are similar, except– A few steps are optional for Foundation, and

– Tools are invoked differently

• Alliance on PC and on UNIX– Graphical User Interface (GUI) procedures are same for both

– Command line usage can be found with Utilities -> Command History within the Design Manager

– Scripts can be used on PC or UNIX


Step 1: Invoke Design Manager(1)

Flow EngineStart and Stop the Flow Engine

Timing AnalyzerReport on net and path delays

FloorplannerEdit design layout

PROM File FormatterConfigure download data for PROMs

Hardware DebuggerDownload configuration file

EPIC Design EditorDevice-level view of routing

• Invoke the Design Manager – Alliance users: select icon, or use command line invocation: dsgnmgr

– Foundation users: (optional) select Start -> Programs -> Foundation

Series -> Accessories -> Design Manager

• The Design Manager window appears:

Status Window


Step 1: Invoke Design Manager (cont.)

ProjectDirectory containing netlists, also definition of family

VersionBased on a netlist of the designNew version is required when input design is changed

RevisionAn implementation of a Xilinx netlistMultiple revisions typically result from different options or part types

Project

Versions

Revisions Toolbox

Menu bar

Tool bar


Step 2: Start a New Project

A. Select File -> New Project

B. Specify top levelinput netlist

C. Specify workingdirectory

D. Use pull-down menu to specify netlist format

• Alliance users: select the top level netlist in the design– Shown here

• Foundation users: skip this step


Step 2: Start a Project (cont.)

• Set up the design for implementation• Select Part Type

B. Select Part

C. Select Options (...see next foil)

A. Select Design -> Implement


Step 3: Set up for Implementation (1)• Use the Constraints Editor to set timing and

physical specifications– Define Timing Specification – Lock IO pins

• Usage:– Alliance users : Select Design Manager -> Tools ->

Constraints Editor– Foundation Users: select Start -> Xilinx Foundation

Series -> Accessories -> Design Manager -> Tools -> Constraints Editor


Step 3: Set up for Implementation (2)• Enable back annotation file for simulation

– Select Design -> Implement -> Options

• Enable Configuration Data– To generate data to program FPGA/CPLD

• Enable Timing Analyzer Reports• Usage:

– Alliance - Select Implement -> Options from Design Manager– Foundation - Select Implementation-> Options from

Foundation Project Manager

Options Form


Step 4: Implement the Design• Implementation Places and Routes your design, and creates a file

to program the FPGA or CPLD• Usage

– Alliance Users - select Design -> Implement -> Run from the Design Manager

– Foundation Users - select Implementation -> Run from the Foundation Project Manager


Step 4: Implement the Design (cont.) Once implementation is started, the “Run-only” Flow Engine appears

– Tracks status of your design, and allows you to stop or pause


Step 5A. Check Results

• Reports are generated throughout the Design Flow• Reports will be discussed in the next chapter and in

lab

From Design Manager, select Report Browser


Step 5B. Analyze Static Timing

• Displays delays for any path or timing constraint in your design• Provides detailed breakdown of each delay path, including

– net delay– component delay– primitive delay

• Usage:– Alliance users: select Design Manager -> Timing Analyzer– Foundation users: select Start -> Foundation Series -> Accessories -> Design Manager -> Timing Analyzer


Step 6: Configure the FPGA/CPLD

• To configure, or program FPGAs, a bit file is created and downloaded – Configuration can be driven by a

microprocessor

– Data can be stored in a PROM

– Enable Produce Configuration Data (Flow Engine -> Setup -> Options) before implementation

• To configure CPLDs, a JTAG file is downloaded– CPLDs can be configured In-System, or

– CPLDs can be configured using third party programmers

Alliance : Design ->Implement -> OptionsFoundation : Implementation -> Options


Step 6: Configuration MethodsConfiguration Mode Data Input Characteristics

Master Parallel Byte-Wide FPGA loads itself from externalbyte-wide PROM

Master Serial Bit-Serial FPGA loads itself from externalserial PROM

Peripheral Byte-Wide FPGA loaded undermicroprocessor control

Synchronous Peripheral Byte-Wide FPGA loaded by users’configuration clock

Slave Bit-Serial FPGA loaded by microprocessoror DMA controller; used byXChecker Download Cable


Outline

• Design Flow• Design Manager Implementation







Simple Foundation Implementation

• Foundation is both simple to use and powerful– To implement your design, simply select simply select

Implementation -> Run from the Foundation Project Manager Window

• For simple implementation, all tools are located in Foundation Project Manager– Invoke with Start -> Programs -> Xilinx Foundation Series ->

Xilinx Foundation Project Manager

• For customized implementation, tools are located at Start -> Programs -> Xilinx Foundation Series -> Accessories -> Design Manager


Foundation Methodology ChartProcedure Tool LocationBasic Implementation withdefault options

Foundation Project Manager (FPM) ->Implementation

Customization forImplementation, TimingReports, or Configuration

FPM -> Implementation -> Options

Specification of TimingConstraints

Start -> Programs -> Xilinx Foundation Series ->Accessories -> Constraints Editor

Viewing Design Layout Start -> Programs -> Xilinx Foundation Series ->Accessories -> Floorplanner

Edit of physical design Start -> Programs -> Xilinx Foundation Series ->Accessories -> Design Manager -> Tools -> EPIC

In-Depth analysis of designperformance

Start -> Programs -> Xilinx Foundation Series ->Accessories -> Design Manager -> Tools ->Timing Analyzer

• More information is available in the On-Line documents. • Also,Xilinx offers one-day Foundation class and Foundation Express classes


Outline

• Design Flow• Steps to Implement the design with Design Manager





• Design Manager Implementation

• Summary


Summary

• Design Manager is a fast, simple tool to implement an FPGA design

• The techniques just covered were for a simple design• Powerful options for larger and faster designs are

discussed in the high density design materials• Summary for Foundation follows

Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager.

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Transcript of Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager.