Tool for Customizing Fault Tolerance in a System
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Transcript of Tool for Customizing Fault Tolerance in a System
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Karan Maini and Sriharsha Yerramalla ECE 753 Project #10
May 1, 2014
Tool for Customizing Fault Tolerance in a System
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Agenda• Introduction• Background and Related Work• Problem Statement Formulation• Implementation• Hardware Redundancy Techniques and FT Library• Synthesis Results – Area and Timing• Conclusion and Future Scope
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• CAD Tools– Implementing electronic systems easier– Cut down on development time– Made verification process automated
• CAD Tools for Fault Tolerance– Did not leverage advancements– Fault Tolerance was introduced manually– Being picked up in the recent past
Introduction
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• Need for Fault Tolerance– Real-time Systems– Operation Critical Systems– No guarantee of flawless execution
• Applications– Banking– ATM Machines– Spacecraft– Satellites
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Introduction
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• There has been several attempts made to develop an efficient tool without much manual intervention to introduce FT.
• This could be at various levels of granularity. • Our attempt is to make FT at module level
granularity.
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Introduction
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The Challenge
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The Plan
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The Plan
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Solution
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Agenda• Introduction• Background and Related Work• Problem Statement Formulation• Implementation• Hardware Redundancy Techniques and FT Library• Synthesis Results – Area and Timing• Conclusion and Future Scope
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• Hardware Redundancy– Insertion of F-T components into circuit– Done Manually (Old days)– Automatic Insertion Tools (At Present)
• Process– Identify element(s) to be modified– Replication of selected element(s)– Selecting one set of output from different outputs coming from
replicated element(s)
Background and Related Work
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• Hardware Redundancy (Contd.)– Initial Conditions – Input synthesizable design files
– Pre-processing tasks – Identify type, number of elements present
and their characteristics
– Similar to simplified elaboration for synthesis
– Specify the Hardware Redundancy technique to be followed
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Background and Related Work
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• Information Redundancy– Selection of elements (Memory – IM, DM, Register Files)
– Nearly entire module modification to deal with
– Modification of data types and operators in order to process
encoded information
– Insertion of encoders, decoders and checkers in original design
– Adding appropriate operators in F-T library
– Declaration of target objects with the extra bits
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Background and Related Work
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• Information Redundancy (Contd.)– Insert an encoder at a selected point
– Extend the size of selected data to accommodate extra bits
required by the redundant code used
– Perform the functionality on the coded data
– Insert a decoder/checker at a selected output point to get back
the original data
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Background and Related Work
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Agenda• Introduction• Background and Related Work• Problem Statement Formulation• Implementation• Hardware Redundancy Techniques and FT Library• Synthesis Results – Area and Timing• Conclusion and Future Scope
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Make a design Fault Tolerant by introducing
components into the design using various Hardware
Redundancy Techniques. Provide a Fault Tolerant
Library to choose components from. Synthesize the
original and new design to compare overhead
introduced in terms of area and time.
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Problem Statement Formulation
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• Introduce Fault tolerance at Modular level
• Target for Coarse granularity
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Aim
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Assumptions
• User will input all the Synthesizable design files
• At any given instant of time, only a single
instance of a module may be fault prone.
• User will only input files written in Verilog HDL
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Agenda• Introduction• Background and Related Work• Problem Statement Formulation• Implementation• Hardware Redundancy Techniques and FT Library• Synthesis Results – Area and Timing• Conclusion and Future Scope
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Taming the Bull
• In which stage of design should this be tackled? RTL or netlist
• In netlist – Finer control over granularity, but higher design complexity
• In RTL – Difficult to have smaller granularity, but relatively simple design
• This is where our tool helps
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Approach• Accept design files and top level module from
user.• Identify different modules and their hierarchies
present in the design.• Accept options from user.• Update the design with fault tolerance.• Verify the design.
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Design
Scheme of Fault Tolerant Insertion Tool
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Front End - GUI
Technology: Java Swing Look and Feel: Windows 8
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Section 1• Welcome Screen• Upload Design files• View/Update selected files• Enter top-level module
• Fork() a child process to call back-end search engine
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Section 2• Hierarchical View• Returns from back-end• JTree Component used • Different levels – modules
and instantiations
• Singleton selection on leaf node - select an instance
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Section 3• Select Redundancy Type• Scan characteristics of
Instantiated Module Parameters passed Bus-width of parameters
• Introduction of Library Component into design
• Success Message Dialog Box to inform user
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Logical Components of Tool
GUI
FT Insertion
Library
Search Engine
Front End Back End
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Search Engine block• FT insertion block passes the Verilog design
files to search engine block.• Searches for all modules in the design and
populates them in an array.• Starts a recursive process to identify all the
instances and their hierarchies. • Returns the hierarchical information to FT
insertion.
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Library• Following hardware redundancies are supported.1. TMR2. 5MR3. Hybrid4. Sift-out5. Pair and Spare
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TMR • Instance is replicated thrice and a Voter is
added. Parameterized voter to support any bus width
ALU1
ALU2
ALU3
Voter
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• Similar to TMR Voter….
5MR
ALU2
ALU3
ALU4
Voter
ALU5
ALU1
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Hybrid Redundancy• Implemented the design proposed by Daniel P.
Siewiorek et al.• Made minor modifications to circuit to support
scalability.
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Implementation of Hybrid Redundancy P
P
P
S Status reg Comp block
Voter
S
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Sift-Out Modular Redundancy• Implemented the design proposed by Paulo T. De
Sousa et al.• Made minor modifications
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Implementation of Sift-out Redundancy
comparator and registerE C
P1
P2
P3
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Pair and Spare
comparator
comparator
Switch
P1
P2
P3
P4
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Library Options
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Area and Delay Overhead
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Micro-op Generator
FSM D
Data PathMicro-op inst gen
Inst_gen
Inst_gen
Offset_reg_num_gen
Offset_gen
Offset_gen
Reg_num_gen
ALD
Priority Encoder
ALD
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Area Overhead for Micro-op Generator
• Area without FT – 7628.1
Module / FT technique
5MR Hybrid (3,2) Sift-out (5)
Data_path 28023.1 28220.7 28214.2
FSM 11215.3 11420.8 11415.7
Offset_Regnum gen
17925.6 18128.2 18123.4
Reg_Num_Gen 16968.4 17212 17205.3
Act low decoder 8378.1 8661.9 8656
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DUTs• PIIR filter• Micro-op Generator• 5 stage pipelined micro-processor
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Future Work• Other types of hardware redundancies can be
added to library modules without changing other parts of tools.
• Information redundancy can also be added, but it will involve change in the tool and will need more information from user.
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Conclusion• Tool that introduces fault tolerance in a Digital
System is successfully developed.• The tool is tested on three different designs.• Overhead of various fault tolerance techniques
is calculated and compared.
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Tools Used• Java• Perl• Design Vision• Quartus