TMS320F2809, F2808, F2806, F2802, F2801, F2801x...

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, UCD9501

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

Data Manual

Literature Number: SPRS230H

October 2003–Revised June 2006

UNLESS OTHERWISE NOTED this document containsPRODUCTION DATA information current as of publication date.Products conform to specifications per the terms of TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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Contents

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, UCD9501TMS320C2802, TMS320C2801, and TMS320F2801x DSPsSPRS230H–OCTOBER 2003–REVISED JUNE 2006

Revision History ........................................................................................................................... 91 F280x, F2801x, C280x, UCD9501 DSPs.................................................................................. 11

1.1 Features ..................................................................................................................... 112 Introduction ....................................................................................................................... 12

2.1 Pin Assignments............................................................................................................ 142.2 Signal Descriptions......................................................................................................... 19

3 Functional Overview ........................................................................................................... 253.1 Memory Maps............................................................................................................... 263.2 Brief Descriptions........................................................................................................... 32

3.2.1 C28x CPU ....................................................................................................... 333.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 333.2.3 Peripheral Bus .................................................................................................. 333.2.4 Real-Time JTAG and Analysis ................................................................................ 333.2.5 Flash .............................................................................................................. 343.2.6 ROM............................................................................................................... 343.2.7 M0, M1 SARAMs ............................................................................................... 343.2.8 L0, L1, H0 SARAMs ............................................................................................ 343.2.9 Boot ROM ........................................................................................................ 343.2.10 Security .......................................................................................................... 363.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................. 373.2.12 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 373.2.13 Oscillator and PLL .............................................................................................. 373.2.14 Watchdog ........................................................................................................ 373.2.15 Peripheral Clocking ............................................................................................. 373.2.16 Low-Power Modes .............................................................................................. 373.2.17 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 383.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 383.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 383.2.20 Control Peripherals ............................................................................................. 383.2.21 Serial Port Peripherals ......................................................................................... 39

3.3 Register Map................................................................................................................ 393.4 Device Emulation Registers............................................................................................... 413.5 Interrupts .................................................................................................................... 42

3.5.1 External Interrupts .............................................................................................. 443.6 System Control ............................................................................................................. 45

3.6.1 OSC and PLL Block ............................................................................................ 463.6.2 Watchdog Block ................................................................................................. 49

3.7 Low-Power Modes Block .................................................................................................. 504 Peripherals ........................................................................................................................ 51

4.1 32-Bit CPU-Timers 0/1/2 .................................................................................................. 514.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6).......................................................................... 534.3 Hi-Resolution PWM (HRPWM) ........................................................................................... 554.4 Enhanced CAP Modules (eCAP1/2/3/4) ................................................................................ 564.5 Enhanced QEP Modules (eQEP1/2)..................................................................................... 584.6 Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 604.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)..................................... 654.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) .................................................... 704.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)........................................... 734.10 Inter-Integrated Circuit (I2C)............................................................................................... 774.11 GPIO MUX .................................................................................................................. 79

2 Contents

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TMS320C2802, TMS320C2801, and TMS320F2801x DSPsSPRS230H–OCTOBER 2003–REVISED JUNE 2006

5 Device Support .................................................................................................................. 835.1 Device and Development Support Tool Nomenclature................................................................ 835.2 Documentation Support ................................................................................................... 85

6 Electrical Specifications ...................................................................................................... 876.1 Absolute Maximum Ratings............................................................................................... 876.2 Recommended Operating Conditions ................................................................................... 886.3 Electrical Characteristics ................................................................................................. 886.4 Current Consumption ..................................................................................................... 89

6.4.1 Reducing Current Consumption .............................................................................. 936.4.2 Current Consumption Graphs.................................................................................. 94

6.5 Timing Parameter Symbology ............................................................................................ 956.5.1 General Notes on Timing Parameters ........................................................................ 956.5.2 Test Load Circuit ................................................................................................ 966.5.3 Device Clock Table ............................................................................................. 96

6.6 Clock Requirements and Characteristics ............................................................................... 986.7 Power Sequencing ......................................................................................................... 99

6.7.1 Power Management and Supervisory Circuit Solutions .................................................... 996.8 General-Purpose Input/Output (GPIO)................................................................................. 102

6.8.1 GPIO - Output Timing ......................................................................................... 1026.8.2 GPIO - Input Timing ........................................................................................... 103

6.9 Enhanced Control Peripherals .......................................................................................... 1086.9.1 Enhanced Pulse Width Modulator (ePWM) Timing........................................................ 1086.9.2 Trip-Zone Input Timing ........................................................................................ 1086.9.3 External Interrupt Timing...................................................................................... 1106.9.4 I2C Electrical Specification and Timing...................................................................... 1116.9.5 Serial Peripheral Interface (SPI) Master Mode Timing.................................................... 1116.9.6 SPI Slave Mode Timing ....................................................................................... 1156.9.7 On-Chip Analog-to-Digital Converter ........................................................................ 118

6.10 Detailed Descriptions .................................................................................................... 1236.11 Flash Timing............................................................................................................... 1246.12 ROM Timing (C280x only) ............................................................................................... 125

7 Migrating From F280x Devices to C280x Devices.................................................................. 1267.1 Migration Issues........................................................................................................... 126

8 Mechanical Data ............................................................................................................... 127

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List of Figures2-1 TMS320F2808 100-Pin PZ LQFP (Top View)................................................................................. 152-2 TMS320F2806 100-Pin PZ LQFP (Top View)................................................................................. 162-3 TMS320F2802, TMS320F2801/UCD9501, TMS320C2802, TMS320C2801, TMS320F2801x 100-Pin PZ LQFP

(Top View) ......................................................................................................................... 172-4 TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,

TMS320C2802, TMS320C2801 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) ........................... 183-1 Functional Block Diagram........................................................................................................ 253-2 F2809 Memory Map .............................................................................................................. 263-3 F2808 Memory Map .............................................................................................................. 273-4 F2806 Memory Map .............................................................................................................. 283-5 F2802, C2802 Memory Map ..................................................................................................... 293-6 F2801/9501, F28015, F28016, C2801 Memory Map......................................................................... 303-7 External and PIE Interrupt Sources............................................................................................. 423-8 Multiplexing of Interrupts Using the PIE Block ................................................................................ 433-9 Clock and Reset Domains ....................................................................................................... 453-10 OSC and PLL Block Diagram ................................................................................................... 463-11 Using a 3.3-V External Oscillator ............................................................................................... 473-12 Using a 1.8-V External Oscillator ............................................................................................... 473-13 Using the Internal Oscillator ..................................................................................................... 473-14 Watchdog Module................................................................................................................. 494-1 CPU-Timers........................................................................................................................ 514-2 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 524-3 Multiple PWM Modules in a 280x System ..................................................................................... 534-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 554-5 eCAP Functional Block Diagram ................................................................................................ 564-6 eQEP Functional Block Diagram................................................................................................ 584-7 Block Diagram of the ADC Module ............................................................................................. 614-8 ADC Pin Connections With Internal Reference ............................................................................... 624-9 ADC Pin Connections With External Reference .............................................................................. 634-10 eCAN Block Diagram and Interface Circuit .................................................................................... 664-11 eCAN-A Memory Map ............................................................................................................ 674-12 eCAN-B Memory Map ............................................................................................................ 684-13 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 724-14 SPI Module Block Diagram (Slave Mode) ..................................................................................... 764-15 I2C Peripheral Module Interfaces ............................................................................................... 784-16 GPIO MUX Block Diagram....................................................................................................... 794-17 Qualification Using Sampling Window.......................................................................................... 825-1 Example of TMS320x280x Device Nomenclature ............................................................................ 845-2 Example of UCD Device Nomenclature........................................................................................ 846-1 Typical Operational Current Versus Frequency (F2808) .................................................................... 94

4 List of Figures

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6-2 Typical Operational Power Versus Frequency (F2808) ...................................................................... 946-3 3.3-V Test Load Circuit ........................................................................................................... 966-4 Clock Timing ....................................................................................................................... 996-5 Power-on Reset.................................................................................................................. 1006-6 Warm Reset ...................................................................................................................... 1016-7 Example of Effect of Writing Into PLLCR Register .......................................................................... 1026-8 General-Purpose Output Timing............................................................................................... 1026-9 Sampling Mode .................................................................................................................. 1036-10 General-Purpose Input Timing ................................................................................................. 1046-11 IDLE Entry and Exit Timing .................................................................................................... 1056-12 STANDBY Entry and Exit Timing Diagram................................................................................... 1066-13 HALT Wake-Up Using GPIOn ................................................................................................. 1076-14 PWM Hi-Z Characteristics ...................................................................................................... 1086-15 ADCSOCAO or ADCSOCBO Timing ......................................................................................... 1106-16 External Interrupt Timing ....................................................................................................... 1106-17 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 1136-18 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 1156-19 SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 1166-20 SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 1176-21 ADC Power-Up Control Bit Timing ............................................................................................ 1196-22 ADC Analog Input Impedance Model ......................................................................................... 1206-23 Sequential Sampling Mode (Single-Channel) Timing....................................................................... 1216-24 Simultaneous Sampling Mode Timing ........................................................................................ 122

List of Figures 5

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List of Tables2-1 Hardware Features (100-MHz Devices)........................................................................................ 132-2 Hardware Features (60-MHz Devices) ......................................................................................... 142-3 Signal Descriptions ............................................................................................................... 193-1 Addresses of Flash Sectors in F2809 .......................................................................................... 313-2 Addresses of Flash Sectors in F2808 .......................................................................................... 313-3 Addresses of Flash Sectors in F2806, F2802 ................................................................................. 313-4 Addresses of Flash Sectors in F2801/9501, F28015, F28016 .............................................................. 323-5 Wait-states ......................................................................................................................... 323-6 Boot Mode Selection.............................................................................................................. 353-7 Peripheral Frame 0 Registers ................................................................................................... 403-8 Peripheral Frame 1 Registers ................................................................................................... 403-9 Peripheral Frame 2 Registers ................................................................................................... 413-10 Device Emulation Registers ..................................................................................................... 413-11 PIE Peripheral Interrupts ......................................................................................................... 433-12 PIE Configuration and Control Registers ...................................................................................... 443-13 External Interrupt Registers...................................................................................................... 443-14 PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 463-15 PLLCR Register Bit Definitions.................................................................................................. 483-16 Possible PLL Configuration Modes ............................................................................................. 483-17 Low-Power Modes ................................................................................................................ 504-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 524-2 ePWM Control and Status Registers ........................................................................................... 544-3 eCAP Control and Status Registers ............................................................................................ 574-4 eQEP Control and Status Registers ............................................................................................ 594-5 ADC Registers..................................................................................................................... 644-6 3.3-V eCAN Transceivers ....................................................................................................... 664-7 CAN Register Map ................................................................................................................ 694-8 SCI-A Registers ................................................................................................................... 714-9 SCI-B Registers ................................................................................................................... 714-10 SPI-A Registers ................................................................................................................... 744-11 SPI-B Registers ................................................................................................................... 744-12 SPI-C Registers ................................................................................................................... 754-13 SPI-D Registers ................................................................................................................... 754-14 I2C-A Registers .................................................................................................................... 784-15 GPIO Registers ................................................................................................................... 804-16 F2808 GPIO MUX Table ......................................................................................................... 816-1 TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............................... 896-2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT .............................. 906-3 TMS320F2802, TMS320F2801/UCD9501 Current Consumption by Power-Supply Pins at 100-MHz

SYSCLKOUT ...................................................................................................................... 91

6 List of Tables

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6-4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ........... 926-5 Typical Current Consumption by Various Peripherals (at 100 MHz) ....................................................... 936-6 TMS320x280x Clock Table and Nomenclature (100-MHz Devices) ....................................................... 966-7 TMS320x280x Clock Table and Nomenclature (60-MHz Devices)......................................................... 976-8 Input Clock Frequency ........................................................................................................... 986-9 XCLKIN Timing Requirements - PLL Enabled ................................................................................ 986-10 XCLKIN Timing Requirements - PLL Disabled................................................................................ 986-11 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ......................................................... 986-12 Power Management and Supervisory Circuit Solutions...................................................................... 996-13 Reset (XRS) Timing Requirements ........................................................................................... 1016-14 General-Purpose Output Switching Characteristics......................................................................... 1026-15 General-Purpose Input Timing Requirements ............................................................................... 1036-16 IDLE Mode Timing Requirements ............................................................................................. 1056-17 IDLE Mode Switching Characteristics......................................................................................... 1056-18 STANDBY Mode Timing Requirements ...................................................................................... 1056-19 STANDBY Mode Switching Characteristics ................................................................................. 1066-20 HALT Mode Timing Requirements ............................................................................................ 1066-21 HALT Mode Switching Characteristics ....................................................................................... 1076-22 ePWM Timing Requirements................................................................................................... 1086-23 ePWM Switching Characteristics .............................................................................................. 1086-24 Trip-Zone input Timing Requirements ........................................................................................ 1086-25 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) .............................................. 1096-26 Enhanced Capture (eCAP) Timing Requirement............................................................................ 1096-27 eCAP Switching Characteristics ............................................................................................... 1096-28 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements.................................................... 1096-29 eQEP Switching Characteristics ............................................................................................... 1096-30 External ADC Start-of-Conversion Switching Characteristics.............................................................. 1106-31 External Interrupt Timing Requirements ...................................................................................... 1106-32 External Interrupt Switching Characteristics ................................................................................. 1106-33 I2C Timing ........................................................................................................................ 1116-34 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 1126-35 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 1146-36 SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 1156-37 SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 1166-38 ADC Electrical Characteristics (over recommended operating conditions) .............................................. 1186-39 ADC Power-Up Delays.......................................................................................................... 1196-40 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)....................................... 1196-41 Sequential Sampling Mode Timing ............................................................................................ 1216-42 Simultaneous Sampling Mode Timing ........................................................................................ 1226-43 Flash Endurance................................................................................................................. 1246-44 Flash Parameters at 100-MHz SYSCLKOUT................................................................................ 124

List of Tables 7

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6-45 Flash/OTP Access Timing...................................................................................................... 1246-46 Minimum Required Flash/OTP Wait-States at Different Frequencies .................................................... 1256-47 ROM/OTP Access Timing ...................................................................................................... 1256-48 ROM/ROM (OTP area) Minimum Required Wait-States at Different Frequencies ..................................... 1258-1 F280x, UCD9501 Thermal Model 100-pin GGM Results .................................................................. 1278-2 F280x, UCD9501 Thermal Model 100-pin PZ Results ..................................................................... 1278-3 C280x Thermal Model 100-pin GGM Results................................................................................ 1278-4 C280x Thermal Model 100-pin PZ Results................................................................................... 127

8 List of Tables

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Revision History



This data manual was revised from SPRS230G to SPRS230H.

Scope: Added information/data on TMS320F2801-60, TMS320F2802-60, TMS320F28015, andTMS320F28016.• Information/data on TMS320F2809 is PRODUCT PREVIEW.

– PRODUCT PREVIEW information concerns products in the formative or design phase ofdevelopment. Characteristic data and other specifications are design goals. Texas Instrumentsreserves the right to change or discontinue these products without notice.

• Information/data on TMS320F2802, TMS320F28015, TMS320F28016, TMS320C2802, andTMS320C2801 is PRODUCTION DATA.– PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty. Production processing doesnot necessarily include testing of all parameters.

This document has been reviewed for technical accuracy; the technical content is up to date as of thespecified release date with the following changes:

Technical Changes Made for Revision H

Location Additions, Deletions, Changes

Global Added information/data on TMS320F28015

Added information/data on TMS320F28016

Added information/data on TMS320C2802-60

Added information/data on TMS320C2801-60

Section 1.1 Added 60-MHz devices to first bullet (High-Performance static CMOS Technology) and memoryinformation on F28015, F28016 to the fourth bullet (On-Chip Memory) in the Features list

Section 2 Added new devices to the Introduction opening paragraph

Table 2-2 Added a new hardware features table for the 60-MHz devices

Figure 2-1 Corrected pin 48 to GPIO3, not GPIO2 in PZ pinout for the F2808

Figure 2-3 Added a note to the pinout

Figure 3-1 Added the F2801x devices to the Flash block on the functional block diagram

Figure 3-2 Added memory map for F2809 device

Table 3-15 Modified PLLCR Register Bit Definitions table and notes under it

Table 4-2 Changed TBCNT to TBCTR in ePWM Control and Status Registers table

Figure 5-1 Modified example of device nomenclature figure to include F2801x devices and -60 for 60-MHzdevices

Table 6-8 Changed values for external oscillator/clock source (XCLKIN or X1 pin) With PLL

Figure 6-2 Added a note under Typical Operational Power Versus Frequency (F2808) figure for F2801x devices

Table 6-7 Added clock table and nomenclature table for 60-MHz devices

Table 6-8 Added 60-MHz device values to Input Clock Frequency table

Table 6-10 Added 60-MHz device values to XCLKIN Timing Requirements - PLL Disabled table

Table 6-11 Added 60-MHz device values to XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)table

Figure 6-17 Added to note under SPI Master Mode External Timing (Clock Phase = 0) figure

Figure 6-18 Added to note under SPI Master Mode External Timing (Clock Phase = 1) figure

Table 6-45 Deleted note and added Flash to equations following the Flash/OTP Access Timing table. Alsoadded equation to compute the OTP wait-state.

Table 6-46 Added a column for OTP Wait-State, added a row for 60 MHz devices and added the word "Flash"to the title and two column headers in Minimum Required Flash Wait-States at Different Frequenciestable

Section 6.12 Modified section title by adding (C280x only)

Table 6-47 Modified ROM/OTP Access Timing table and added ROM to equations below it

Table 6-48 Modified title of ROM/ROM (OTP area) Minimum Required Wait-States at Different Frequenciestable by adding ROM/ROM (OTP area)

Revision History 9

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Revision History10

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1 F280x, F2801x, C280x, UCD9501 DSPs

1.1 Features



– Up to 6 HRPWM Outputs With 150 ps MEP• High-Performance Static CMOS TechnologyResolution– 100 MHz (10-ns Cycle Time)

– Up to Four Capture Inputs– 60 MHz (16.67-ns Cycle Time)– Up to Two Quadrature Encoder Interfaces– Low-Power (1.8-V Core, 3.3-V I/O) Design– Up to Six 32-bit/Six 16-bit Timers• JTAG Boundary Scan Support (1)

• Serial Port Peripherals• High-Performance 32-Bit CPU (TMS320C28x)

– Up to 4 SPI Modules– 16 x 16 and 32 x 32 MAC Operations

– Up to 2 SCI (UART) Modules– 16 x 16 Dual MAC

– Up to 2 CAN Modules– Harvard Bus Architecture

– One Inter-Integrated-Circuit (I2C) Bus– Atomic Operations

• 12-Bit ADC, 16 Channels– Fast Interrupt Response and Processing– 2 x 8 Channel Input Multiplexer– Unified Memory Programming Model– Two Sample-and-Hold– Code-Efficient (in C/C++ and Assembly)– Single/Simultaneous Conversions

• On-Chip Memory– Fast Conversion Rate:

– F2809: 128K X 16 Flash, 18K X 16 SARAM 80 ns - 12.5 MSPS (F2809 only)F2808: 64K X 16 Flash, 18K X 16 SARAM 160 ns - 6.25 MSPS (280x, 9501)F2806: 32K X 16 Flash, 10K X 16 SARAM 267 ns - 3.75 MSPS (F2801x)F2802: 32K X 16 Flash, 6K X 16 SARAM

– Internal or External ReferenceF2801: 16K X 16 Flash, 6K X 16 SARAM• Up to 35 Individually Programmable,9501: 16K X 16 Flash, 6K X 16 SARAM

Multiplexed GPIO Pins With Input FilteringF2801x: 16K X 16 Flash, 6K X 16 SARAM– 1K x 16 OTP ROM (Flash Devices Only) • Advanced Emulation Features– C2802: 32K X 16 ROM, 6K X 16 SARAM – Analysis and Breakpoint Functions

C2801: 16K X 16 ROM, 6K X 16 SARAM – Real-Time Debug via Hardware• Boot ROM (4K x 16) • Development Support Includes

– With Software Boot Modes (via SCI, SPI, – ANSI C/C++ Compiler/Assembler/LinkerCAN, I2C, and Parallel I/O) – Code Composer Studio™ IDE

– Standard Math Tables – DSP/BIOS™• Clock and System Control – Digital Motor Control and Digital Power

– Dynamic PLL Ratio Changes Supported Software Libraries– On-Chip Oscillator • Low-Power Modes and Power Savings– Watchdog Timer Module – IDLE, STANDBY, HALT Modes Supported

• Any GPIO A Pin Can Be Connected to One of – Disable Individual Peripheral Clocksthe Three External Core Interrupts • Package Options

• Peripheral Interrupt Expansion (PIE) Block – Thin Quad Flatpack (PZ)That Supports All 43 Peripheral Interrupts – MicroStar BGA™ (GGM, ZGM)

• 128-Bit Security Key/Lock • Temperature Options:– Protects Flash/OTP/L0/L1 Blocks – A: -40°C to 85°C (PZ, GGM, ZGM)– Prevents Firmware Reverse Engineering – S: -40°C to 125°C (PZ, GGM, ZGM)

• Three 32-Bit CPU Timers – Q: -40°C to 125°C (PZ)• Enhanced Control Peripherals

– Up to 16 PWM Outputs

(1) IEEE Standard 1149.1-1990 Standard Test Access Port andBoundary Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this document.

Code Composer Studio, DSP/BIOS, MicroStar BGA, TMS320C28x, C28x, TMS320C2000 are trademarks of Texas Instruments.eZdsp is a trademark of Spectrum Digital.

UNLESS OTHERWISE NOTED this document contains Copyright © 2003–2006, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date.Products conform to specifications per the terms of TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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2 Introduction


The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F28015,TMS320F28016, TMS320C2802, and TMS320C2801, devices, members of the TMS320C28x™ DSPgeneration, are highly integrated, high-performance solutions for demanding control applications.UCD9501 is a member of the same device family specifically targeting power management controlapplications.

Throughout this document, TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802,TMS320F2801/UCD9501, TMS320C2802, TMS320C2801, TMS320F28015, and TMS32028016 areabbreviated as F2809, F2808, F2806, F2802, F2801/9501, F28015, F28016, C2802, and C2801,respectively. TMS320F28015 and TMS320F28016 are abbreviated as F2801x. TMS320x280x devicereference guides, flash tools, and other collateral are applicable to the UCD9501 device as well. Table 2-1provides a summary of features for each device.

NOTEInformation/data on TMS320F2809 is PRODUCT PREVIEW.

PRODUCT PREVIEW information concerns products in the formative or design phase ofdevelopment. Characteristic data and other specifications are design goals. TexasInstruments reserves the right to change or discontinue these products without notice.

12 Introduction

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Table 2-1. Hardware Features (100-MHz Devices)

FEATURE F2809 F2808 F2806 F2802 F2801/ 9501 C2802 C2801

Instruction cycle (at 100 MHz) 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns

18K 18K 10K 6K 6K 6K 6KSingle-access RAM (SARAM) (16-bit word) (L0, L1, M0, M1, (L0, L1, M0, M1, (L0, L1, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)H0) H0)

3.3-V on-chip flash (16-bit word) 128K 64K 32K 32K 16K – –

On-chip ROM (16-bit word) – – – – – 32K 16K

Code security for on-chip flash/SARAM/OTP blocks Yes Yes Yes Yes Yes Yes Yes

Boot ROM (4K X16) Yes Yes Yes Yes Yes Yes Yes

One-time programmable (OTP) ROM 1K 1K 1K 1K 1K – –(16-bit word)

PWM outputs ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3

ePWM1A/2A/3A/ ePWM1A/2A/ ePWM1A/2A/HRPWM channels ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A4A/5A/6A 3A/4A 3A/4A

32-bit CAPTURE inputs or auxiliary PWM outputs eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2

32-bit QEP channels (four inputs/channel) eQEP1/2 eQEP1/2 eQEP1/2 eQEP1 eQEP1 eQEP1 eQEP1

Watchdog timer Yes Yes Yes Yes Yes Yes Yes

12-Bit, 16-channel ADC conversion time 80 ns 160 ns 160 ns 160 ns 160 ns 160 ns 160 ns

32-Bit CPU timers 3 3 3 3 3 3 3

Serial Peripheral Interface (SPI) SPI-A/B/C/D SPI-A/B/C/D SPI-A/B/C/D SPI-A/B SPI-A/B SPI-A/B SPI-A/B

Serial Communications Interface (SCI) SCI-A/B SCI-A/B SCI-A/B SCI-A SCI-A SCI-A SCI-A

Enhanced Controller Area Network (eCAN) eCAN-A/B eCAN-A/B eCAN-A eCAN-A eCAN-A eCAN-A eCAN-A

Inter-Integrated Circuit (I2C) I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A

Digital I/O pins (shared) 35 35 35 35 35 35 35

External interrupts 3 3 3 3 3 3 3

Supply voltage 1.8-V Core, 3.3-V I/O Yes Yes Yes Yes Yes Yes Yes

100-Pin PZ Yes Yes Yes Yes Yes Yes YesPackaging

100-Ball GGM, ZGM Yes Yes Yes Yes Yes Yes Yes

A: -40°C to 85°C (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Temperature options (1) S: -40°C to 125°C (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Q: -40°C to 125°C (PZ) (PZ) (PZ) (PZ) (PZ) (PZ) (PZ)

Product status (2) TMX TMS TMS TMS TMS TMS TMS

(1) The UCD9501 device is not available in the Q temperature option or in ZGM/GGM packages.(2) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages. TMX is an experimental device that is not necessarily representative of the final

device's electrical specifications. TMS is a fully qualified production device. For UCD9501, the production qualified device is labeled UCD9501.

Introduction 13

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2.1 Pin Assignments


Table 2-2. Hardware Features (60-MHz Devices)

FEATURE F2802-60 F2801-60 F28016 F28015

Instruction cycle (at 60 MHz) 16.67 ns 16.67 ns 16.67 ns 16.67 ns

6K 6K 6K 6KSingle-access RAM (SARAM) (16-bit word) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)

3.3-V on-chip flash (16-bit word) 32K 16K 16K 16K

On-chip ROM (16-bit word) – – – –

Code security for on-chip flash/SARAM/OTP Yes Yes Yes Yesblocks

Boot ROM (4K X16) Yes Yes Yes Yes

One-time programmable (OTP) ROM 1K 1K 1K 1K(16-bit word)

PWM outputs ePWM1/2/3 ePWM1/2/3 ePWM1/2/3/4 ePWM1/2/3/4

HRPWM channels ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A/4A ePWM1A/2A/3A/4A

32-bit CAPTURE inputs or auxiliary PWM eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2outputs

32-bit QEP channels (four inputs/channel) eQEP1 eQEP1 - -

Watchdog timer Yes Yes Yes Yes

No. of channels 16 16 16 16

12-Bit ADC MSPS 3.75 3.75 3.75 3.75

Conversion time 267 ns 267 ns 267 ns 267 ns

32-Bit CPU timers 3 3 3 3

Serial Peripheral Interface (SPI) SPI-A/B SPI-A/B SPI-A SPI-A

Serial Communications Interface (SCI) SCI-A SCI-A SCI-A SCI-A

Enhanced Controller Area Network (eCAN) eCAN-A eCAN-A eCAN-A

Inter-Integrated Circuit (I2C) I2C-A I2C-A I2C-A I2C-A

Digital I/O pins (shared) 35 35 35 35

External interrupts 3 3 3 3

1.8-V Core, 1.8-V Core, 1.8-V Core, 1.8-V Core,Supply voltage 3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O

Packaging 100-Pin PZ Yes Yes Yes Yes

A: -40°C to 85°C (PZ) (PZ) (PZ) (PZ)

Temperature options S: -40°C to 125°C (PZ) (PZ) (PZ) (PZ)

Q: -40°C to 125°C (PZ) (PZ) (PZ) (PZ)

Product status (1) TMS TMS TMS TMS

(1) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages. TMX is an experimental device thatis not necessarily representative of the final device's electrical specifications. TMS is a fully qualified production device. For UCD9501,the production qualified device is labeled UCD9501.

The TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801/UCD9501, TMS320C2802,TMS320C2801, TMS320F28015, and TMS320F28016 100-pin PZ low-profile quad flatpack (LQFP) pinassignments are shown in Figure 2-1, Figure 2-2 and Figure 2-3. The F2801-60 and F2802-60 areavailable only in the PZ package. The TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801,TMS320C2802, and TMS320C2801 100-ball GGM and ZGM ball grid array (BGA) terminal assignmentsare shown in Figure 2-4. Table 2-3 describes the function(s) of each pin.

14 Introduction

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26

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77

78

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83

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90

91

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94

95

96

97

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100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

GPIO0/EPWM1A

TC

K

TM

S

TD

I

GP

IO23

/EQ

EP

1I/S

PIS

TE

C/S

CIR

XD

BG

PIO

22/E

QE

P1S

/SP

ICL

KC

/SC

ITX

DB

GP

IO11

/EP

WM

6B/S

CIR

XD

B/E

CA

P4

GP

IO21

/EQ

EP

1B/S

PIS

OM

IC/C

AN

RX

B

XC

LK

OU

T

GP

IO20

/EQ

EP

1A/S

PIS

IMO

C/C

AN

TX

B

GP

IO9/

EP

WM

5B/S

CIT

XD

B/E

CA

P3

GP

IO7/

EP

WM

4B/S

PIS

TE

D/E

CA

P2

GP

IO19

/SP

IST

EA

/SC

IRX

DB

GP

IO6/

EP

WM

4A/E

PW

MS

YN

CI/E

PW

MS

YN

CO

GP

IO18

/SP

ICL

KA

/SC

ITX

DB

GP

IO5/

EP

WM

3B/S

PIC

LK

D/E

CA

P1

GP

IO4/

EP

WM

3A

XRS

TRST

VS

S

VD

D

VD

DIO

GP

IO10

/EP

WM

6A/C

AN

RX

B/A

DC

SO

CB

O

VS

S

GP

IO8/

EP

WM

5A/C

AN

TX

B/A

DC

SO

CA

OV

DD

VS

S

GP

IO17

/SP

ISO

MIA

/CA

NR

XB

/TZ

6

VSS

VSS

VDD

VDDIO

GPIO16/SPISIMOA/CANTXB/TZ5

VDD2A18VSS2AGND

VDDAIO

GP

IO12

/TZ

1/C

AN

TX

B/S

PIS

IMO

B

VS

SV

DD

IO

GP

IO29

/SC

ITX

DA

/TZ

6

GP

IO33

/SC

LA

/EP

WM

SY

NC

O/A

DC

SO

CB

O

GP

IO14

/TZ

3/S

CIT

XD

B/S

PIC

LK

B

VS

S

VD

D

VD

D1A

18

VS

S1A

GN

D

VS

SA

2V

DD

A2

GP

IO15

/TZ

4/S

CIR

XD

B/S

PIS

TE

B

VS

SA

IO

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO13/TZ2/CANRXB/SPISOMIBVDD3VFL

VSS

VDD

GPIO28/SCIRXDA/TZ5

VSS

VSS

VDD

VSS

VDDIO

GPIO26/ECAP3/EQEP2I/SPICLKB

TEST2TEST1

GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

X1

X2

EMU1

EMU0

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO

GP

IO30

/CA

NR

XA

GP

IO31

/CA

NT

XA

AD

CIN

A7

AD

CIN

A6

AD

CIN

A5

AD

CIN

A4

AD

CIN

A3

AD

CIN

A2

AD

CIN

A1

AD

CIN

A0

AD

CL

O

ADCINB0

ADCINB1

ADCINB2ADCINB3

ADCINB4ADCINB5ADCINB6

ADCINB7ADCREFIN

ADCREFMADCREFP

ADCRESEXT

GPIO34

GPIO1/EPWM1B/SPISIMODGPIO2/EPWM2A

GPIO3/EPWM2B/SPISOMID



A. F2809 is pin-compatible to F2808.

Figure 2-1. TMS320F2808 100-Pin PZ LQFP (Top View)

Introduction 15

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75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

GPIO3/EPWM2B/SPISOMID

GPIO0/EPWM1A

GPIO2/EPWM2A

GPIO1/EPWM1B/SPISIMODGPIO34

ADCRESEXT

ADCREFP

ADCREFM

ADCREFINADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCINB3ADCINB2

ADCINB1

ADCINB0

TC

K

TM

S

TD

I

GP

IO23

/EQ

EP

1I/S

PIS

TE

C/S

CIR

XD

BG

PIO

22/E

QE

P1S

/SP

ICL

KC

/SC

ITX

DB

XC

LK

OU

T

GP

IO20

/EQ

EP

1A/S

PIS

IMO

C

GP

IO9/

EP

WM

5B/S

CIT

XD

B/E

CA

P3

GP

IO7/

EP

WM

4B/S

PIS

TE

D/E

CA

P2

GP

IO19

/SP

IST

EA

/SC

IRX

DB

GP

IO6/

EP

WM

4A/E

PW

MS

YN

CI/E

PW

MS

YN

CO

GP

IO18

/SP

ICL

KA

/SC

ITX

DB

GP

IO5/

EP

WM

3B/S

PIC

LK

D/E

CA

P1

GP

IO4/

EP

WM

3A

GP

IO30

/CA

NR

XA

GP

IO31

/CA

NT

XA

AD

CIN

A7

AD

CIN

A6

AD

CIN

A5

AD

CIN

A4

AD

CIN

A3

AD

CIN

A2

AD

CIN

A1

AD

CIN

A0

AD

CL

O

XRS

TRST

GP

IO11

/EP

WM

6B/S

CIR

XD

B/E

CA

P4

GP

IO21

/EQ

EP

1B/S

PIS

OM

IC

VSS

VSS

VDD

VDDIO

GPIO16/SPISIMOA/TZ5

VDD2A18VSS2AGND

VDDAIO

VS

S

VD

D

VD

DIO

GP

IO10

/EP

WM

6A/A

DC

SO

CB

O

VS

S

GP

IO8/

EP

WM

5A/A

DC

SO

CA

OV

DD

VS

S

GP

IO17

/SP

ISO

MIA

/TZ

6

VDD3VFL

VSS

VDD

GPIO28/SCIRXDA/TZ5

VSS

VSS

VDD

VSS

VDDIO

GPIO13/TZ2/SPISOMIB

GP

IO12

/TZ

1/S

PIS

IMO

B

GP

IO29

/SC

ITX

DA

/TZ

6

GP

IO33

/SC

LA

/EP

WM

SY

NC

O/A

DC

SO

CB

O

GP

IO14

/TZ

3/S

CIT

XD

B/S

PIC

LK

B

VD

D

VD

D1A

18V

SS

1AG

ND

VS

SA

2

VD

DA

2

GP

IO15

/TZ

4/S

CIR

XD

B/S

PIS

TE

B

VS

SA

IO

VS

S

VD

DIO

GPIO32/SDAA/EPWMSYNCI/ADCSOCAOGPIO26/ECAP3/EQEP2I/SPICLKB

TEST2TEST1

GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

X1

X2

GPIO24/ECAP1/EQEP2A/SPISIMOB

EMU1EMU0

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO

VS

S


Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View)

16 Introduction

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75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

GPIO0/EPWM1A

GPIO2/EPWM2AGPIO1/EPWM1B

GPIO34

ADCRESEXT

ADCREFP

ADCREFM

ADCREFINADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCINB3ADCINB2

ADCINB1

ADCINB0

TC

K

TM

S

TD

I

XC

LK

OU

T

GP

IO30

/CA

NR

XA

GP

IO31

/CA

NT

XA

AD

CIN

A7

AD

CIN

A6

AD

CIN

A5

AD

CIN

A4

AD

CIN

A3

AD

CIN

A2

AD

CIN

A1

AD

CIN

A0

AD

CL

O

XRS

TRST

GP

IO12

/TZ

1/S

PIS

IMO

B

VS

S

VD

DIO

GP

IO29

/SC

ITX

DA

/TZ

6

GP

IO33

/SC

LA

/EP

WM

SY

NC

O/A

DC

SO

CB

O

GP

IO14

/TZ

3/S

PIC

LK

B

VS

S

VD

D

VD

D1A

18

VS

S1A

GN

D

VS

SA

2V

DD

A2

GPIO32/SDAA/EPWMSYNCI/ADSOCAO

GPIO13/TZ2/SPISOMIB

VDD3VFL(A)

VSS

VDD

GPIO28/SCIRXDA/TZ5

VSS

VSS

VDD

GP

IO21

/EQ

EP

1B

VS

SV

DD

GP

IO23

/EQ

EP

1I

GP

IO22

/EQ

EP

1S

VD

DIO

GP

IO10

/AD

CS

OC

BO

GP

IO20

/EQ

EP

1AV

SS

GP

IO9

GP

IO8/

AD

CS

OC

AO

VD

D

GP

IO7/

EC

AP

2

GP

IO19

/SP

IST

EA

GP

IO6/

EP

WM

SY

NC

I/EP

WM

SY

NC

O

GP

IO11

VS

SG

PIO

18/S

PIC

LK

AG

PIO

5/E

PW

M3B

/EC

AP

1

GP

IO17

/SP

ISO

MIA

/TZ

6

GP

IO4/

EP

WM

3A

VSS

VSS

VDD

VDDIO

GPIO16/SPISIMOA/TZ5

GPIO3/EPWM2B

VDD2A18VSS2AGND

VDDAIO

GP

IO15

/TZ

4/S

PIS

TE

B

VSS

GPIO27/SPISTEB

VDDIOGPIO24/ECAP1/SPISIMOB

VS

SA

IO

GPIO25/ECAP2/SPISIMOB

GPIO26/SPICLKB

TEST2TEST1

XCLKIN

X1

X2

EMU1

EMU0

TDO



A. On the C280x devices, the VDD3VFL pin is VDDIO.

B. Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.

Figure 2-3. TMS320F2802, TMS320F2801/UCD9501, TMS320C2802, TMS320C2801, TMS320F2801x 100-PinPZ LQFP

(Top View)

Introduction 17

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4

C

B

A

D

E

21 3

K

F

G

H

J

5 76 98 10

Bottom View

TRST TCK

TDI

TDO TMS

EMU0

EMU1

VDD3VFL

TEST1

TEST2

��

XCLKIN

X1

X2

XRS

GPIO0GPIO1

GPIO2 GPIO3 GPIO4

GPIO5

GPIO6GPIO7

GPIO9 GPIO8

GPIO10

GPIO11

GPIO12 GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23GPIO24GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30GPIO31

GPIO32

GPIO33

GPIO34

VDDA2

�� VDD

VDDIO

VSSAIO

VDDAIO

VSSA2 ��

��

VDD2A18

VDD

VDD

VDD

VDD

VDD

VDDIO

VDDIO

VDDIO

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSVSS

��

��

��ADCINA4 ��

ADCINA1 ��

��

ADCINB1

ADCINB0

ADCLO

��

��

��

��

ADCINB3 ��

ADCINB4

��


Figure 2-4. TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,TMS320C2802, TMS320C2801 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)

Introduction18

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2.2 Signal Descriptions



Table 2-3 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outputs are3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Table 2-3. Signal Descriptions

PIN NO.

GGM/NAME DESCRIPTION (1)PZ ZGMPIN # BALL #

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control ofthe operations of the device. If this signal is not connected or driven low, the device operates in itsfunctional mode, and the test reset signals are ignored.NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an activehigh test pin and must be maintained low at all times during normal device operation. In a low-noiseTRST 84 A6 environment, TRST may be left floating. In other instances, an external pulldown resistor is highlyrecommended. The value of this resistor should be based on drive strength of the debugger podsapplicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this isapplication-specific, it is recommended that each target board be validated for proper operation ofthe debugger and the application. (I, ↓)

TCK 75 A10 JTAG test clock with internal pullup (I, ↑)

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAPTMS 74 B10 controller on the rising edge of TCK. (I, ↑)

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instructionTDI 73 C9 or data) on a rising edge of TCK. (I, ↑)

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)TDO 76 B9 are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulatorsystem and is defined as input/output through the JTAG scan. This pin is also used to put thedevice into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at alogic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

EMU0 80 A8 (I/O/Z, 8 mA drive ↑)NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should bebased on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩresistor is generally adequate. Since this is application-specific, it is recommended that each targetboard be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulatorsystem and is defined as input/output through the JTAG scan. This pin is also used to put thedevice into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at alogic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

EMU1 81 B7 (I/O/Z, 8 mA drive ↑)NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should bebased on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩresistor is generally adequate. Since this is application-specific, it is recommended that each targetboard be validated for proper operation of the debugger and the application.

FLASH

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROMVDD3VFL 96 C4 parts (C280x), this pin should be connected to VDDIO.

TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half thefrequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0

XCLKOUT 66 E8 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signalcan be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is notplaced in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,XCLKIN 90 B5 the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is

used to feed clock to X1 pin), this pin must be tied to GND. (I)

(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown

Introduction 19

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Table 2-3. Signal Descriptions (continued)

PIN NO.


Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramicresonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital

X1 88 E6 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKINpin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 mustbe tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 andX2 86 C6 X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out).Device reset. XRS causes the device to terminate execution. The PC will point to the addresscontained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at thelocation pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.XRS 78 B8 During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLKcycles. (I/OD, ↑)The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). It isrecommended that this pin be driven by an open-drain device.

ADC SIGNALS

ADCINA7 16 F3 ADC Group A, Channel 7 input (I)

ADCINA6 17 F4 ADC Group A, Channel 6 input (I)

ADCINA5 18 G4 ADC Group A, Channel 5 input (I)




ADCINA1 22 H1 ADC Group A, Channel 1 input (I)

ADCINA0 23 H2 ADC Group A, Channel 0 input (I)

ADCINB7 34 K5 ADC Group B, Channel 7 input (I)

ADCINB6 33 H4 ADC Group B, Channel 6 input (I)


ADCINB4 31 J4 ADC Group B, Channel 4 input (I)


ADCINB2 29 H3 ADC Group B, Channel 2 input (I)

ADCINB1 28 J3 ADC Group B, Channel 1 input (I)


ADCLO 24 J1 Low Reference (connect to analog ground) (I)

ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.

ADCREFIN 35 J5 External reference input (I)

Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitorADCREFP 37 G5 of 2.2 µF to analog ground. (O)

Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitorADCREFM 36 H5 of 2.2 µF to analog ground. (O)

CPU AND I/O POWER PINS

VDDA2 15 F2 ADC Analog Power Pin (3.3 V)

VSSA2 14 F1 ADC Analog Ground Pin

VDDAIO 26 J2 ADC Analog I/O Power Pin (3.3 V)

VSSAIO 25 K1 ADC Analog I/O Ground Pin

VDD1A18 12 E4 ADC Analog Power Pin (1.8 V)

VSS1AGND 13 E5 ADC Analog Ground Pin

VDD2A18 40 J6 ADC Analog Power Pin (1.8 V)

VSS2AGND 39 K6 ADC Analog Ground Pin

20 Introduction

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PIN NO.


VDD 10 E2

VDD 42 G6

VDD 59 F10CPU and Logic Digital Power Pins (1.8 V)

VDD 68 D7

VDD 85 B6

VDD 93 D4

VDDIO 3 C2

VDDIO 46 H7Digital I/O Power Pin (3.3 V)

VDDIO 65 E9

VDDIO 82 A7

VSS 2 B1

VSS 11 E3

VSS 41 H6

VSS 49 K9

VSS 55 H10

VSS 62 F7 Digital Ground Pins

VSS 69 D10

VSS 77 A9

VSS 87 D6

VSS 89 A5

VSS 94 A4

GPIOA AND PERIPHERAL SIGNALS (2) (3)

GPIO0 General purpose input/output 0 (I/O/Z) (4)EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)47 K8- -- -

GPIO1 General purpose input/output 1 (I/O/Z) (4)EPWM1B Enhanced PWM1 Output B (O)44 K7SPISIMOD SPI-D slave in, master out (I/O) (not available on 2801/9501, 2802)- -

GPIO2 General purpose input/output 2 (I/O/Z) (4)EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)45 J7- -- -

GPIO3 General purpose input/output 3 (I/O/Z) (4)EPWM2B Enhanced PWM2 Output B (O)48 J8SPISOMID SPI-D slave out, master in (I/O) (not available on 2801/9501, 2802)- -

GPIO4 General purpose input/output 4 (I/O/Z) (4)EPWM3A Enhanced PWM3 output A and HRPWM channel (O)51 J9- -- -

GPIO5 General purpose input/output 5 (I/O/Z) (4)EPWM3B Enhanced PWM3 output B (O)53 H9SPICLKD SPI-D clock (I/O) (not available on 2801/9501, 2802)ECAP1 Enhanced capture input/output 1 (I/O)

(2) Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.(3) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default atreset. The peripheral signals that are listed under them are alternate functions.

(4) The pullups on GPIO0-GPIO11 pins are not enabled at reset.

Introduction 21

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PIN NO.


GPIO6 General purpose input/output 6 (I/O/Z) (4)EPWM4A Enhanced PWM4 output A and HRPWM channel (not available on 2801/9501, 2802) (O)56 G9EPWMSYNCI External ePWM sync pulse input (I)EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General purpose input/output 7 (I/O/Z) (4)EPWM4B Enhanced PWM4 output B (not available on 2801/9501, 2802) (O)58 G8SPISTED SPI-D slave transmit enable (not available on 2801/9501, 2802) (I/O)ECAP2 Enhanced capture input/output 2 (I/O)

GPIO8 General purpose input/output 8 (I/O/Z) (4)EPWM5A Enhanced PWM5 output A (not available on 2801/9501, 2802) (O)60 F9CANTXB Enhanced CAN-B transmit (not available on 2801/9501, 2802, F2806) (O)ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General purpose input/output 9 (I/O/Z) (4)EPWM5B Enhanced PWM5 output B (not available on 2801/9501, 2802) (O)61 F8SCITXDB SCI-B transmit data (not available on 2801/9501, 2802) (O)ECAP3 Enhanced capture input/output 3 (not available on 2801/9501, 2802) (I/O)

GPIO10 General purpose input/output 10 (I/O/Z) (4)EPWM6A Enhanced PWM6 output A (not available on 2801/9501, 2802) (O)64 E10CANRXB Enhanced CAN-B receive (not available on 2801/9501, 2802, F2806) (I)ADCSOCBO ADC start-of-conversion B (O)

GPIO11 General purpose input/output 11 (I/O/Z) (4)EPWM6B Enhanced PWM6 output B (not available on 2801/9501, 2802) (O)70 D9SCIRXDB SCI-B receive data (not available on 2801/9501, 2802) (I)ECAP4 Enhanced CAP Input/Output 4 (not available on 2801/9501, 2802) (I/O)

GPIO12 General purpose input/output 12 (I/O/Z) (5)TZ1 Trip Zone input 1 (I)1 B2CANTXB Enhanced CAN-B transmit (not available on 2801/9501, 2802, F2806) (O)SPISIMOB SPI-B Slave in, Master out (I/O)

GPIO13 General purpose input/output 13 (I/O/Z) (5)TZ2 Trip zone input 2 (I)95 B4CANRXB Enhanced CAN-B receive (not available on 2801/9501, 2802, F2806) (I)SPISOMIB SPI-B slave out, master in (I/O)

GPIO14 General purpose input/output 14 (I/O/Z) (5)TZ3 Trip zone input 3 (I)8 D3SCITXDB SCI-B transmit (not available on 2801/9501, 2802) (O)SPICLKB SPI-B clock input/output (I/O)

GPIO15 General purpose input/output 15 (I/O/Z) (5)TZ4 Trip zone input (I)9 E1SCIRXDB SCI-B receive (not available on 2801/9501, 2802) (I)SPISTEB SPI-B slave transmit enable (I/O)

GPIO16 General purpose input/output 16 (I/O/Z) (5)SPISIMOA SPI-A slave in, master out (I/O)50 K10CANTXB Enhanced CAN-B transmit (not available on 2801/9501, 2802, F2806) (O)TZ5 Trip zone input 5 (I)

GPIO17 General purpose input/output 17 (I/O/Z) (5)SPISOMIA SPI-A slave out, master in (I/O)52 J10CANRXB Enhanced CAN-B receive (not available on 2801/9501, 2802, F2806) (I)TZ6 Trip zone input 6(I)

GPIO18 General purpose input/output 18 (I/O/Z) (5)SPICLKA SPI-A clock input/output (I/O)SCITXDB 54 H8 SCI-B transmit (not available on 2801/9501, 2802) (O)- -- -

GPIO19 General purpose input/output 19 (I/O/Z) (5)SPISTEA SPI-A slave transmit enable input/output (I/O)SCIRXDB 57 G10 SCI-B receive (not available on 2801/9501, 2802) (I)- -- -

(5) The pullups on GPIO12-GPIO34 are enabled upon reset.

22 Introduction

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PIN NO.


GPIO20 General purpose input/output 20 (I/O/Z) (5)EQEP1A Enhanced QEP1 input A (I)63 F6SPISIMOC SPI-C slave in, master out (not available on 2801/9501, 2802) (I/O)CANTXB Enhanced CAN-B transmit (not available on 2801/9501, 2802, F2806) (O)

GPIO21 General purpose input/output 21 (I/O/Z) (5)EQEP1B Enhanced QEP1 input A (I)67 E7SPISOMIC SPI-C master in, slave out (not available on 2801/9501, 2802) (I/O)CANRXB Enhanced CAN-B receive (not available on 2801/9501, 2802, F2806) (I)

GPIO22 General purpose input/output 22 (I/O/Z) (5)EQEP1S Enhanced QEP1 strobe (I/O)71 D8SPICLKC SPI-C clock (not available on 2801/9501, 2802) (I/O)SCITXDB SCI-B transmit (not available on 2801/9501, 2802) (O)

GPIO23 General purpose input/output 23 (I/O/Z) (5)EQEP1I Enhanced QEP1 index (I/O)72 C10SPISTEC SPI-C slave transmit enable (not available on 2801/9501, 2802) (I/O)SCIRXDB SCI-B receive (I) (not available on 2801/9501, 2802)

GPIO24 General purpose input/output 24 (I/O/Z) (5)ECAP1 Enhanced capture 1 (I/O)83 C7EQEP2A Enhanced QEP2 input A (I) (not available on 2801/9501, 2802)SPISIMOB SPI-B slave in, master out (I/O)

GPIO25 General purpose input/output 25 (I/O/Z) (5)ECAP2 Enhanced capture 2 (I/O)91 C5EQEP2B Enhanced QEP2 input B (I) (not available on 2801/9501, 2802)SPISOMIB SPI-B master in, slave out (I/O)

GPIO26 General purpose input/output 26 (I/O/Z) (5)ECAP3 Enhanced capture 3 (I/O) (not available on 2801/9501, 2802)99 A2EQEP2I Enhanced QEP2 index (I/O) (not available on 2801/9501, 2802)SPICLKB SPI-B clock (I/O)

GPIO27 General purpose input/output 27 (I/O/Z) (5)ECAP4 Enhanced capture 4 (I/O) (not available on 2801/9501, 2802)79 C8EQEP2S Enhanced QEP2 strobe (I/O) (not available on 2801, 2802)SPISTEB SPI-B slave transmit enable (I/O)

GPIO28 General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)SCIRXDA SCI receive data (I)92 D5- -TZ5 Trip zone input 5 (I)

GPIO29 General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)SCITXDA SCI transmit data (O)4 C3- -TZ6 Trip zone 6 input (I)

GPIO30 General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)CANRXA Enhanced CAN-A receive data (I)6 D2- -- -

GPIO31 General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)CANTXA Enhanced CAN-A transmit data (O)7 D1- -- -

GPIO32 General purpose input/output 32 (I/O/Z) (5)SDAA I2C data open-drain bidirectional port (I/OD)100 A1EPWMSYNCI Enhanced PWM external sync pulse input (I)ADCSOCAO ADC start-of-conversion (O)

Introduction 23

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PIN NO.


GPIO33 General-Purpose Input/Output 33 (I/O/Z) (1)SCLA I2C clock open-drain bidirectional port (I/OD)5 C1EPWMSYNCO Enhanced PWM external synch pulse output (O)ADCSOCBO ADC start-of-conversion (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z) (1)- -43 G7- -- -

(1) The pullups on GPIO12-GPIO34 are enabled upon reset.

NOTESome peripheral functions may not be available in TMS320F2801x devices. SeeTable 2-2 for details.

24 Introduction

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3 Functional Overview

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

INT[12:1]

Real-Time JTAG (TDI, TDO, TRST, TCK,

TMS, EMU0, EMU1)

C28x CPU(100 MHz)

NMI, INT13

Memory Bus

Boot ROM4 K �16

(1-wait state)

FLASH128K x 16 (F2809) 64K x 16 (F2808) 32K x 16 (F2806)32K x 16 (F2802) 16K x 16 (F2801)16K x 16 (9501)

16K x 16 (F2801x)

H0 SARAM (C) 8 K � 16(0-wait)

L1 SARAM (B)4 K � 16(0-wait)

L0 SARAM 4 K � 16(0-wait)

M0 SARAM 1 K � 16

M1 SARAM 1 K � 16

INT14

32-bit CPU TIMER 0

32-bit CPU TIMER 1

32-bit CPU TIMER 2

SYSCLKOUT

RS

CLKIN

12-Bit ADC

ADCSOCA/B

SOCA/B

16 Channels

12

6

32

XCLKOUTXRS

XCLKINX1X2

32

System Control

(Oscillator , PLL, Peripheral Clocking,Low Power Modes,

WatchDog)

ePWM1/2/3/4/5/6(12 PWM outputs,

6 trip zones,6 timers 16-bit)

eCAP1/2/3/4(4 timers 32-bit)

eQEP1/2

eCAN-A/B (32 mbox)

External InterruptControl

PIE(96 Interrupts) (A)

FIFO

FIFO

FIFO

SCI-A/B

SPI-A/B/C/D

I2C-A

4

8

4

2

16

4

GP

IO M

UX

GPIOs(35)

TINT0

TINT1

TINT2

7

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉOTP(D)1K � 16Peripheral Bus

ÍÍÍÍÍÍÍÍÍÍÍÍ Protected by the code-security module.ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉROM32K x 16 (C2802) 16K x 16 (C2801)



A. 43 of the possible 96 interrupts are used on the devices.

B. Not available in F2802, F2801/9501, C2802, and C2801.

C. Not available in F2806, F2802, F2801/9501, C2802, and C2801.

D. The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices.

Figure 3-1. Functional Block Diagram

Functional Overview 25

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3.1 Memory Maps

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

0x00 0000

Block StartAddress Data Space Prog Space

M0 SARAM (1 K � 16)

M1 SARAM (1 K � 16)

0x00 0400

Peripheral Frame 00x00 0800ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ0x00 0D00 Peripheral Frame 1

(protected)

0x00 6000

Peripheral Frame 2(protected)

0x00 7000

L0 SARAM (0-wait)(4 k � 16, Secure Zone, Dual Mapped)

0x00 8000


0x00 9000

H0 SARAM (0-wait)(8 k � 16, Dual Mapped)

0x00 A000

0x00 C000

OTP(1 k � 16, Secure Zone)

0x3D 7800

0x3D 7C00

FLASH(128 k � 16, Secure Zone)

0x3D 8000

0x3F 7FF8128-bit Password


0x3F 8000


0x3F 9000


0x3F A000

0x3F F000

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉBoot ROM (4 k � 16)Vectors (32 � 32)

(enabled if VMAP = 1, ENPIE = 0)

0x3F FFC0

Low

64K

[000

0 −

FF

FF

](2

4x/2

40x

equi

vale

nt d

ata

spac

e)H

igh

64K

[3F

0000

− 3

FF

FF

F]

(24x

/240

x eq

uiva

lent

pro

gram

spa

ce)ÉÉÉÉÉÉÉÉÉÉÉÉReserved

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉPIE Vector − RAM (256 x 16) (Enabled if ENPIE = 1)0x00 0E00

0x3F C000


A. Memory blocks are not to scale.

B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.User program cannot access these memory maps in program space.

C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.

D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 3-2. F2809 Memory Map


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ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

0x00 0000

Block StartAddress Data Space Prog Space

M0 SARAM (1 K � 16)

M1 SARAM (1 K � 16)

0x00 0400

Peripheral Frame 00x00 0800ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ0x00 0D00 Peripheral Frame 1

(protected)

0x00 6000

Peripheral Frame 2(protected)

0x00 7000


0x00 8000


0x00 9000


0x00 A000

0x00 C000

OTP(1 k � 16, Secure Zone)

0x3D 7800

0x3D 7C00

FLASH(64 k � 16, Secure Zone)

0x3E 8000

0x3F 7FF8128-bit Password


0x3F 8000


0x3F 9000


0x3F A000

0x3F F000

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉBoot ROM (4 k � 16)Vectors (32 � 32)

(enabled if VMAP = 1, ENPIE = 0)

0x3F FFC0

Low

64K

[000

0 −

FF

FF

](2

4x/2

40x

equi

vale

nt d

ata

spac

e)H

igh

64K

[3F

0000

− 3

FF

FF

F]

(24x

/240

x eq

uiva

lent

pro

gram

spa

ce)ÉÉÉÉÉÉÉÉÉÉÉÉReserved

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉPIE Vector − RAM (256 x 16) (Enabled if ENPIE = 1)0x00 0E00

0x3F C000








Functional Overview 27

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ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

0x00 0000

Block StartAddress

Data Space

M0 SARAM (1K � 16)

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F 9000

0x3F A000

0x3F F000

0x3F FFC0

OTP(1 K � 16, Secure Zone)

FLASH(32 K � 16, Secure Zone)ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

Boot ROM (4 K � 16)

Low

64K

[000

0−F

FF

F]

(24x

/240

x eq

uiva

lent

dat

a sp

ace)

Hig

h 64

K [

3F00

00 −

3FF

FF

](2

4x/2

40x

equi

vale

nt p

rogr

am s

pace

)ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉReserved

M1 SARAM (1K � 16)

L0 SARAM (0-wait) (4k � 16, Secure Zone, Dual Mapped)

L1 SARAM (0-wait) (4k � 16, Secure Zone, Dual Mapped)

L0 SARAM (0-wait) (4k � 16,Secure Zone, Dual Mapped)

L1 SARAM (0-wait) (4k � 16,Secure Zone, Dual Mapped)

128-bit Password

0x3F 0000

Prog Space

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉPeripheral Frame 0ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉPeripheral Frame 1(protected)Peripheral Frame 2(protected)ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉPIE Vector − RAM (256 x 16) (Enabled if ENPIE = 1)

Vectors (32 � 32)(enabled if VMAP = 1, ENPIE = 0)

0x00 0E00








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0x00 0000

Block StartAddress

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x3D 7800

0x3F 000

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