Title REV: TABLE OF CONTENTS Date...WCN_SW _CTRL [77] S DCARD ET_N [45] USB_P HY_PS [19] WMSS_RES ET...

ITS CONTENTS REVEALED IN ANY MANNER TO OTHERS WITHOUT THE EXPRESS WRITTENNOT TO BE USED, COPIED, REPRODUCED, OR MODIFIED IN WHOLE OR IN PART, NOR

PERMISSION OF QUALCOMM TECHNOLOGIES, INC.THIS TECHNICAL DATA MAY BE SUBJECT TO U.S. AND INTERNATIONAL EXPORT,

CONFIDENTIAL AND PROPRIETARY - QUALCOMM TECHNOLOGIES, INC.

RE-EXPORT, OR TRANSFER ("EXPORT") LAWS. DIVERSION CONTRARY TO U.S. ANDINTERNATIONAL LAW IS STRICTLY PROHIBITED.

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

TABLE_OF_CONTENTS

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION

6 47 58 3 2 1LAST EDIT DATE

BLOCKSHEET

17

32

SCHEMATICSHEET

8

13

44

46

26

49

4

SHEET

11

34

41

38

22

SCHEMATICTITLE

10

18

23

25

6

2728293031

35

BLOCK BLOCK

12

15

2

19

SCHEMATIC

16

TABLE_OF_CONTENTS

24

33

37

21

1BLOCK

9

SCHEMATIC

7

SHEET

3

5

14

20

36

3940

4243

45

4748

50

GPIO TABLE

SM6150 CONTROLBLOCK DIAGRAM

DRX_Reserved_3

WCN3950_SH

SM6150 MIPI-CSI/DSI

SM6150 PWR_1

SM6150 PWR_3

DRX_Reserved_1

52

55

WCS_NFC_SN100U

53

6061

63

QPA8687

57

DRX_QDM2302

QAT3522QAT3518_DRX_ANT1

51

54

DRX_Reserved_4

56

62

SHEILDING_FRAME64

WLAN_RF_SH

59

Reserved_7

65

DRX_Reserved_2

58

SM6150 GPIOSM6150 LP GPIOSM6150 EBI0/1

SM6150 WCSS/RF

SM6150 PWR_2

SM6150 DECAPSSM6125 GNDReserved_1PM6125 HK/IOPM6125_Bucks_S1-S4PM6125_Bucks_S5-S8PM6125_LDOs

PMI632_ControlDECAPS

eMCP/uMCP

PMI632_LCD/VIB/RGB/Flash

REAR CAMERACAM eLDO

FRONT CAMERA

RCM/DEBUG

SDR480_PRX_DRX_FBRX

Reserved_4

Reserved_6

SDR480_POWER

PMI632_Charger/PD PHY

WCD9370

SMB1355

eMCP_POWER

Sensors

DISPLAY

SIM/SDKEYPAD/INDICATORBATT/B2BAudio over Type C

SDR480_GND

AUDIO

QPA8673QET4101

Reserved_5PRx_HBPRx_MBPRx_LB

PM8008 CAM_LDO

CHANGE LIST

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1 53

V10Page Name = 01_TABLE_OF_CONTENTS

Page Modify Date = Wednesday, May 15, 2019

DESIGNER = zhanglieqiang

Design Name = S88512AA1_1_21_20190515_1605

Title

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LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 CONTROL

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


UFS_REXT: DNI on Internal test chip, 100 OHM on SM6125Can float if UFS is not used

USB0_HS_REXT: 6.04K on Internal test chip, 4.02K on SM6125R34 can connect to GND if USB0 is not used

USB0_SS_REXT: 0OHM on Internal test chip, 100OHM on SM6125T34 can float if DP/USB0 is not used

Place near to the SDM about 1cm and put ino the shielding

SLEEP_CLK[16,77]

LN_BB_CLK1[16]

JTAG_SRST_N[47]

JTAG_TCK[47]

JTAG_TDI[47]

JTAG_TRST_N[47]

JTAG_TMS[47]

PS_HOLD[16]

JTAG_TDO[47]

PON_RESET_N[16,17]

SDC2_DATA_0 [45]

SDC2_DATA_1 [45]

SDC2_DATA_2 [45]

SDC2_DATA_3 [45]

USB0_HS_DM [19,47,48]

USB0_HS_DP [19,47,48]

PMIC_SPMI_DATA [16,17]

PMIC_SPMI_CLK [16,17]

SDC2_CLK [45]

SDC2_CMD [45]

QUIET_THERM [16]

UFS_RESET[11]

UFS_REF_CLK[11]

UFS_RX_M[11]

UFS_RX_P[11]

UFS_TX_M[11]

UFS_TX_P[11]

Title

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2 53

V10Page Name = 02_SM6125 CONTROL



Design Name = S88512AA1_1_21_20190515_1605

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2 53




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Title

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Design Name = S88512AA1_1_21_20190515_1605

R0211 22;5%;0201

R0215

0;0.5A;0201

NTC0201100K;1%;0201

12

R0225

0;0.5A;0201

R0205

0;0.5A;0201

R0208 NF_100;5%;0201

R0206

0;0.5A;0201

C02030.047uF;20%;6.3V;0201

R0213 4.02K;1%;0201

C0202

NF_33pf;30%;50V;0201

MFG_NO

U0501A

CONTROL

CXOAB34

SLEEP_CLKAF24

RESIN_NAH19

RESOUT_NAE23

MODE_0AG29

MODE_1AF29

PS_HOLDAG21

SRST_NAC32

TCKAC33

TDIAA32

TDOAD33

TMSAB32

TRST_NAD34

UFS_RESET_NB30

UFS_REFCLKA30

UFS_L0_RX_MD17

UFS_L0_RX_PE17

UFS_L0_TX_MD16

UFS_L0_TX_PE16

UFS_REXTB16

QPHY_TPAAE13

PLL_TEST_SEAH27

ATEST0AJ30

ATEST1AE29

SDC1_RCLKC32

SDC1_CLKD32

SDC1_CMDD31

SDC1_DATA_0C34

SDC1_DATA_1B33

SDC1_DATA_2D33

SDC1_DATA_3D34

SDC1_DATA_4C33

SDC1_DATA_5B34

SDC1_DATA_6A33

SDC1_DATA_7C31

SDC2_CLKAH21

SDC2_CMDAJ22

SDC2_DATA_0AH22

SDC2_DATA_1AH23

SDC2_DATA_2AJ24

SDC2_DATA_3AH24

USB0_DP_AUX_MW33

USB0_DP_AUX_PW34

USB0_HS_DMP33

USB0_HS_DPP34

USB0_HS_REXTR34

USB0_SS_REXTT34

USB0_SS_RX0_MV33

USB0_SS_RX0_PV34

USB0_SS_TX0_MT32

USB0_SS_TX0_PT31

USB0_SS_RX1_MU33

USB0_SS_RX1_PU34

USB0_SS_TX1_MR32

USB0_SS_TX1_PR31

USB0_SS_TPAP32

PMIC_SPMI_CLKAH18

PMIC_SPMI_DATAAJ19

TP02031

R0210

100;5%;0201

C0201

NF_33pf;30%;50V;0201

TP02041

SDC2_CLK_R

USB0_SS_REXT

USB0_HS_REXT

SDM_RESIN_N_R

UFS_REXT





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 GPIO

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


BOOT_CONFIG [2]

BOOT_CONFIG[3]

BOOT_CONFIG[0]

BOOT_CONFIG [10]

Force USB boot pol sel

BOOT_CONFIG [11]

BOOT_CONFIG [8]

BOOT_CONFIG [9]

BOOT_CONFIG [7]

I2C BUS PULL-UPs

BOOT_CONFIG [15]

BOARD_ID

D_GND D_GND D_GND

WCN_UART_RX_N[77]

DBG_UART_RX[47]

TS_I2C_SCL[3,40]

WCN_UART_TX_N[77]

DBG_UART_TX[47]

VCI_3P0_EN [40]

CAM_AFVDD_EN [21]

SNS_I3C_SCL[3,44]

SNS_I2C_SCL[3,44,61]

FP_SPI_MISO[48]

FP_SPI_SCLK[48]

CAM_MCLK0[41]

CAM_MCLK1[41]

CCI_I2C_SCL0[3,41]

CCI_I2C_SCL1[3,41]

CAM0_AVDD_EN[21]

CAM2_RST_N[41]

CAM1_RST_N[41]

CAM0_RST_N[41]

QLINK_ENABLE[58]

RFFE1_CLK[58]

RFFE2_CLK[62,67,70,75]

CAM_MCLK2[41]

TS_I2C_SDA[3,40]

WCN_UART_CTS_N[77]

WCN_UART_RFR_N[77]

SNS_I3C_SDA[3,44]

SNS_I2C_SDA[3,44,61]

FP_SPI_MOSI[48]

FP_SPI_CS_N[48]

CCI_I2C_SDA0[3,41]

CCI_I2C_SDA1[3,41]

RFFE1_DATA[58]

RFFE2_DATA[62,67,70,75]

QLINK_REQUEST[58]

UIM2_PRESENT [45]

UIM2_DATA [45]

UIM2_CLK [45]

UIM2_RESET [45]

UIM1_CLK [45]

UIM1_RESET [45]

UIM1_DATA [45]

UIM1_PRESENT [45]

ACCEL_INT [44]

GYRO_INT [44]

IR_LED_EN [21]

TS_RESET_N [40]

TS_INT_N [40]

MDP_VSYNC_P [40]

ALSP_INT_N [44]

FP_INT_N [48]

FORCED_USB_BOOT [47]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

MSS_LTE_COXM_RXD [77]

WCN_SW_CTRL [77]

SD_CARD_DET_N [45]

USB_PHY_PS [19]

WMSS_RESET [58]

SWR_TX_DATA0 [20]

SWR_TX_DATA1 [20]

SWR_RX_DATA0 [20]

SWR_RX_DATA1 [20]

QCA_SB_DATA [77]

AUDIO_PA_RST [37]

LCD_RESET_N [40]

FP_RST_N [48]

SWR_TX_CLK [20]

MSS_LTE_COXM_TXD [77]

SWR_RX_CLK [20]

WCD_RESET_N [20]

QCA_SB_CLK [77]

SNS_I2C_SCL[3,44,61]

CCI_I2C_SCL1[3,41] CCI_I2C_SCL0[3,41]

TS_I2C_SCL[3,40]

TS_I2C_SDA[3,40]

SNS_I2C_SDA[3,44,61]

CCI_I2C_SDA0[3,41]CCI_I2C_SDA1[3,41]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77] VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

VREG_L12A_1P8 [3,15,41] VREG_L12A_1P8 [3,15,41]

I2S1_SCK [37]

I2S1_WS [37]

I2S1_DATA0 [37]

I2S1_DATA1 [37]

INT_SMARTPA [37]

FP_LDO_EN [43]

CAM3_RST_N[41]

CAM0_DVDD_EN[21]

CAM1_2_DVDD_EN[21]

SAR_INT_GRFC0 [61]

GRFC9

GRFC1

GRFC2

GRFC3[67]

GRFC4[69]

GRFC5[69]

GRFC8

GRFC10[48]

GRFC11 [48]

GRFC_ANT_DET [61]

TP_LDO_EN [40]

CAM0_AVDD_EN2[21]

CAM_MCLK3[41]

BOARD_ID1[3]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

BOARD_ID1[3]BOARD_ID2[16]BOARD_ID3[16]

CAM_SW_EN [41]

FCAM_SEL [41]

LCD_ID[40]

CAM1_2_3_AVDD_EN[21]

GRFC13 [48]

IRTX_OUT[42]

SPK_SDA[3,37]

SPK_SCL[3,37]

SPK_SDA[3,37]

SPK_SCL[3,37]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

SNS_I3C_SDA[3,44]

SNS_I3C_SCL[3,44]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

VDDI_1P8_EN[40]

Title

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V10Page Name = 03_SM6125 GPIO



Design Name = S88512AA1_1_21_20190515_1605

Title

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Design Name = S88512AA1_1_21_20190515_1605

Title

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Design Name = S88512AA1_1_21_20190515_1605

R03072.2K;5%;0201

R0314

0;0.5A;0201

R0325

0;0.5A;0201

C0302

33pf;30%;50V;0201

R03102.2K;5%;0201

R034368K;5%;0201

R03492.2K;5%;0201

R03012.2K;5%;0201

R0342200K;1%;0201

R03462.2K;5%;0201

C030333pf;30%;50V;0201

R0313

0;0.5A;0201

R03082.2K;5%;0201

R03451K;5%;0201

R03022.2K;5%;0201

R0344NF_1K;5%;0201

R03472.2K;5%;0201

R03092.2K;5%;0201

MFG_NO

U0501B

GPIO

GPIO_0L33

GPIO_1L34

GPIO_2L32

GPIO_3L31

GPIO_4AG34

GPIO_5AD32

GPIO_6N34

GPIO_7M33

GPIO_8N33

GPIO_9M31

GPIO_10L4

GPIO_11K1

GPIO_12K2

GPIO_13L5

GPIO_14AF34

GPIO_15AE33

GPIO_16AF33

GPIO_17AE32

GPIO_18AH1

GPIO_19AG1

GPIO_20AF2

GPIO_21AF1

GPIO_22AH34

GPIO_23AG33

GPIO_24AF32

GPIO_25AH33

GPIO_26AJ33

GPIO_27AG32

GPIO_28AE31

GPIO_29AC31

GPIO_30AB31

GPIO_31AB30

GPIO_32AC30

GPIO_33AD30

GPIO_34AH5

GPIO_35AG6

GPIO_36AD7

GPIO_37AE7

GPIO_38AE6

GPIO_39AF6

GPIO_40AG5

GPIO_41AH4

GPIO_42AJ3

GPIO_43AH3

GPIO_44AH8

GPIO_45AG8

GPIO_46AH7

GPIO_47AE8

GPIO_48AD8

GPIO_49AG7

GPIO_50AG20

GPIO_51AE19

GPIO_52AG26

GPIO_53AF21

GPIO_54AG22

GPIO_55AJ27

GPIO_56AE20

GPIO_57AH26

GPIO_58AH25

GPIO_59AJ25

GPIO_60AF16

GPIO_61AG17

GPIO_62AE15

GPIO_63AD15

GPIO_64AJ18

GPIO_65AH17

GPIO_66AG16

GPIO_67AG15

GPIO_68AH16

GPIO_69AJ16

GPIO_70AH15

GPIO_71AJ15

GPIO_72AJ21

GPIO_74AH20

GPIO_75AE18

GPIO_76AF18

GPIO_77AE17

GPIO_78AG18

GPIO_79AE16

GPIO_80AH29

GPIO_81AG28

GPIO_82AH28

GPIO_83AE22

GPIO_84AE21

GPIO_85AJ28

GPIO_86AG27

GPIO_87AH32

GPIO_88AG31

GPIO_89AH31

GPIO_90AJ31

GPIO_91AG30

GPIO_92AF30

GPIO_93AH30

GPIO_94AJ9

GPIO_95AE9

GPIO_96AJ8

GPIO_97AH9

GPIO_98AF19

GPIO_99AF25

GPIO_100AF27

GPIO_101AF28

GPIO_103AG9

GPIO_104L2

GPIO_105L3

GPIO_106N3

GPIO_107N4

GPIO_108N5

GPIO_109M1

GPIO_110M2

GPIO_111L1

GPIO_112M5

GPIO_113AF3

GPIO_114AJ2

GPIO_115AH2

GPIO_116AG2

GPIO_117AH6

GPIO_118AJ6

GPIO_119AJ5

GPIO_120AF7

GPIO_121P5

GPIO_122P4

GPIO_123N1

GPIO_124N2

GPIO_125AG4

GPIO_126AF5

GPIO_127AG3

GPIO_128AE4

GPIO_129AF22

GPIO_130AG23

GPIO_131AG24

GPIO_132AG25

GPIO_102AF9

GPIO_73AG19

R03122.2K;5%;0201

R0350

10K;5%;0201

C030133pf;30%;50V;0201

R03411K;5%;0201

R0340NF_1K;5%;0201

R03482.2K;5%;0201

R0328

0;0.5A;0201

R0324

NF_2.2K;5%;0201

R03112.2K;5%;0201





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 EBI0/1

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


EBI0_CA_CS_0[11]

EBI0_CA_CS_1[11]

EBI0_CA_CK_C[11]

EBI0_CA_CK_T[11]

EBI0_CA_CKE_0[11]

EBI0_CA_CKE_1[11]

EBI0_DMI_0[11]

EBI0_DMI_1[11]

EBI0_DQS_C_0[11]

EBI0_DQS_T_0[11]

EBI0_DQS_C_1[11]

EBI0_DQS_T_1[11]

EBI0_CA_CA_0[11]

EBI0_CA_CA_1[11]

EBI0_CA_CA_2[11]

EBI0_CA_CA_3[11]

EBI0_CA_CA_4[11]

EBI0_CA_CA_5[11]

EBI1_CA_CS_0[11]

EBI1_CA_CS_1[11]

EBI1_CA_CK_C[11]

EBI1_CA_CK_T[11]

EBI1_CA_CKE_0[11]

EBI1_CA_CKE_1[11]

EBI1_CA_CA_0[11]

EBI1_CA_CA_1[11]

EBI1_CA_CA_2[11]

EBI1_CA_CA_3[11]

EBI1_CA_CA_4[11]

EBI1_CA_CA_5[11]

EBI1_DMI_0[11]

EBI1_DMI_1[11]

EBI1_DQS_C_0[11]

EBI1_DQS_T_0[11]

EBI1_DQS_C_1[11]

EBI1_DQS_T_1[11]

EBI0_DQ_0 [11]

DDR_RESET_N [11]

VREG_L6A_0P6 [9,11,12,15]

EBI0_DQ_1 [11]

EBI0_DQ_2 [11]

EBI0_DQ_3 [11]

EBI0_DQ_4 [11]

EBI0_DQ_5 [11]

EBI0_DQ_6 [11]

EBI0_DQ_7 [11]

EBI0_DQ_8 [11]

EBI0_DQ_9 [11]

EBI0_DQ_10 [11]

EBI0_DQ_11 [11]

EBI0_DQ_12 [11]

EBI0_DQ_13 [11]

EBI0_DQ_14 [11]

EBI0_DQ_15 [11]

EBI1_DQ_0 [11]

EBI1_DQ_1 [11]

EBI1_DQ_2 [11]

EBI1_DQ_3 [11]

EBI1_DQ_4 [11]

EBI1_DQ_5 [11]

EBI1_DQ_6 [11]

EBI1_DQ_7 [11]

EBI1_DQ_8 [11]

EBI1_DQ_9 [11]

EBI1_DQ_10 [11]

EBI1_DQ_11 [11]

EBI1_DQ_12 [11]

EBI1_DQ_13 [11]

EBI1_DQ_14 [11]

EBI1_DQ_15 [11]

Title

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V10Page Name = 04_SM6125 EBI0_1



Design Name = S88512AA1_1_21_20190515_1605

Title

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DESIGNER:

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Design Name = S88512AA1_1_21_20190515_1605

Title

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DESIGNER:

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Design Name = S88512AA1_1_21_20190515_1605

R0401

240;1%;0201

MFG_NO

U0501C

EBI0

EBI0_LP4X_CS0_LP3_CA0D8

EBI0_LP4X_CS1_LP3_CA2D9

EBI0_LP4X_CLK_CE11

EBI0_LP4X_CLK_TD11

EBI0_LP4X_CKE0_LP3_CKE0E9

EBI0_LP4X_CKE1E10

EBI0_LP4X_DMI0_LP3_DQ21D6

EBI0_LP4X_DMI1_LP3_DQ2A12

EBI0_LP4X_DQS0_C_LP3_DQS2_CD7

EBI0_LP4X_DQS0_T_LP3_DQS2_TE7

EBI0_LP4X_DQS1_C_LP3_DQS0_CE13

EBI0_LP4X_DQS1_T_LP3_DQS0_TD13

EBI0_LP4X_CA0_LP3_CS0D10

EBI0_LP4X_CA1_LP3_CS1B11

EBI0_LP4X_CA2A9

EBI0_LP4X_CA3_LP3_CA3B9

EBI0_LP4X_CA4_LP3_CA4B10

EBI0_LP4X_CA5_LP3_CA1E8

EBI0_CALF15

EBI0_LP4X_DQ0_LP3_DQ20A6

EBI0_LP4X_DQ1_LP3_DQ19B6


EBI0_LP4X_DQ3_LP3_DMI2A8

EBI0_LP4X_DQ4_LP3_DQ18E5



EBI0_LP4X_DQ7_LP3_DQ17D5


EBI0_LP4X_DQ9_LP3_DMI0D14







MFG_NO

U0501D

EBI1

EBI1_LP4X_CS0_LP3_CA7E25

EBI1_LP4X_CS1_LP3_CA6E24

EBI1_LP4X_CLK_C_LP3_CLK_CD22

EBI1_LP4X_CLK_T_LP3_CLK_TE22

EBI1_LP4X_CKE0D24

EBI1_LP4X_CKE1_LP3_CKE1D23

EBI1_LP4X_DMI0_LP3_DQ26E27

EBI1_LP4X_DMI1_LP3_DQ14A20

EBI1_LP4X_DQS0_C_LP3_DQS3_CE26

EBI1_LP4X_DQS0_T_LP3_DQS3_TD26

EBI1_LP4X_DQS1_C_LP3_DQS1_CD20

EBI1_LP4X_DQS1_T_LP3_DQS1_TE20

EBI1_LP4X_CA0_LP3_CA5E23

EBI1_LP4X_CA1B21

EBI1_LP4X_CA2_LP3_CA8A23

EBI1_LP4X_CA3B23

EBI1_LP4X_CA4B22

EBI1_LP4X_CA5_LP3_CA9D25

EBI1_TESTF18

DDR_RESET_NB29




EBI1_LP4X_DQ3_LP3_DMI3A24






EBI1_LP4X_DQ9_LP3_DMI1E19











LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 MIPI-CSI/DSI

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


FRONT/WIDE CAMERA

MIPI_DSI0_REXT_PLL: DNI on Internal test chip, 1.4K on SM6150Rear CAMERA

Depth

compatible MIPI interface camera

MIPI_DSI0_CLK_M [40]

MIPI_DSI0_CLK_P [40]

MIPI_DSI0_L0_M [40]

MIPI_DSI0_L0_P [40]

MIPI_DSI0_L1_M [40]

MIPI_DSI0_L1_P [40]

MIPI_DSI0_L2_M [40]

MIPI_DSI0_L2_P [40]

MIPI_DSI0_L3_M [40]

MIPI_DSI0_L3_P [40]

MIPI_CSI1_CLK_P[41]

MIPI_CSI1_CLK_M[41]

MIPI_CSI1_L0_P[41]

MIPI_CSI1_L0_M[41]

MIPI_CSI2_L3_M[41]

MIPI_CSI2_L3_P[41]

MIPI_CSI2_L2_M[41]

MIPI_CSI2_L2_P[41]

MIPI_CSI2_L1_M[41]

MIPI_CSI2_L1_P[41]

MIPI_CSI2_L0_M[41]

MIPI_CSI2_L0_P[41]

MIPI_CSI2_CLK_P[41]

MIPI_CSI2_CLK_M[41]

MIPI_CSI0_CLK_P[41]

MIPI_CSI0_CLK_M[41]

MIPI_CSI0_L0_P[41]

MIPI_CSI0_L0_M[41]

MIPI_CSI1_L1_P[41]

MIPI_CSI1_L1_M[41]

MIPI_CSI1_L2_P[41]

MIPI_CSI1_L2_M[41]

MIPI_CSI1_L3_P[41]

MIPI_CSI1_L3_M[41]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

5 53

V10Page Name = 05_SM6125 MIPI-CSI_DSI



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

5 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

5 53




Design Name = S88512AA1_1_21_20190515_1605

MFG_NO

U0501E

MIPI

CSI0_NC_CLK_PR4

CSI0_A0_CLK_MR3

CSI0_B0_LN0_PR2

CSI0_C0_LN0_MR1

CSI0_A1_LN1_PT4

CSI0_B1_LN1_MT3

CSI0_C1_LN2_PU4

CSI0_A2_LN2_MU3

CSI0_B2_LN3_PU2

CSI0_C2_LN3_MU1

CSI1_NC_CLK_PV1

CSI1_A0_CLK_MV2

CSI1_B0_LN0_PV3

CSI1_C0_LN0_MV4

CSI1_A1_LN1_PW3

CSI1_B1_LN1_MW4

CSI1_C1_LN2_PY1

CSI1_A2_LN2_MY2

CSI1_B2_LN3_PY3

CSI1_C2_LN3_MY4

CSI2_NC_CLK_PAA3

CSI2_A0_CLK_MAA4

CSI2_B0_LN0_PAB1

CSI2_C0_LN0_MAB2

CSI2_A1_LN1_PAB3

CSI2_B1_LN1_MAB4

CSI2_C1_LN2_PAC3

CSI2_A2_LN2_MAC4

CSI2_B2_LN3_PAD1

CSI2_C2_LN3_MAD2

DSI0_CLK_MF33

DSI0_CLK_PF34

DSI0_LN0_MG33

DSI0_LN0_PG34

DSI0_LN1_MJ33

DSI0_LN1_PJ34

DSI0_LN2_MG31

DSI0_LN2_PG32

DSI0_LN3_MH32

DSI0_LN3_PH31

DSI0_REXT_PLLK34

DSI1_CLK_MJ31

DSI1_CLK_PJ32

R0502

1.4K;1%;0201





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 WCSS/RF

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Add C1001-C1008 caps place holder for CLK desense to improve sensitivity.

WL_Rx_BB_I_N[77]

WL_Rx_BB_I_P[77]

WL_Rx_BB_Q_N[77]

WL_Rx_BB_Q_P[77]

WL_Tx_BB_I_N[77]

WL_Tx_BB_I_P[77]

WL_Tx_BB_Q_N[77]

WL_Tx_BB_Q_P[77]

WLAN_BT_COEX_DATA[77]

WL_CMD_DATA[77]

WLAN_BT_COEX_CLK[77]

WL_CMD_CLK[77]

WLAN_XO_CLK [16]

QPHY_CLK_M [58]

QPHY_CLK_P [58]

QPHY_DL0_M [58]

QPHY_DL0_P [58]

QPHY_DL1_M [58]

QPHY_DL1_P [58]

QPHY_DL2_M [58]

QPHY_DL2_P [58]

QPHY_UL0_M [58]

QPHY_UL0_P [58]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

6 53

V10Page Name = 06_SM6125 WCSS_RF



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

6 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

6 53




Design Name = S88512AA1_1_21_20190515_1605

C06072.7pF;0.25pF;50V;0201

C06052.7pF;0.25pF;50V;0201

C0601

2.7pF;0.25pF;50V;0201

MFG_NO

U0501F

WLAN_QLINK

WLAN_CXM_CLKH1

WLAN_CXM_DATAJ1

WLAN_BBD_CLKF1

WLAN_BBD_DATAG1

WLAN0_REXTG2

WLAN_RX_I_MB2

WLAN_RX_I_PA2

WLAN_RX_Q_MB1

WLAN_RX_Q_PC1

WLAN_TX_I_MJ4

WLAN_TX_I_PH4

WLAN_TX_Q_MH3

WLAN_TX_Q_PJ3

WLAN_XO_CLKE1

QREFS_CXO_REXTAA33

QLINK_CLK_MAF11

QLINK_CLK_PAG11

QLINK_DL0_MAH13

QLINK_DL0_PAJ13

QLINK_DL1_MAG12

QLINK_DL1_PAF12

QLINK_DL2_MAJ11

QLINK_DL2_PAH11

QLINK_UL0_MAG13

QLINK_UL0_PAF13

C06042.7pF;0.25pF;50V;0201

R0601

6.04K;1%;0201

C0602

2.7pF;0.25pF;50V;0201

R0602

3.01K;1%;0201

C06062.7pF;0.25pF;50V;0201

C06082.7pF;0.25pF;50V;0201

C0603

2.7pF;0.25pF;50V;0201





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 PWR_1

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


BULK CAPS

MX

VREG_S5A [9,14,15]

VREG_S1A_S2A[13]

VREF_MSM[8,16]

VREG_L10A_1P8[8,9,15,16]

VREG_S5A_SNS[14]

RMT_VREG_S1A_S2A_P[13]

RMT_VREG_S1A_S2A_M[13]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

7 53

V10Page Name = 07_SM6125 PWR_1



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

7 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

7 53




Design Name = S88512AA1_1_21_20190515_1605

JP0702

TOP;BOT

L91 2

C07172.2uF;20%;6.3V;0201

C07041.0UF;20%;6.3V;0201

21

C0709

1.0UF;20%;6.3V;0201

21

JP0701

TOP;BOT

L91 2

C07061.0UF;20%;6.3V;0201

21

C07162.2uF;20%;6.3V;0201

C07142.2uF;20%;6.3V;0201

C07301.0UF;20%;6.3V;0201

21

C072210uF;20%;6.3V;0402 C0723

10uF;20%;6.3V;0402

C07280.1uF;20%;6.3V;0201

C072410uF;20%;6.3V;0402

C07121.0UF;20%;6.3V;0201

21

JJP0703

TOP;BOT

L91 2

C07101.0UF;20%;6.3V;0201

21

C072610uF;20%;6.3V;0402

C07071.0UF;20%;6.3V;0201

21

C0727

0.1uF;20%;6.3V;0201

C0720NF_10uF;20%;6.3V;0402

C0711

1.0UF;20%;6.3V;0201

21

C07152.2uF;20%;6.3V;0201

C07020.1uF;20%;6.3V;0201

C072510uF;20%;6.3V;0402

C071910uF;20%;6.3V;0402

C072110uF;20%;6.3V;0402

C07132.2uF;20%;6.3V;0201

C07290.1uF;20%;6.3V;0201

C07081.0UF;20%;6.3V;0201

21

C07011.0UF;20%;6.3V;02012

1

C07051.0UF;20%;6.3V;0201

21 C0718

10uF;20%;6.3V;0402

C07032.2uF;20%;6.3V;0201

MFG_NO

U0501G

PWR1

VDDMX_1_1AA19

VDDMX_1_2AA20

VDDMX_1_3AA28

VDDMX_1_4AB28

VDDMX_1_5J12

VDDMX_1_6J26

VDDMX_1_7L11

VDDMX_1_8L12

VDDMX_1_9L13

VDDMX_1_10L15

VDDMX_1_11L16

VDDMX_1_12L17

VDDMX_1_13L19

VDDMX_1_14L20

VDDMX_1_15L21

VDDMX_1_16L22

VDDMX_1_17L23

VDDMX_1_18L24

VDDMX_1_19L26

VDDMX_1_20N9

VDDMX_1_21T24

VDDMX_1_22U11

VDDMX_1_23U12

VDDMX_1_24U13

VDDMX_1_25U14

VDDMX_1_26U15

VDDMX_1_27U16

VDDMX_1_28U17

VDDMX_1_29U18

VDDMX_1_30U19

VDD_QFPROML28

VDDPX_VBIAS_SDCAC18

VDD_APC0_1AA25

VDD_APC0_2AA26

VDD_APC0_3AB25

VDD_APC0_4AB26

VDD_APC0_5AC25

VDD_APC0_6AC26

VDD_APC0_7AD25

VDD_APC0_8AD26

VDD_APC0_9U24

VDD_APC0_10U26

VDD_APC0_11V25

VDD_APC0_12V26

VDD_APC0_13W20

VDD_APC0_14W21

VDD_APC0_15W22

VDD_APC0_16W25

VDD_APC0_17Y20

VDD_APC0_18Y21

VDD_APC0_19Y22

VDD_APC0_20Y23

VDD_APC0_21Y24

VDD_APC0_22Y25

VDDMX_1_31U20

VDDMX_1_32U22

VDDMX_1_33U23

VDDMX_1_34U28

VDDMX_1_35V10

VDDMX_1_36W28

VDDMX_1_37Y18

VDD_APC0_23Y26





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 PWR_2

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


WCSS CX

SDC2

G28 can float if UFS is not used

CXO

DDR

UIM1

eMMC

UFS

UIM2

BULK CAPS

MODEMMSM PX_3

VREG_S3A_S4A [13]

RTM_VREG_S3A_S4A_P[13]

RTM_VREG_S3A_S4A_M[13]

VIO_OUT[16,17]

VREG_S8A[11,12,14,15]

VREG_L5A_2P96[15,45]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

VREG_L19A_1P8[15,45]

VREG_L20A_1P8[15,45]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

VREG_L18A_1P232[9,15]

VREG_L10A_1P8[7,9,15,16]

VREF_MSM[7,16]

VREG_L8A_0P736[15]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

8 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

8 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

8 53




Design Name = S88512AA1_1_21_20190515_1605

JP0801

TOP;BOT

L91 2

C08320.1uF;20%;6.3V;0201

C08370.1uF;20%;6.3V;0201

C08010.1uF;20%;6.3V;0201

C08024.7uF;20%;6.3V;0402

C08111.0UF;20%;6.3V;02012

1

C0833

0.1uF;20%;6.3V;0201

C08051.0UF;20%;6.3V;02012

1

C0818

1.0UF;20%;6.3V;0201

21

C0830

10uF;20%;6.3V;0402

C0831

10uF;20%;6.3V;0402

C0826

10uF;20%;6.3V;0402

C08031.0UF;20%;6.3V;0201

21

C0816

1.0UF;20%;6.3V;0201

21 C0819

1.0UF;20%;6.3V;0201

21 C0838

1.0UF;20%;6.3V;0201

21

C0817

1.0UF;20%;6.3V;0201

21

C08340.1uF;20%;6.3V;0201

C08151.0UF;20%;6.3V;02012

1

C08241.0UF;20%;6.3V;02012

1

C0825

1.0UF;20%;6.3V;0201

21

C08121.0UF;20%;6.3V;02012

1

C08061.0UF;20%;6.3V;02012

1

C08231.0UF;20%;6.3V;02012

1

C08071.0UF;20%;6.3V;02012

1

C08201.0UF;20%;6.3V;02012

1

C08350.1uF;20%;6.3V;0201

C0808

1.0UF;20%;6.3V;0201

21

C0821

1.0UF;20%;6.3V;020121

JP0802

TOP;BOT

L91 2

C08391.0UF;20%;6.3V;0201

21

C0809

1.0UF;20%;6.3V;0201

21

C0822

1.0UF;20%;6.3V;0201

21

C082710uF;20%;6.3V;0402

C0810

1.0UF;20%;6.3V;0201

21

C0829

10uF;20%;6.3V;0402

C08131.0UF;20%;6.3V;02012

1

MFG_NO

U0501H

PWR2

VDDCX_1_1K13

VDDCX_1_2K14

VDDCX_1_3K15

VDDCX_1_4K16

VDDCX_1_5K17

VDDCX_1_6K18

VDDCX_1_7K19

VDDCX_1_8K20

VDDCX_1_9K24

VDDCX_1_10K25

VDDCX_1_11N10

VDDCX_1_12N12

VDDCX_1_13N14

VDDCX_1_14N16

VDDCX_1_15N18

VDDCX_1_16N20

VDDCX_1_17N22

VDDCX_1_18N24

VDDCX_1_19N26

VDDCX_1_20R8

VDDCX_1_21R10

VDDCX_1_22R11

VDDCX_1_23R12

VDDCX_1_24R13

VDDCX_1_25R14

VDDCX_1_26R15

VDDCX_1_27R16

VDDCX_1_28R17

VDDCX_1_29R18

VDDCX_1_30R19

VDDCX_1_31R20

VDDCX_1_32R21

VDDCX_1_33R22

VDDCX_1_34R23

VDDCX_1_35R24

VDDCX_1_36R25

VDDCX_1_37W8

VDDCX_1_38W10

VDDCX_1_39W12

VDDCX_1_40W14

VDDCX_1_41W16

VDDCX_1_42W17

VDDCX_1_43Y8

VDDCX_1_44Y10

VDDCX_1_45Y14

VDDPX_0AC14

VDDPX_1_AF11

VDDPX_1_BF14

VDDPX_2AC19

VDDPX_3_1AA6

VDDPX_3_2AC10

VDDPX_3_3AC29

VDDPX_3_4AD17

VDDPX_3_5AD20

VDDPX_3_6F29

VDDPX_3_7L30

VDDPX_3_8P6

VDDPX_3_9W30

VDDPX_5AC16

VDDPX_6AC17

VDDPX_7G29

VDDPX_10G28

VDDPX_11V30

VDD_WCSS_CX_1J10

VDD_WCSS_CX_2J11

VDDPX_1_CF19

VDDPX_1_DF22

VDDPX_1_EG26

VDDPX_VBIAS_UIMAB16

VDDPX_3_AF12

VDDPX_3_BF21

C0828

10uF;20%;6.3V;0402

C08041.0UF;20%;6.3V;02012

1

C08141.0UF;20%;6.3V;02012

1

C08360.1uF;20%;6.3V;0201





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 PWR_3

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


eMMC compatible UFS soltion

VREG_S5A [7,9,14,15]

VREG_L4A_0P928 [9,15]

VREG_L18A_1P232 [8,9,15]

VREG_S5A [7,9,14,15]

VREG_L10A_1P8 [7,8,9,15,16]

VREG_L16A_1P8 [15,77,79]

VREG_S5A [7,9,14,15]

VREG_L4A_0P928 [9,15]

VREG_L4A_0P928[9,15]

VREG_L10A_1P8[7,8,9,15,16]

VREG_L6A_0P6[4,9,11,12,15]

VREG_L7A_0P928[15]

VREG_L10A_1P8[7,8,9,15,16]

VREG_L15A_3P104[15]

VREG_L18A_1P232[8,9,15]

VREG_L17A_1P304[15,77]

VREG_L6A_0P6[4,9,11,12,15]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

9 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

9 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

9 53




Design Name = S88512AA1_1_21_20190515_1605

C0910

1.0UF;20%;6.3V;0201

21

C0924

1.0UF;20%;6.3V;0201

21

C09141.0UF;20%;6.3V;02012

1

C0916

1.0UF;20%;6.3V;020121

C0907

1.0UF;20%;6.3V;0201

21

C0927

1.0UF;20%;6.3V;0201

21

C09221.0UF;20%;6.3V;02012

1

C0901

1.0UF;20%;6.3V;0201

21

C09131.0UF;20%;6.3V;02012

1

C0918

1.0UF;20%;6.3V;0201

21

C09091.0UF;20%;6.3V;02012

1

C0926

1.0UF;20%;6.3V;0201

21

C0906

1.0UF;20%;6.3V;020121

C09041.0UF;20%;6.3V;02012

1

C0921

1.0UF;20%;6.3V;0201

21

C09292.2uF;20%;6.3V;0201C0930

2.2uF;20%;6.3V;0201

C09111.0UF;20%;6.3V;02012

1

C0932

1.0UF;20%;6.3V;0201

21

MFG_NO

U0501I

PWR3

VDDA_APC0_PLLV23

VDDA_EBI0_AH10

VDDA_EBI_PLLG16

VDDA_CSI0_1P2T8

VDDA_CSI1_1P2U8

VDDA_CSI2_1P2V8

VDDA_DSI_PLLK29

VDDA_DSI_1P2H28

VDDA_DSI_0P9J29

VDDA_QLINK_LVAB12

VDDA_QLINK_LV_CKAC12

VDDA_UFS_COREF17

VDDA_UFS_1P8G17

VDDIO_CK_EBI0F13

VDDIO_CK_EBI1F20

VDDA_USB_SS_DP_CORER28

VDDA_USB_SS_DP_1P8P30

VDDA_USB_HS_1P8N30

VDDA_USB_HS_3P1N29

VDDA_PLL_HV_CC_EBIF16

VDDA_WCSS_ADCDAC_1J8

VDDA_WCSS_ADCDAC_0K8

VDDIO_EBI_A1G10

VDDIO_EBI_B1G14

VDDIO_EBI_C1G18

VDDIO_EBI_D1G22

VDDA_EBI0_BH12

VDDA_EBI0_CH14

VDDA_EBI1_AH19

VDDA_EBI1_BH21

VDDA_EBI1_CH23

VDDIO_EBI_A2G11

VDDIO_EBI_B2G15

VDDIO_EBI_C2G19

VDDIO_EBI_D2G23

VDD_USB_HS_COREN28

VDDA_AUDIO_PLLL10

VDDA_CAMSS_PLLT17

VDDA_CC_EBIH16

VDDA_WCSS_PLLL7

VDDA_QREFS_0P9_4G25

VDDA_QREFS_0P9_5AD28

VDDA_QREFS_0P9_6AD22

VDDA_QREFS_0P9_7AB13

C09171.0UF;20%;6.3V;02012

1

C09081.0UF;20%;6.3V;02012

1

C0933

1.0UF;20%;6.3V;0201

21

C0925

1.0UF;20%;6.3V;0201

21

C0903

1.0UF;20%;6.3V;0201

21

C09231.0UF;20%;6.3V;0201

C09282.2uF;20%;6.3V;0201

C0905

1.0UF;20%;6.3V;0201

21

C0931

1.0UF;20%;6.3V;0201

21

C09201.0UF;20%;6.3V;02012

1

C09151.0UF;20%;6.3V;02012

1

C09121.0UF;20%;6.3V;02012

1

C091910uF;20%;6.3V;0402

C0902

1.0UF;20%;6.3V;020121





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SM6125 GND

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

10 53

V10Page Name = 10_SM6125 GND



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

10 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

10 53




Design Name = S88512AA1_1_21_20190515_1605

MFG_NO

U0501J

GND1

VSSX_0_1A5

VSSX_0_2A14

VSSX_0_3A15

VSSX_0_4A17

VSSX_0_5A18

VSSX_0_6A27

VSSX_0_7A29

VSSX_0_8A32

VSSX_0_9A34

VSSX_0_10AA1

VSSX_0_11AA2

VSSX_0_12AA5

VSSX_0_13AA7

VSSX_0_14AA8

VSSX_0_15AA21

VSSX_0_16AA22

VSSX_0_17AA24

VSSX_0_18AA27

VSSX_0_19AA29

VSSX_0_20AA30

VSSX_0_21AA31

VSSX_0_22AA34

VSSX_0_23AB5

VSSX_0_24AB7

VSSX_0_25AB9

VSSX_0_26AB11

VSSX_0_27AB14

VSSX_0_28AB23

VSSX_0_29AB24

VSSX_0_30AB29

VSSX_0_31AB33

VSSX_0_32AC1

VSSX_0_33AC2

VSSX_0_34AC5

VSSX_0_35AC6

VSSX_0_36AC7

VSSX_0_37AC8

VSSX_0_38AC9

VSSX_0_39AC11

VSSX_0_40AC13

VSSX_0_41AC21

VSSX_0_42AC22

VSSX_0_43AC23

VSSX_0_44AC24

VSSX_0_45AC27

VSSX_0_46AC28

VSSX_0_47AC34

VSSX_0_48AD3

VSSX_0_49AD4

VSSX_0_50AD5

VSSX_0_51AD9

VSSX_0_52AD11

VSSX_0_53AD13

VSSX_0_54AD16

VSSX_0_55AD19

VSSX_0_56AD23

VSSX_0_57AD24

VSSX_0_58AD27

VSSX_0_59AD29

VSSX_0_60AD31

VSSX_0_61AE1

VSSX_0_62AE2

VSSX_0_63AE3

VSSX_0_64AE5

VSSX_0_65AE10

VSSX_0_66AE11

VSSX_0_67AE12

VSSX_0_68AE14

VSSX_0_69AE24

VSSX_0_70AE25

VSSX_0_71AE26

VSSX_0_72AE27

VSSX_0_73AE28

VSSX_0_74AE30

VSSX_0_75AE34

VSSX_0_76AF4

VSSX_0_77AF8

VSSX_0_78AF10

VSSX_0_79AF14

VSSX_0_80AF15

VSSX_0_81AF17

VSSX_0_82AF20

VSSX_0_83AF23

VSSX_0_84AF26

VSSX_0_85AF31

VSSX_0_86AG10

VSSX_0_87AG14

VSSX_0_88AH10

VSSX_0_89AH12

VSSX_0_90AH14

VSSX_0_91AJ1

VSSX_0_92AJ4

VSSX_0_93AJ7

VSSX_0_94AJ10

VSSX_0_95AJ12

VSSX_0_96AJ14

VSSX_0_97AJ17

VSSX_0_98AJ20

VSSX_0_99AJ23

VSSX_0_100AJ26

MFG_NO

U0501L

GND2

VSSX_0_201M22

VSSX_0_202M24

VSSX_0_203M26

VSSX_0_204M29

VSSX_0_205M30

VSSX_0_206M32

VSSX_0_207M34

VSSX_0_208N6

VSSX_0_209N7

VSSX_0_210N31

VSSX_0_211N32

VSSX_0_212P1

VSSX_0_213P2

VSSX_0_214P3

VSSX_0_215P7

VSSX_0_216P11

VSSX_0_217P12

VSSX_0_218P13

VSSX_0_219P14

VSSX_0_220P15

VSSX_0_221P17

VSSX_0_222P18

VSSX_0_223P19

VSSX_0_224P20

VSSX_0_225P21

VSSX_0_226P23

VSSX_0_227P24

VSSX_0_228P25

VSSX_0_229P31

VSSX_0_230R5

VSSX_0_231R6

VSSX_0_232R7

VSSX_0_233R29

VSSX_0_234R30

VSSX_0_235R33

VSSX_0_236T1

VSSX_0_237T2

VSSX_0_238T7

VSSX_0_239T10

VSSX_0_240T11

VSSX_0_241T12

VSSX_0_242T13

VSSX_0_243T14

VSSX_0_244T15

VSSX_0_245T18

VSSX_0_246T20

VSSX_0_247T21

VSSX_0_248T22

VSSX_0_249T23

VSSX_0_250T25

VSSX_0_251T26

VSSX_0_252T29

VSSX_0_253T33

VSSX_0_254U5

VSSX_0_255U6

VSSX_0_256U7

VSSX_0_257U10

VSSX_0_258U21

VSSX_0_259U25

VSSX_0_260U30

VSSX_0_261U31

VSSX_0_262U32

VSSX_0_263V7

VSSX_0_264V12

VSSX_0_265V14

VSSX_0_266V16

VSSX_0_267V19

VSSX_0_268V20

VSSX_0_269V21

VSSX_0_270V24

VSSX_0_271V28

VSSX_0_272W1

VSSX_0_273W2

VSSX_0_274W5

VSSX_0_275W6

VSSX_0_276W7

VSSX_0_277W24

VSSX_0_278W26

VSSX_0_279W31

VSSX_0_280W32

VSSX_0_281Y7

VSSX_0_282Y11

VSSX_0_283Y15

VSSX_0_284Y16

VSSX_0_285Y17

VSSX_0_286Y19

VSSX_0_287Y28

VSSX_0_288Y32

VSSX_0_289Y33

VSSX_0_290Y34

MFG_NO

U0501K

GND2

VSSX_0_101AJ29

VSSX_0_102AJ32

VSSX_0_103AJ34

VSSX_0_104B5

VSSX_0_105B15

VSSX_0_106B17

VSSX_0_107B27

VSSX_0_108B28

VSSX_0_109B31

VSSX_0_110B32

VSSX_0_111C5

VSSX_0_112C6

VSSX_0_113C7

VSSX_0_114C8

VSSX_0_115C9

VSSX_0_116C10

VSSX_0_117C11

VSSX_0_118C12

VSSX_0_119C13

VSSX_0_120C14

VSSX_0_121C15

VSSX_0_122C16

VSSX_0_123C17

VSSX_0_124C18

VSSX_0_125C19

VSSX_0_126C20

VSSX_0_127C21

VSSX_0_128C22

VSSX_0_129C23

VSSA_WCSS_ADCDAC_0_1G3

VSSA_WCSS_ADCDAC_0_2G4

VSSA_WCSS_ADCDAC_0_3H5

VSSA_WCSS_ADCDAC_0_4J5

VSSA_WCSS_ADCDAC_0_5K4



VSSA_WCSS_ADCDAC_1_1A1

VSSA_WCSS_ADCDAC_1_2A3

VSSA_WCSS_ADCDAC_1_3B3

VSSA_WCSS_ADCDAC_1_4B4

VSSA_WCSS_ADCDAC_1_5C2



VSSA_WCSS_ADCDAC_1_8E3

VSSA_WCSS_ADCDAC_1_9E4

VSSA_WCSS_ADCDAC_1_10F4

VSSA_WCSS_ADCDAC_1_11F5



VSSGR_WCSS_ADC_1J7

VSSA_APC0_PLLV22

VSSX_0_130C24

VSSX_0_131C25

VSSX_0_132C26

VSSX_0_133C27

VSSX_0_134C28

VSSX_0_135C29

VSSX_0_136D1

VSSX_0_137D2

VSSX_0_138D15

VSSX_0_139D18

VSSX_0_140D29

VSSX_0_141D30

VSSX_0_142E2

VSSX_0_143E15

VSSX_0_144E18

VSSX_0_145E29

VSSX_0_146E30

VSSX_0_147E33

VSSX_0_148E34

VSSX_0_149F2

VSSX_0_150F3

VSSX_0_151F6

VSSX_0_152F7

VSSX_0_153F8

VSSX_0_154F9

VSSX_0_155F10

VSSX_0_156F23

VSSX_0_157F24

VSSX_0_158F25

VSSX_0_159F26

VSSX_0_160F27

VSSX_0_161F28

VSSX_0_162F31

VSSX_0_163F32

VSSX_0_164G7

VSSX_0_165G12

VSSX_0_166H2

VSSX_0_167H8

VSSX_0_168H30

VSSX_0_169H33

VSSX_0_170H34

VSSX_0_171J2

VSSX_0_172J13

VSSX_0_173J14

VSSX_0_174J15

VSSX_0_175J16

VSSX_0_176J18

VSSX_0_177J19

VSSX_0_178J20

VSSX_0_179J21

VSSX_0_180J22

VSSX_0_181J24

VSSX_0_182J25

VSSX_0_183J30

VSSX_0_184K3

VSSX_0_185K10

VSSX_0_186K11

VSSX_0_187K21

VSSX_0_188K22

VSSX_0_189K31

VSSX_0_190K32

VSSX_0_191K33

VSSX_0_192L6

VSSX_0_193L29

VSSX_0_194M4

VSSX_0_195M6

VSSX_0_196M12

VSSX_0_197M14

VSSX_0_198M16

VSSX_0_199M18

VSSX_0_200M20

VSSA_AUDIO_PLLM8

VSSA_CAMSS_PLLT16

VSSA_WCSS_PLLM7





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Pls near to the memory

eMCP and UFS compatible designVREG_L6A_0P6 [4,9,12,15]

EBI0_CA_CS_0[4]

EBI0_CA_CS_1[4]

EBI0_CA_CK_T[4]

EBI0_CA_CK_C[4]

EBI0_CA_CKE_0[4]

EBI0_CA_CKE_1[4]

VREG_S8A[8,11,12,14,15]

EBI0_CA_CA_0[4]

EBI0_CA_CA_1[4]

EBI0_CA_CA_2[4]

EBI0_CA_CA_3[4]

EBI0_CA_CA_4[4]

EBI0_CA_CA_5[4]

DDR_RESET_N[4]

EBI0_DQS_T_0[4]

EBI0_DQS_T_1[4]

EBI0_DQS_C_0[4]

EBI0_DQS_C_1[4]

EBI0_DMI_0[4]

EBI0_DMI_1[4]

EBI0_DQ_0 [4]

EBI0_DQ_1 [4]

EBI0_DQ_2 [4]

EBI0_DQ_3 [4]

EBI0_DQ_4 [4]

EBI0_DQ_5 [4]

EBI0_DQ_6 [4]

EBI0_DQ_7 [4]

EBI0_DQ_8 [4]

EBI0_DQ_9 [4]

EBI0_DQ_10 [4]

EBI0_DQ_11 [4]

EBI0_DQ_12 [4]

EBI0_DQ_13 [4]

EBI0_DQ_14 [4]

EBI0_DQ_15 [4]

EBI1_DQ_0 [4]

EBI1_DQ_1 [4]

EBI1_DQ_2 [4]

EBI1_DQ_3 [4]

EBI1_DQ_4 [4]

EBI1_DQ_5 [4]

EBI1_DQ_6 [4]

EBI1_DQ_7 [4]

EBI1_DQ_8 [4]

EBI1_DQ_9 [4]

EBI1_DQ_10 [4]

EBI1_DQ_11 [4]

EBI1_DQ_12 [4]

EBI1_DQ_13 [4]

EBI1_DQ_14 [4]

EBI1_DQ_15 [4]

EBI1_CA_CS_0[4]

EBI1_CA_CS_1[4]

EBI1_CA_CK_T[4]

EBI1_CA_CK_C[4]

EBI1_CA_CKE_0[4]

EBI1_CA_CKE_1[4]

VREG_S8A[8,11,12,14,15]

EBI1_CA_CA_0[4]

EBI1_CA_CA_1[4]

EBI1_CA_CA_2[4]

EBI1_CA_CA_3[4]

EBI1_CA_CA_4[4]

EBI1_CA_CA_5[4]

EBI1_DQS_T_0[4]

EBI1_DQS_T_1[4]

EBI1_DQS_C_0[4]

EBI1_DQS_C_1[4]

EBI1_DMI_1[4]

EBI1_DMI_0[4]

EMMC_UFS_THERM [16]

UFS_REF_CLK[2]

UFS_RESET[2]

UFS_RX_P[2]

UFS_TX_M[2]

UFS_RX_M[2]

UFS_TX_P[2]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

11 53

V10Page Name = 11_eMCP_uMCP



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

11 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

11 53




Design Name = S88512AA1_1_21_20190515_1605

R1105 0;0.5A;0201

R1103 240;1%;0201

U1101A

MFG_NO

LPDDR4_A

RST_N_2AA16

ZQ0B16

ZQ1C16

CS0_AE15

CS1_AF15

NC_7H14

CLK_T_AH16

CLK_C_AG16

CKE0_AE16

CKE1_AF16

NC_8J14

NC_11J13

DQS0_T_AC9

DQS1_T_AK9

DQS0_C_AD9

DQS1_C_AJ9

CA0_AG14

CA1_AF13

CA2_AC13

CA3_AD13

CA4_AE13

CA5_AC15

DMI0_AD5

DMI1_AH3

DQ0_AA3

DQ1_AB3

DQ2_AC3

DQ3_AD3

DQ4_AB7

DQ5_AC6

DQ6_AD7

DQ7_AC8

DQ8_AK5

DQ9_AK6

DQ10_AK3

DQ11_AJ3

DQ12_AJ7

DQ13_AG3

DQ14_AH6

DQ15_AH8

U1101C

MFG_NO

EMMC

RST_N_1N9

CMDM9

CLKMP12

DSM12

DAT0P16

DAT1M15

DAT2N13

DAT3P15

DAT4M16

DAT5N14

DAT6L14

DAT7L13

R1101 240;1%;0201

U1101B

MFG_NO

LPDDR4_B

CS0_BY15

CS1_BW15

NC_9U14

CLK_T_BU16

CLK_C_BV16

CKE0_BY16

CKE1_BW16

NC_10T14

NC_12T13

DQS0_T_BAB9

DQS1_T_BR9

DQS0_C_BAA9

DQS1_C_BT9

CA0_BV14

CA1_BW13

CA2_BAB13

CA3_BAA13

CA4_BY13

CA5_BAB15

DMI0_BAA5

DMI1_BU3

DQ0_BAD3

DQ1_BAC3

DQ2_BAB3

DQ3_BAA3

DQ4_BAC7

DQ5_BAB6

DQ6_BAA7

DQ7_BAB8

DQ8_BR5

DQ9_BR6

DQ10_BR3

DQ11_BT3

DQ12_BT7

DQ13_BV3

DQ14_BU6

DQ15_BU8

NTC1101100K;1%;0201

12

R1102

0;0.5A;0201





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

eMCP_POWER

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


VREG_L24A_2P96 [15]

VREG_L11A_1P8 [15]

VREG_L6A_0P6 [4,9,11,12,15]

VREG_L9A_1P8[3,8,15,16,17,20,37,44,45,47,60,61,62,75,77]

VREG_S8A[8,11,14,15]

RTM_VREG_S8A_P[14]

RTM_VREG_S8A_M[14]

VREG_L6A_0P6 [4,9,11,12,15]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

12 53

V10Page Name = 12_EMCP_POWER



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

12 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

12 53




Design Name = S88512AA1_1_21_20190515_1605

C12142.2uF;20%;6.3V;0201

C12060.1uF;20%;6.3V;0201

JP1202

TOP;BOT

L91 2

C1233

NF_10uF;20%;6.3V;0402

JP1201

TOP;BOT

L91 2

C1236

1.0UF;20%;6.3V;0201

21

C1207

1.0UF;20%;6.3V;0201

21

C1226

10uF;20%;6.3V;0402

C1235

1.0UF;20%;6.3V;0201

2 1

U1101E

MFG_NO

NC_DNU

VSF1M3

VSF2N3

VSF3M4

VSF4N4

VSF5M5

VSF6N5

VSF7M6

VSF8N6

VSF9M7

NC_1D16

NC_2K17

NC_3N7

NC_4T17

NC_5AB16

NC_6AC16

DNU_1A1

DNU_2A2

DNU_3A17

DNU_4A18

DNU_5B1

DNU_6B18

DNU_7AC1

DNU_8AC18

DNU_9AD1

DNU_10AD2

DNU_11AD17

DNU_12AD18

C1209

1.0UF;20%;6.3V;02012

1

C1217

1.0UF;20%;6.3V;0201

21

C12012.2uF;20%;6.3V;0201

C1221

1.0UF;20%;6.3V;0201

21

U1101F

MFG_NO

GND

VSSM_1K13

VSSM_2K14

VSSM_3K16

VSSM_4L12

VSSM_5L15

VSSM_6L16

VSSM_7M8

VSSM_8M13

VSSM_9M14

VSSM_10N8

VSSM_11N12

VSSM_12N15

VSSM_13N16

VSSM_14P13

VSSM_15P14

VSSM_16R15

VSSM_17R16

VSSM_18R17

VSS_1B4

VSS_2B6

VSS_3B8

VSS_4C4

VSS_5C5

VSS_6C7

VSS_7C14

VSS_8D4

VSS_9D6

VSS_10D8

VSS_11D14

VSS_12D15

VSS_13E14

VSS_14F14

VSS_15G4

VSS_16G5

VSS_17G6

VSS_18G13

VSS_19G15

VSS_20H4

VSS_21H7

VSS_22H13

VSS_23H15

VSS_24J6

VSS_25K4

VSS_26K7

VSS_27K8

VSS_28R4

VSS_29R7

VSS_30R8

VSS_31T6

VSS_32U4

VSS_33U7

VSS_34V4

VSS_35V5

VSS_36V6

VSS_37AA4

VSS_38AA6

VSS_39AA8

VSS_40AB4

VSS_41AB5

VSS_42AB7

VSS_43AC4

VSS_44AC6

VSS_45AC8

VSS_46U13

VSS_47U15

VSS_48V13

VSS_49V15

VSS_50W14

VSS_51Y14

VSS_52AA14

VSS_53AA15

VSS_54AB14

C1224

1.0UF;20%;6.3V;0201

21C1229

10uF;20%;6.3V;0402

C1237

1.0UF;20%;6.3V;02012

1

C1211

1.0UF;20%;6.3V;0201

21

U1101D

MFG_NO

PWR

VDDIL17

VCC_1M17

VCC_2N17

VCC_3P17

VCCQ_1J15

VCCQ_2J16

VCCQ_3J17

VCCQ_4K15

VCCQ_5R13

VCCQ_6R14

VCCQ_7T15

VCCQ_8T16

VDDQ_1A6

VDDQ_2A7

VDDQ_3A13

VDDQ_4A14

VDDQ_5B5

VDDQ_6H5

VDDQ_7H9

VDDQ_8J4

VDDQ_9J5

VDDQ_10J8

VDDQ_11T4

VDDQ_12T5

VDDQ_13T8

VDDQ_14U5

VDDQ_15U9

VDDQ_16AC5

VDDQ_17AD6

VDDQ_18AD7

VDDQ_19AD13

VDDQ_20AD14

VDD1_1A4

VDD1_2A9

VDD1_3A15

VDD1_4A16

VDD1_5B15

VDD1_6AC15

VDD1_7AD4

VDD1_8AD9

VDD1_9AD15

VDD1_10AD16

VDD2_1A5

VDD2_2A8

VDD2_3B9

VDD2_4B13

VDD2_5B14

VDD2_6G7

VDD2_7G8

VDD2_8G9

VDD2_9K2

VDD2_10L7

VDD2_11L8

VDD2_12L9

VDD2_13P7

VDD2_14P8

VDD2_15P9

VDD2_16R2

VDD2_17V7

VDD2_18V8

VDD2_19V9

VDD2_20AC9

VDD2_21AC13

VDD2_22AC14

VDD2_23AD5

VDD2_24AD8

C12050.1uF;20%;6.3V;0201

C1227

10uF;20%;6.3V;0402 C1219

1.0UF;20%;6.3V;0201

21

C12040.1uF;20%;6.3V;0201

C1212

1.0UF;20%;6.3V;0201

21

C1203

0.1uF;20%;6.3V;0201

C1223

1.0UF;20%;6.3V;0201

21

C12162.2uF;20%;6.3V;0201

C1242

1.0UF;20%;6.3V;0201

21

C1218

1.0UF;20%;6.3V;0201

21

C12022.2uF;20%;6.3V;0201

C12324.7uF;20%;6.3V;0402

C1225

10uF;20%;6.3V;0402

C1241

1.0UF;20%;6.3V;0201

21

C1208

1.0UF;20%;6.3V;0201

21

R1201NF_240;1%;0201

C12404.7uF;20%;6.3V;0402

C1213

2.2uF;20%;6.3V;0201

C12284.7uF;20%;6.3V;0402

C1222

1.0UF;20%;6.3V;0201

21

C1215

2.2uF;20%;6.3V;0201





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

PM6125_Bucks_S1-S4

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


VREG_S4A is REMOTE diff sense,VREG_Sx & RMT_GND_Sx should be routed as a differential pair Do not route VREG_Sx & RMT_GND_Sx near VIN_SxDo not route VREG_Sx & RMT_GND_Sx near VSW_Sx unless separated by ground shield

Diff Pair back to PMIC from load cap


Dual-phased buck

Shares input cap with VDD_S5

Diff Pair back to PMIC from load cap


Place Cin as close to PMIC as possible to achieve this requirement.

Loop inductance from (VIN_Sx to Cin + Cin to GND_Sx) must be < 3nH Nicobar Power Grid v1.31 10/31/2018

VREG_S2A is REMOTE diff sense,

VREG_Sx & RMT_GND_Sx should be routed as a differential pair Do not route VREG_Sx & RMT_GND_Sx near VIN_SxDo not route VREG_Sx & RMT_GND_Sx near VSW_Sx unless separated by ground shield

Dual-phased buck

S1A-2A: FTS510 0.8V default 8000mA Ipeak 8110.00mA APCS3A-4A: FTS510 0.8V default 8000mA Ipeak 8480mA CX, MODEMS5A: HFS510 0.912V default 4000mA Ipeak 3620.00mA EBI, MX, nLDOS6A: HFS510 1.352V default 4000mA Ipeak 1560mA LDOS7A: HFS510 2.04V default 2500mA Ipeak 2350mA LDOS8A: FTS510 1.128V default 4000mA Ipeak 1790mA LDO, LPDDR4x

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

VREG_S1A_S2A[7]

RMT_VREG_S1A_S2A_P [7]

RMT_VREG_S1A_S2A_M [7]

VREG_S3A_S4A[8]

RTM_VREG_S3A_S4A_P [8]

RTM_VREG_S3A_S4A_M [8]

Title

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DESIGNER:

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Custom

13 53

V10Page Name = 13_PM6125_Bucks_S1-S4



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

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13 53




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

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Custom

13 53




Design Name = S88512AA1_1_21_20190515_1605

C1322

10uF;20%;6.3V;0402

L1301

0.47UH;20%;2016

L1302

0.47UH;20%;2016

L1303

0.47UH;20%;2016

MFG_NO

U1301D

VREG1

RMT_GND_S146

VDD_S148

VREG_S158

VSW_S1_159

VSW_S1_260

VREG_S270

GND_S1_171

GND_S1_272

RMT_GND_S282

GND_S2_183

GND_S2_284

VSW_S2_195

VSW_S2_296

VDD_S2108

RMT_GND_S4117

VREG_S4118

VSW_S3_1119

VDD_S3120

VSW_S4_1128

GND_S4_1129

RMT_GND_S3130

GND_S3_1131

VSW_S3_2132

VDD_S4139

VSW_S4_2140

GND_S4_2141

VREG_S3142

GND_S3_2143

VSW_S3_3144

C1303

10uF;20%;6.3V;0402

JP1302

4/L8

2

JP1304

4/L8

2

C1302

1.0UF;20%;6.3V;0201

21

JP1301

4/L8

2

C1301

1.0UF;20%;6.3V;0201

21

L1304

0.47UH;20%;2016

C1321

10uF;20%;6.3V;0402

JP1303

4/L8

2

VSW_S2

VSW_S1

VSW_S4

VSW_S3





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

PM6125_Bucks_S5-S8

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Route diff pair out from Cap back toappropriate pins at PMIC

Load Caps are remote

VREG_S8A is LOCAL diff sense,VREG_Sx & RMT_GND_Sx should be routed as a differential pair Do not route VREG_Sx & RMT_GND_Sx near VIN_SxDo not route VREG_Sx & RMT_GND_Sx near VSW_Sx unless separated by ground shield

Place Cin as close to PMIC as possible to achieve this requirement.

Loop inductance from (VIN_Sx to Cin + Cin to GND_Sx) must be < 3nH

Shares input cap with VDD_S1

Note: Dedicated trace for connecting the sense(VREG_S6) from bulk caps on layout.

Note: Dedicated trace for connecting the sense(VREG_S7) from bulk caps on layout.

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

VREG_S5A[7,9,15]

VREG_S5A_SNS [7]

VREG_S6A[15,21]

VREG_S7A[15,21]

VREG_S8A[8,11,12,15]

RTM_VREG_S8A_P [12]

RTM_VREG_S8A_M [12]

Title

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Design Name = S88512AA1_1_21_20190515_1605

Title

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Design Name = S88512AA1_1_21_20190515_1605

Title

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14 53




Design Name = S88512AA1_1_21_20190515_1605

JP1408

4/L8

2

JP1402

4/L8

2

JP1404

4/L8

2

L1404

0.47UH;20%;2016

L1402

0.47UH;20%;2016

C1403

NF_10uF;20%;6.3V;0402

JP1401

4/L8

2

L1403

0.47UH;20%;2016

L1401

0.47UH;20%;2016

C1408

10uF;20%;6.3V;0402

C1406

10uF;20%;6.3V;0402

C1402

1.0UF;20%;6.3V;0201

21

C1401

1.0UF;20%;6.3V;0201

21

JP1403

4/L8

2

C1407

10uF;20%;6.3V;0402C1409

10uF;20%;6.3V;0402

JP1405

4/L8

2

C1405

10uF;20%;6.3V;0402

MFG_NO

U1301E

VREG2

GND_S6_11

VDD_S83

VSW_S8_14

GND_S8_15

GND_S76

VSW_S7_17

VDD_S78

GND_S5_111

VSW_S5_112

VSW_S6_113

GND_S6_214

VSW_S8_216

GND_S8_217

VSW_S7_219

GND_S5_223

VSW_S5_224

VDD_S625

VSW_S6_226

VREG_S828

RMT_GND_S829

VREG_S534

VSW_S5_335

VDD_S536

VREG_S652

VREG_S754

VSW_S7

VSW_S6

VSW_S8

VSW_S5





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

PM6125_LDOs

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


LDO L5/L9/L10/L11/L12/L13/L14/L15/L16/L19/L20/L21/L22/L23/L24 is the Pseudo-capless LDO, so can dni CAP in BOM

1.0uFNicobar Power Grid v1.31 11/12/2018

LDO Input Rail Parent Buck Max CurrentVDD_L1_L7_L17_L18 VREG_S6 1.13VDD_L2_L3_L4 VREG_S8 0.816VDD_L5_L15_L19_L20_L21_L22 Ext Boost Byp 1.38VDD_L6_L8 VREG_S5 0.906VDD_L9_L11 VREG_S7 1.01VDD_L10_L13_L14 VREG_S7 1.08VDD_L12_L16 VREG_S7 0.270VDD_L23_L24 Ext Boost Byp 1.161

LDO Type Source V_default (est) Target Pin#L1 N600 S6A 1.2V (625) QLN,SDR 1,2 61L2 N300 S8A 1V (320) SDR VDD 1.0V 63L3 N600 S8A 1V (370) SDR VDD 1.0V 64L4 N300 S8A 0.928V (126) QLINK, EBI, MIPI 39L5 MVP50 VPH 2.96V (22) PX 113L6 N1200 S5A 0.624V (1040) VDDQ, EBI 9L7 N600 S6A 0.928V (54.2) USB 49L8 N300 S5A 0.664V (81) CX 33L9 LVP600 S7A 1.8V (754) Sensors, WCD, TMD, PMI_MSM, QET 43L10 LVP150 S7A 1.8V (100) QFPROM, USB,UFS, PX 81L11 LVP600 S7A 1.8V (925) EMMC/VCCQ 45L12 LVP300 S7A 1.8V (121) OV. USB_REDRIVER 69L13 LVP300 S7A 1.8V (204) QPM 1.8V, BBRX, GPS 105L14 LVP600 S7A 1.8V (650) WCD Buck 94,93L15 MVP150 VPH 3.128V (5.28) USB 3.1V, DP PHY 114L16 LVP150 S7A 1.8V (92.5) WCSS, WCN_XO 93L17 N300 S6A 1.304V (246) WCN, WCSS ADX DAC 38L18 N300 S6A 1.232V (133) MIPI, VDDPX 37L19 MVP150 VPH/BB 1.8V (60.2) Memory, SN100, PX 126L20 MVP150 VPH/BB 1.8V (60.2) Memory, SN100, PX 138L21 MVP600 VPH/BB 2.704V (0.68) QAT, DFE, RTC,QSW 136L22 MVP600 VPH/BB 2.96V (800) MMC 137L23 MVP600 VPH/BB 3.304V (591) WCN 3.3V 41L24 MVP600 VPH/BB 2.96V (1170) EMMC 31

2.2uF

PSEUDO CAPLESS LDOsP-type are psuedo-capless, cap can be at loadFor CAPLESS LDOs: If decaps on the load side do notadd up to LDO spec, then install the cap close to the PMIC

Note: Place LDO input caps near to PMIC

VREG_S6A [14,21]

VREG_S8A [8,11,12,14]

VPH_PWR [13,14,16,18,19,20,21,37,40,42,43,44,62,67,75]

VREG_S5A [7,9,14]

VREG_S7A [14,21]

VREG_L1A_1P2[60]

VREG_L2A_1P0[60]

VREG_L3A_1P0[60]

VREG_L4A_0P928[9]

VREG_L5A_2P96[8,45]

VREG_L6A_0P6[4,9,11,12]

VREG_L7A_0P928[9]

VREG_L8A_0P736[8]

VREG_L9A_1P8[3,8,12,16,17,20,37,44,45,47,60,61,62,75,77]

VREG_L9_LVS[40]

VREG_L10A_1P8[7,8,9,16]

VREG_L11A_1P8[12]

VREG_L12A_1P8[3,41]

VREG_L13A_1P8[60]

VREG_L14A_1P8[20]

VREG_L15A_3P104[9]

VREG_L16A_1P8[9,77,79]

VREG_L17A_1P304[9,77]

VREG_L18A_1P232[8,9]

VREG_L19A_1P8[8,45]

VREG_L20A_1P8[8,45]

VREG_L21A_2P704[67]

VREG_L22A_2P96[45]

VREG_L23A_3P304[77,78]

VREG_L24A_2P96[12]

Title

Size

DESIGNER:

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DOCUMENT NO.:

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15 53

V10Page Name = 15_PM6125_LDOS



Design Name = S88512AA1_1_21_20190515_1605

Title

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Title

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Design Name = S88512AA1_1_21_20190515_1605

C1518

10uF;20%;6.3V;0402

C1530

NF_10uF;20%;6.3V;0402

C1502

1.0UF;20%;6.3V;0201

21

C1501

1.0UF;20%;6.3V;0201

21 C1512

1.0UF;20%;6.3V;0201

21

C15162.2uF;20%;6.3V;0201

C1531

10uF;20%;6.3V;0402

C1511

1.0UF;20%;6.3V;0201

21

C1532

10uF;20%;6.3V;0402

C1519

NF_4.7uF;20%;6.3V;0402

C1525

10uF;20%;6.3V;0402

C1533

10uF;20%;6.3V;0402

MFG_NO

U1301F

VREG3

VREG_L69

VDD_L6_L820

VDD_L2_L3_L4_127

VREG_L2431

VREG_L9_LVS32

VREG_L833

VREG_L1837

VREG_L1738

VREG_L439

VDD_L2_L3_L4_240

VREG_L2341

VDD_L23_L2442

VREG_L943

VREG_L1145

VREG_L749

VDD_L1_L7_L17_L1850

VDD_L9_L1156

VREG_L1657

VREG_L161

VREG_L263

VREG_L364

VDD_L12_L1668

VREG_L1269

VDD_L10_L13_L1480

VREG_L1081

VREG_L14_193

VREG_L14_294

VREG_L13105

VREG_L5113

VREG_L15114

VDD_L5_L15_L19_L20_L21_L22125

VREG_L19126

VREG_L21136

VREG_L22137

VREG_L20138

C15152.2uF;20%;6.3V;0201

C1528

10uF;20%;6.3V;0402

C1504

1.0UF;20%;6.3V;0201

21

C15172.2uF;20%;6.3V;0201

C1529

NF_10uF;20%;6.3V;0402





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

PM6125_HK/IO

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


TEST_EN_VPP must be grounded in all chipset level and customer-facing HW schematics.

GND_XOADC Skinny trace to XTAL components ground. One dedicated via to main ground place as close to PMIC pin as possible

AVDD_BYP should be routedaway from noisy traces

Critical Layout Guidelines for Clocks (go/PmicLayoutChecklist)Coupling to any RFCLK or LNBBCLK output from each aggressor should be < 50 fF.1. SMPS components (Buck, Boost, Charger)2. VSW_Sx traces (Buck, Boost, Charger)3. All other RFCLK, LNBBCLK4. Any high speed digital signal5. Any other noisy signals

SPMI_CLK & SPMI_DATA should be routed away from noisy tracesRoute signals as a diff pair as much as possible

REF_BYP and REF_GND should be routed away from noisy traces

Placement/Layout Note:VREG_RF Cout should be placed close to the PMICCan be prioritized over VREG_XO Cout placement

Route XTAL IN/OUT trace withlength between 3mm and 10mm

Short dedicated route to VREG_RF/XO capDedicated via directly to main ground plane at the capacitor

Dedicated trace from REF_BYP to cap. Dedicated trace from REF_GND to cap.Dedicated via to main ground plane right under PMIC pin (REF_GND) or as close to the pin as possible. Do NOT add via at cap.

Trace from pin to cap and ONE dedicated via from cap to main ground plane.DCR < 200mOhm and ESL < 10nHDo NOT connect to any other ground.

Critical Layout Guidelines for VREF_RF (go/PmicLayoutChecklist)

Preferred: Short, dedicated route to VREG_RF cap, away from noisy signals and dedicated via to main ground plane at cap or PMIC pin.

Acceptable: Dedicated via directly to main ground plane at the GND_CLKSXO pin and at VREG_RF cap (without routing to cap).

Do NOT connect to any other ground.

Loop DCR must be <1000 m?.Loop inductance must be <3 nH.

Layout Note:No trace shall be present in at-least two immediate layers below XTAL.

If RTC support is not needed when the battery is removed, a backup capacitor can be used on the VCOIN pin. A ceramic capacitor with an effective capacitance of 10uF can support SMPL for up to 1 second.

If USB the LPDDR3 need this VREF voltage, LPDDR4 don't need it.

If you use embedded battery ,can remove these capcitors PON_RESET_N[2,17]

FAULT_N[17]

SYS_OK[17]

KYPDPWR_N[17,46]

PS_HOLD[2]

RESIN_N[46]

PMIC_SPMI_CLK[2,17]

PMIC_SPMI_DATA[2,17]

LN_BB_CLK1[2]

WLAN_XO_CLK[6]

RF_CLK1[58]

RF_CLK2[77]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

VPH_PWR[13,14,15,18,19,20,21,37,40,42,43,44,62,67,75]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

VREF_MSM[7,8]

SLEEP_CLK [2,77]

VIO_OUT[8,17]

VREG_L10A_1P8[7,8,9,15]

PA_THERM0 [67]

QUIET_THERM [2]

KYPD_VOLP_N[46]

EMMC_UFS_THERM[11]

XO_THERM[16]

GND_XOADC[16]

GND_XOADC [16]

XO_THERM[16]

BOARD_ID2[3]

BOARD_ID3[3]

Title

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V10Page Name = 16_PM6125_HK_IO



Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

Y1601

XTAL_X1E000401000400

THERMISTOR4

2GND/THERMISTOR

XTAL23

XTAL11

C16051000pF;10%;25V;0201

C1601

1.0UF;20%;6.3V;0201

21

MFG_NO

U1301B

CMN_GND_153

CMN_GND_265

CMN_GND_366

CMN_GND_467

CMN_GND_578

CMN_GND_679

CMN_GND_790

C161222pF;30%;50V;0201

R1601 0;0.5A;0201

JP1602

4/L8

2

C1608

10uF;20%;6.3V;0402

JP1603

4/L8

2

R1606

75K;1%;0201

R1605 0;0.5A;0201

JP1606

4/L8

2

JP1601

4/L8

2

C16090.1uF;20%;6.3V;0201

C1604

10uF;20%;6.3V;0402

JP1605

4/L8

2

C1610

0.1uF;20%;6.3V;0201

U1301A

MFG_NO

HK

TEST_EN_VPP2

VREF_LPDDR351

SLEEP_CLK55

VREF_MSM62

AVDD_BYP73

DVDD_BYP74

REF_BYP75

REF_GND76

VIO_IN77

GND_XOADC85

AMUX_186

VIO_OUT87

RF_CLK288

LN_BB_CLK289

SPMI_DATA91

PON_RESET_N92

XO_THERM97

AMUX_298

LN_BB_CLK399

RF_CLK1100

VREG_BB101

VPH_PWR102

RESIN_N103

SPMI_CLK104

FAULT_N107

VREG_RF_CLK109

GND_RF110

VDD_LDO_XO_RF111

LN_BB_CLK1112

KPD_PWR_N115

CBL_PWR_N116

XTAL_OUT121

GND_XO122

VREG_XO123

OPTION124

PS_HOLD127

XTAL_IN_1133

XTAL_IN_2134

VCOIN135

R1603 0;0.5A;0201

C16130.1uF;20%;6.3V;0201

C16070.1uF;20%;6.3V;0201

C1611

15pF;10%;50V;0201

JP1604

4/L8

2

R1604 0;0.5A;0201

C1606

10uF;20%;6.3V;0402

C1603

1.0UF;20%;6.3V;0201

21

MFG_NO

U1301C

UI

GPIO_0710

GPIO_0315

GPIO_0918

GPIO_0521

GPIO_0822

GPIO_0230

GPIO_0144

GPIO_0447

GPIO_06106

C1602

1.0UF;20%;6.3V;0201

21

PM_AVDD_BYP

XO_THERM





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

PMI632_Control

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


REF_BYP and REF_GND should be routed away from noisy traces

Trace from pin to cap and ONE dedicated via from cap to main ground plane.DCR < 200mOhm and ESL < 10nHDo NOT connect to any other ground.

AVDD_BYP should be routedaway from noisy traces

GPIO# GPIO FunctionGPIO1 (LV) FMB1 (Output mode) / TypeC_CONN_THERM_SNS / MSM/eMMC THERMGPIO2 (MV) SMB_EN / HRLED / (SINK required ?Fixed 10mA)GPIO3_AMUX Skin_Therm_Sns / FLASH_THERM_SNSGPIO4 (LV) I2C_IRQ (Output) / TypeC_CONN_THERM_SNS / FMB2 (Output)GPIO5_AMUX (MV) SMB_THERM_SNS / Flash_Strobe / USB_IDGPIO6 (LV) WLED_ENGPIO7_AMUX (LV) SMB_VCHG_PGPIO8_AMUX (LV) FMB2 (Output) / SMB_VHG_M

Dedicated trace from REF_BYP to cap. Dedicated trace from REF_GND to cap.Dedicated via to main ground plane right under PMIC pin (REF_GND) or as close to the pin as possible. Do NOT add via at cap.

KYPDPWR_N[16,46]

PON_RESET_N[2,16]

FAULT_N[16]

PMIC_SPMI_CLK[2,16]

PMIC_SPMI_DATA[2,16]

VIO_OUT [8,16]

VREG_L9A_1P8[3,8,12,15,16,20,37,44,45,47,60,61,62,75,77]

SYS_OK [16]

CHARGER_SKIN_THERM[17]

CHARGER_SKIN_THERM [17]

Title

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17 53

V10Page Name = 17_PMI632_CONTROL



Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

R1702

NF_100K;1%;0201

JP1701

4/L8

2

MFG_NO

U1701B

GPIO

BLOCKID

GPIO661

GPIO562

GPIO768

GPIO369

GPIO170

GPIO877

GPIO478

GPIO279

C1701

1.0UF;20%;6.3V;0201

2 1

C17020.1uF;20%;6.3V;0201

R1701

1M;5%;0201

NTC1102100K;1%;0201

12

JP1702

4/L8

2

MFG_NO

U1701A

PON

BLOCKID

KYPDPWR_N2

SYS_OK3

TEST_EN_VPP24

NC2_TST31

SPMI_DATA34

VDD_MSM_IO35

SPMI_CLK43

FAULT_N44

PS_HOLD45

OPTION52

REF_GND53

REF_BYP54

AVDD_BYP63

TP17011

MFG_NO

U1701C

CGND

BLOCKID

CMN_GND_025

CMN_GND_133

CMN_GND_242

CMN_GND_351

CMN_GND_459

CMN_GND_560





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

PMI632_LCD/VIB/RGB/Flash

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Layout Note:DISP_HW_ENThis signal is used for "Display Tap to Wake"If unused in HW, this pin should be connected to GND

Layout Note:VDISP_CAPxPlace fly cap as close to the pin as possible.Avoid routing VDISP_CAP1 trace under VDISP_M_OUT.

NOTE:C2404 can use the 25V capacitor too, just for the BOM category normalized

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

VMID_USB_IN [19]

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

FLASH_LED1[42]

RED_LED[42]

VIB_DRV_LDO_P[37]

Title

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18 53

V10Page Name = 18_PMI632_LCD_VIB_RGB_Flash



Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

MFG_NO

U1701E

LCDB

BLOCKID

VDD_DISP6

VDISP_CAP27

VDISP_M_OUT8

NC1_VDISP_P_OUT9

DISP_HW_EN15

GND_DISP_M16

VDISP_CAP117

VDISP_MID18

VSW_DISP26

PGND_DISP27

VDISP_P_OUT36

JP1801

4/L8

2

JP1805

4/L8

2

C1801

1.0UF;20%;6.3V;0201

21

C1802

1.0UF;20%;6.3V;0201

21

JP1806

4/L8

2

MFG_NO

U1701F

UI

BLOCKID

RGB_GRN4

VIB_DRV_LDO_P5

RGB_RED13

RGB_BLU14

PVDD23

VIN_FLASH_071

F_LED172

F_LED280

VIN_FLASH_181

C18052.2uF;20%;16V;0402

C1803

1.0UF;20%;6.3V;0201

21

JP1807

4/L8

2





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

PMI632_Charger/PD PHY

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


CAD NOTE:Dedicated VIA to Main GND

CAD NOTE:Dedicated VIA to Main GND

Place mid cap close to pin

NOTE:BOOT_PWR net is 5VDC,cap is 0603. Do not use 0402 as may derate to -80%.

Layout Note:PACK_SNS_M should have a dedicated route to battery connector negative senseNOTE:recommand to use battery NTC values 100K, B=4250

NOTE:Use C1902= 2.2uF for paraller Charging ConfigUse C1902= 4.7uF for only PMI Charging Config

NOTE:C1902 can use the 25V capacitor too, just for the BOM category normalized

VBUS_USB_IN [48]

USB_PHY_PS[3]

USB_ID[47,48]

USB0_HS_DP[2,47,48]

USB0_HS_DM[2,47,48]

VBATT_VSNS_P[36]

VBATT_VSNS_M[36]

BATT_THERM[36]

BATT_ID[36]

VMID_USB_IN[18]

VPH_PWR[13,14,15,16,18,20,21,37,40,42,43,44,62,67,75]

VBATT[36,47]

BOOT_PWR

USB_CC2[47,48]

Title

Size

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19 53

V10Page Name = 19_PMI632_Charger_PD PHY

Page Modif y Date = Wednesday , May 15, 2019


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Design Name = S88512AA1_1_21_20190515_1605

C1912220PF;10%;25V;0201

C1902

4.7UF;10%;35V;0603

R1901 1K;5%;020112

JP4105

4/L8

2

JP1903

4/L8

2

C19080.1uF;20%;6.3V;0201

L1901

1.0UH;20%;2520

D1901

ESD56201D04

12

JP1901

4/L8

2

C19034.7UF;10%;35V;0603

C1909

0.1uF;20%;25V;0201

C1905

10uF;20%;6.3V;0402

JP1904

4/L8

2

C1910

100pF;30%;50V;0201

C19044.7uF;10%;10V;0603

JP1902

4/L8

2

C1911220PF;10%;25V;0201

C1907

10uF;20%;6.3V;0402

C1901

0.027uF;20%;16V;0201

MFG_NO

U1701D

CHARGER

BLOCKID

USB_IN_01

USB_IN_110

USB_IN_211

GND_PSUB_CHG12

USB_IN_MID_019

USB_IN_MID_120

USB_IN_MID_221

BOOT_PWR22

VSW_CHG_028

VSW_CHG_129

VSW_CHG_230

VARB32

PGND_CHG_037

PGND_CHG_138

PGND_CHG_239

BOOT_CAP40

CC_OUT41

CC1_ID46

CC247

REF_GND_CHG48

USB_DP49

GND_CHG50

VPH_PWR_055

VPH_PWR_156

VPH_PWR_257

USB_DM58

VBATT_PWR_064

VBATT_PWR_165

VBATT_PWR_266

BAT_ID67

VBATT_PWR_373

VBATT_SNS_P74

PACK_SNS_M75

BAT_THERM76

R1902 1K;5%;020112

C1906

10uF;20%;6.3V;0402

VMID_USB_IN

VSW_CHG





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

WCD9370

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Star route from VREG_L9A_1P8 to VDD_PX and VDD_TXRX.

WCD_RESET_N[3]

AMIC1_INP[38]

AMIC1_INM[38]

AMIC2_INP[39]

AMIC2_INM[39]

AMIC3_INP[38]

AMIC3_INM[38]

SWR_RX_CLK[3]

SWR_TX_CLK[3]

SWR_TX_DATA0[3]

SWR_RX_DATA0[3]

SWR_TX_DATA1[3]

SWR_RX_DATA1[3]

HPH_L[39]

HPH_R[39]

HPH_REF[39]

MIC_BIAS1 [48]

MIC_BIAS2 [39]

MIC_BIAS3 [38]

HSDET_L[39]

PA_VNEG[20]

PA_VPOS[20]

WCD_BUCK_FLYB_GND [20]

WCD_BUCK_FLYB_GND[20]

EAR_OUT_P [37]

EAR_OUT_M [37]

PA_VPOS[20]

PA_VNEG[20]


VPH_PWR[13,14,15,16,18,19,21,37,40,42,43,44,62,67,75]

VREG_L9A_1P8[3,8,12,15,16,17,37,44,45,47,60,61,62,75,77]

VREG_L14A_1P8[15]



Title

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V10Page Name = 20_WCD9370



Design Name = S88512AA1_1_21_20190515_1605

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Title

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Design Name = S88512AA1_1_21_20190515_1605

C20140.47UF;20%;6.3V;0201

C2003

1.0UF;20%;6.3V;0201

21

JP2007

4/L8

2

R2002 0;0.5A;0201

R20050;0.5A;0201

C2002

1.0UF;20%;6.3V;0201

21

JP2006

4/L8

2

C2013470pF;20%;50V;0201

U2001

MFG_NO

PRELIMINARY

1VDD_PX

2 INTR1

3 AMIC1_INP

4VDD_MIC_BIAS

5VDD_EFUSE_BLOW

6 CDC_PDM_RX0

7 CCOMP

8 AMIC3_INP

9 AMIC1_INM

10 LDO_H

11VDD_CX

12 CDC_PDM_TX

13 AMIC3_INM

14 AMIC2_INM

15 MIC_BIAS1

16 CDC_PDM_CLK

17 CCOMP_REF

18 AMIC4_INP

19 AMIC2_INP

20 MICB_CFILT_REF

21GND_D

22 CDC_PDM_RX1

23 AMIC4_INM

24 MIC_BIAS225 MIC_BIAS3

26 CDC_PDM_RX0_COMP

27 CDC_PDM_RX2

28 MBHC_HSDET_G

29GND_RXTX_SRGR

30BUCK_VSW

31 I2C_DATA

32 CDC_PDM_SYNC

33VDD_TXRX

34BUCK_OUT

35VDD_BUCK

36 CDC_PDM_RX1_COMP

37 I2C_CLK

38 HPH_REF

39 RESET_N

40GND_BUCK

41EAR_OUT_M

42 MODE

43 PA_VPOS

44 MBHC_HSDET_L

45FLYB_VSW

46EAR_OUT_P

47AUX_OUT_M

48 HPH_R

49 PA_VNEG

50FLYB_VNEG_OUT_CLSH

51AUX_OUT_P

52GND_A

53 HPH_L 54FLYB_VNEG_OUT_DAC

55CRN_VNEG_OUT_DAC

C2019680pF;20%;25V;0201

C20110.47UF;20%;6.3V;0201

L2001

120ohm;350mA;0402

C2001

1.0UF;20%;6.3V;0201

2 1

C20220.1uF;20%;6.3V;0201

JP2012

4/L8

2

C2009 100pF;30%;50V;0201

C20210.1uF;20%;6.3V;0201

JP2003

4/L8

2

C20230.1uF;20%;6.3V;0201

JP2002

4/L8

2

JP4106

4/L8

2

C2018

0.1uF;20%;6.3V;0201

JP2008

4/L8

2

JP2001

4/L8

2

C2006

100pF;30%;50V;0201

L2004

1000OHM;600mA;0603

C20170.47UF;20%;6.3V;0201

R20010;0.5A;0201

C20150.1uF;20%;6.3V;0201

C2004

1.0UF;20%;6.3V;0201

21

L2003

1000OHM;600mA;0603

JP20044/L8

2

L2002

120ohm;350mA;0402

C20240.1uF;20%;6.3V;0201

JP2005

4/L8

2

C2007

100pF;30%;50V;0201

C2016

4.7uF;20%;6.3V;0402

C2005680pF;20%;25V;0201

C20120.22uF;20%;6.3V;0201

FLYB_VSW

BUCK_VSW

FLYB_VNEG_DAC

WCD_GND_A





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

CAM eLDOs

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


800mA LDO for Rear Camera (CAM0_DVDD_1P1)

20mil 20mil 300mA 1.8V

LDO for CAM1_2_DVDD_1P2

LDO for CAM1_2_3_AVDD_2P8

LDO for CAM_AF_2P8兼容TP2.8V

LDO for Rear Camera (VCAMA_EXT)2.9V

LDO for Rear Camera (VCAMA_EXT)1.8V

20mil 300mA 1.8V20mil

LDO for CAM1_2_DVDD_1P05GND

GND

GND GND

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

CAM0_AVDD_2P9 [41]

CAM0_AVDD_EN[3]

VREG_S7A[14,15,21]

CAM1_2_DVDD_1P2 [41]

CAM1_2_DVDD_EN[3]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

CAM1_2_3_AVDD_2P8 [41]

CAM1_2_3_AVDD_EN[3]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

CAM_AF_2P8 [41]

CAM_AFVDD_EN[3]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

CAM0_DVDD_1P1 [41]

CAM0_DVDD_EN[3]

VREG_S6A[14,15]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

CAM0_AVDD_1P8 [41]

CAM0_AVDD_EN2[3]

VREG_S7A[14,15,21]

CAM1_2_DVDD_1P05 [41]

IR_LED_EN[3]

Title

Size

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V10Page Name = 21_CAM eLDOs



Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

Title

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Design Name = S88512AA1_1_21_20190515_1605

C2110

1.0UF;20%;6.3V;0201

C21071.0uF;20%;6.3V;0201

C21061.0uF;20%;6.3V;0201

C21041.0uF;20%;6.3V;0201

U2105

SGM2031-2.8YUDH4G/TR

OUT1

GND12

EN3

IN4

GND25

TP21051

TP21041

C2108

1.0UF;20%;6.3V;0201

U2106

LDO-TCR8BM11A

1VOUT

2 BIAS

3 CONTROL

4 VIN

5GND

C2103

1.0UF;20%;6.3V;0201

U2101


OUT1

GND12

EN3

IN4

GND25

C2105

1.0UF;20%;6.3V;0201

C21161.0uF;20%;6.3V;0201

C2117

1.0UF;20%;6.3V;0201

U2104


OUT1

GND12

EN3

IN4

GND25

U2103


OUT1

GND12

EN3

IN4

GND25

TP21011

C21141.0uF;20%;6.3V;0201

U2108


OUT1

GND12

EN3

IN4

GND25

C2115

1.0UF;20%;6.3V;0201

TP47311

C21111.0uF;20%;6.3V;0201

U2107


OUT1

GND12

EN3

IN4

GND25

C21122.2uF;20%;6.3V;0201

C21130.1uF;20%;6.3V;0201

C21091.0uF;20%;6.3V;0201

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BATTERYCONNECTOR

SCL

SDA

GND

BATT_ID[19]

VBATT [19,47]

BATT_THERM[19]

VBATT_VSNS_P [19]

VBATT_VSNS_M [19]

BATT_ID_CON[47]

BATT_THERM_CON[47]

Title

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V10Page Name = 36_Battery/USB IF



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Design Name = S88512AA1_1_21_20190515_1605

R3607 1K;5%;02011 2

SG3603

L1

12

D3602

ESD56201D04

12

D3601ESD5651N-2/TR

N1

1N

22

D3604ESD5651N-2/TR

N1

1N

22

C3602

33pf;30%;50V;0201

R3608 100;5%;02011 2

C3603

10uF;20%;6.3V;0402

POWER/GND

POWER/GND

J3601

BM25-4S/2-V(51)

123

45

678 9

1011

1213

141516

SG3710

L1

12

D3603ESD5651N-2/TR

N1

1N

22

C3601

0.1uF;20%;6.3V;0201

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

6mil

6mil

6mil

6mil

Close to connectorClose to BB

Receiver

Connecting the GNDs together andthen to main GND through signle via

32mil32mil

SPK

VIB15mil 15mil

XM-217-XC-173

XM-217-XC-173

EAR_OUT_P[20]

EAR_OUT_M[20]

SPK_N [48]SPK_P [48]

INT_SMARTPA[3]

I2S1_SCK[3]

I2S1_WS[3]

I2S1_DATA0[3]

VPH_PWR [13,14,15,16,18,19,20,21,40,42,43,44,62,67,75]

VIB_DRV_LDO_P[18]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

SPK_SCL[3]

AUDIO_PA_RST[3]

SPK_SDA[3]

I2S1_DATA1[3]

SPK_VSENS_P [48]

SPK_VSENS_N [48]

GND_SPK[37]

GND_SPK[37]

GND_SPK [37]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

GND_SPK [37]

Title

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Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

C3710

0.1uF;20%;25V;0201

L3701

75ohm

R3702 0;1A;0402

R3706 0;0.5A;0201

L3702

1.0UH;20%;2016

JP37024/L8

2

C3702

33pf;30%;50V;0201

C3709

10uF;20%;16V;0603

R3708 0;0.5A;0201

C37151.0UF;20%;6.3V;0201

D3702LESD8D5.0CT5GN

11

N2

2

C3703

33pf;30%;50V;0201

J37024-00-45979

1

2

C371610uF;10%;10V;0603

U3701

MAX98937

LX1 A1

LX2 A2

PG

ND

1A

3

PVDD1A4

OUTP1 A5

OUTP2 A6

LX3B1

LX4 B2

PG

ND

2B

3

PVDD2 B4

PVDD3 B5

VSNSP B6

VBAT C1

ADDR2C2

PG

ND

3C

3

PG

ND

4C

4

PG

ND

5C

5

VSNSNC6

VREFC D1

DIND2

GN

D1

D3

GN

D2

D4

OUTN1D5

OUTN2 D6

BCLKE1

DOUT/PDMTXDATE2

WDT/PDMRXDATE3

SCLE4

ADDR1E5

IRQE6

MCLK/PDMRXCLKF1

LRCLKF2

DVDD F3

SDAF4

ICC/PDMTXCLKF5

RESETF6

C3701100pF;30%;50V;0201

TP3701

1

B3702

0;1A;06031 2

C3704

100pF;30%;50V;0201

JP37014/L8

2

SG37114/L10

2

JP37044/L8

2

JP37034/L8

2

J37034-00-45979

1

2

SG37014/L10

2

C371410uF;20%;16V;0603

R371047K;5%;0201

R3703 0;1A;0402

C3707

0.1uF;20%;10V;0201

J37044-00-45979

1

2

D3701LESD8D5.0CT5G

N1

1N

22

TP3702

1

C3711

33pf;30%;50V;0201

R3705 0;0.5A;0201

D3703RB521CS-30

21

C37061.0UF;20%;6.3V;0201

B37010;1A;06031 2

C3717

33pf;30%;50V;0201

R371310K;1%;0201

C3712

33pf;30%;50V;0201

J37054-00-45979

1

2

C3705

33pf;30%;50V;0201

R370710K;1%;0201

R3709 0;0.5A;0201

REC_P

REC_N

SW

OUT+OUT-

VBST

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAIN MIC

Close to BB

Handset 2nd Microphone (Rear - DMNR), AMIC

Close to MIC

Note 63-1: 1 uF for ACC modeSchematic design notice of "63_PERI_AUDIO_IO" page.

D_GND

D_GND

AMIC1_INM [20]

AMIC1_INP [20]AMIC1_INP_CON[48]

AMIC1_INM_CON[48]

AMIC3_INP [20]

AMIC3_INM [20]

MIC_BIAS3 [20]

Title

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Design Name = S88512AA1_1_21_20190515_1605

C38030.1uF;20%;6.3V;0201

C3808

33pf;30%;50V;0201

C3816

100pF;30%;50V;0201

R3804NF_0;0.5A;0201

JP38064/L8

2

C381168pF;2%;50V;0201

JP48084/L8

2

R3806

0;0.5A;0201

U3801

MIC-S15OB381-066

POWER1

SIGNAL_GND2

OUTPUT3

CASE_GND4

JP38034/L8

2

R3807

0;0.5A;0201

C3809

33pf;30%;50V;0201

R3803

0;0.5A;0201

C380533pf;30%;50V;0201

C3813

100pF;30%;50V;0201

D3801NF_LESD8D5.0CT5GN

11

N2

2

R38020;0.5A;0201

JP38024/L8

2

JP38014/L8

2

C380268pF;2%;50V;0201

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

need to debug

Note: Ferrite beads and their corresponding bypass capacitors onon CDC_HPH_L_P, CDC_HPH_L_M and CDC_HPH_REFare needed to reduce noise generated by audio/FM concurrency

AUDIO JACK

Note: For Cable detection

HSDET_L[20]

HPH_R[20]

HPH_L[20]

AMIC2_INP[20]

FM_ANT[77]

HPH_REF[20]

MIC_BIAS2[20]

AMIC2_INM[20]

Title

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Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

TVS3901PTVS4V5D1BL

N1

1N

22

C3910C0201_NC

B3902 1000OHM;600mA;0603

C3914

33pf;30%;50V;0201

JP3908

4/L10

2

R3904 10;5%;0402

TVS3903PTVS4V5D1BL

N1

1N

22

C3915

0.1uF;20%;6.3V;0201

C390233pf;30%;50V;0201

J3901

PH92-6B20C41A

1GND / MIC+

5DETECT / L AUDIO

2MIC+ / GND 3

R AUDIO4

L AUDIO / DETECT

JP3907

4/L102

C3909NF_18pF;10%;50V;0201

R3914 10K;5%;0201

B3904 1000OHM;600mA;0603

TVS3905AZ4217-01F

N1

1N

22

TVS3904PTVS4V5D1BL

N1

1N

22

L3902120ohm;900mA;0603

B3901 1000OHM;600mA;0603

TVS3902PTVS4V5D1BL

N1

1N

22

C3904

NF_1000pF;20%;50V;0201

JP3909

4/L10

2

JP3913

4/L10

2

C3903

NF_1000pF;20%;50V;0201

R39122.2K;5%;0201

C3906

33pf;30%;50V;0201

C390533pf;30%;50V;0201

B3905

1800ohm;100mA;0402

C39071000pF;20%;50V;0201

JP3915

4/L10

2

C3912

33pf;30%;50V;0201

R39112.2K;5%;0201

L3901NF_120nH;5%;0201

R3903NF_100K;5%;0201

R3913

NF_0;0.5A;0201

C3908

1000pF;20%;50V;0201

C3911

33pf;30%;50V;0201

R3901 10;5%;0402

R3902 10;5%;0402

C3913

33pf;30%;50V;0201

B3903 1800ohm;100mA;0402

JP3911

4/L10

2

JP3902

4/L10

2

C3901

33pf;30%;50V;0201

JP3905

4/L10

2

JP3901

4/L10

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LCD-Connector

OLED_DRIVIER

3.0V LDO

3.0V LDO reveser for TP NC

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDGND

MIPI_DSI0_L0_M[5]

MIPI_DSI0_L0_P[5]

MIPI_DSI0_L3_M[5]

MIPI_DSI0_L3_P[5]

MIPI_DSI0_CLK_M[5]

MIPI_DSI0_CLK_P[5]MIPI_DSI0_L2_M[5]

MIPI_DSI0_L2_P[5]

MIPI_DSI0_L1_M[5]

MIPI_DSI0_L1_P[5]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75]

LCM_AVDD_7P6 [40]

LCM_ELVDD [40]

LCM_ELVSS [40]

EL_ON2[40]

TS_INT_N [3]TS_I2C_SDA [3]TS_I2C_SCL [3]TS_RESET_N [3]LCD_ID [3]MDP_VSYNC_P [3]

LCD_RESET_N [3]

VDDP_EN [40]

FP_TP_VDD3P0[43,48]

LCM_AVDD_7P6[40]

VCI_3P0[40]

EL_ON2 [40]

ERR_INT_N

VDDP_EN[40]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75] VCI_3P0 [40]

VCI_3P0_EN[3]

VDDI_1P8[40]

LCM_ELVDD [40]

LCM_ELVSS [40]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75] TP_VDD3P0 [40]

TP_LDO_EN[3]

TP_VDD3P0 [40]

VDDI_1P8_EN[3]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67,75] VDDI_1P8 [40]

VREG_L9_LVS[15]

ERR_INT_N[3] BOARD_ID1 [40]

Title

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Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

C4019

NF_33pf;30%;50V;0201

C40240.1uF;20%;6.3V;0201

C400410uF;10%;10V;0603

C40411.0uF;20%;6.3V;0201

EMI4001

1 4

2 3

R4001

0;0.5A;0201

TP4002

1

C403927pF;10%;50V;0201

C4007

NF_33pf;30%;50V;0201

EMI4003

1 4

2 3

R4014100K;5%;0201

C4034NF_1.0uF;20%;6.3V;0201

EMI4002

1 4

2 3

C4022

0.1uF;20%;6.3V;0201

R40120;0.5A;0201

C4044

10uF;20%;6.3V;0402

C40311.0uF;20%;6.3V;0201

R4013 1K;5%;0201

U4003

NF_SGM2031-3.3YUDH4G/TR

OUT1

GND12

EN3

IN4

GND25

C4035NF_1.0uF;20%;6.3V;0201

C4038

27pF;10%;50V;0201

C404027pF;10%;50V;0201

C4005

NF_27pF;10%;50V;0201

C40421.0uF;20%;6.3V;0201

C4018

NF_33pf;30%;50V;0201

R4016

NF_0;0.5A;0201

1 2

C401522uF;16V;0805

C40230.1uF;20%;25V;0201

R4015NF_100K;5%;0201

C4008

NF_33pf;30%;50V;0201

U4001

AP7343D-30FS4-7B

VOUT1

GND12

EN3

VIN4

GND25

R4017 NF_0;0.5A;0201

1 2

EMI4005

1 4

2 3

R4018 0;0.5A;0201

1 2

GND4PIN

J4001

BAF04-40083-0500

123456789

1011121314151617181920 21

22232425262728293031323334353637383940

4142 43

44

C40210.1uF;20%;6.3V;0201

C40250.1uF;20%;6.3V;0201

L40014.7uH;20%;2520

L40024.7uH;20%;2520

C4001

22uF;20%;10V;0603

L4003 10uH;20%;2520

U4002

TPS65633BK

LX11

PGND12

VO13

FBS4

FD5

CT6

AGND7

EN_VO38

CTRL9

VO210

LX211

PVIN12

VO313

PGND214

LX315

AVIN16

GNDP17

C400322uF;16V;0805

C4033

22uF;20%;10V;0603

U4004


OUT1

GND12

EN3

IN4

GND25

C40321.0uF;20%;6.3V;0201

EMI4004

1 4

2 3

C40260.1uF;20%;6.3V;0201

TP4001

1

R4006 0;0.5A;0201

1 2

C4009

NF_33pf;30%;50V;0201

C4010

NF_33pf;30%;50V;0201

R4011

0;1A;0402R4002

0;0.5A;0201

R4003

0;0.5A;0201

R4005 0;0.5A;0201

1 2

C4045

10uF;20%;6.3V;0402

AVDD

ELVDD

ELVSS

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Depth Camera

AVDDAGND

Main Camera

Front Camera

需要注意所有的信号线都要维持50ohm阻抗，对于不用的信号线都要下拉 50ohm电阻端接。

CAM_MCLK2[3]

CCI_I2C_SDA1[3,41]CCI_I2C_SCL1[3,41]

CAM2_RST_N [3]

CAM_MCLK0 [3]

CAM0_AVDD_2P9 [21]

VSYNC [41]

CAM0_DVDD_1P1 [21]

VREG_L12A_1P8 [3,15,41]

CAM_MCLK3[3]

CAM1_2_DVDD_1P2 [21,41]

VREG_L12A_1P8 [3,15,41]

CAM1_2_3_AVDD_2P8 [21,41]

CAM1_2_DVDD_1P2 [21,41]

VREG_L12A_1P8 [3,15,41]

CAM1_2_3_AVDD_2P8 [21,41]

VREG_L12A_1P8[3,15,41]

CCI_I2C_SCL1 [3,41]

CCI_I2C_SDA1 [3,41]

CAM_MCLK1 [3]

CAM1_2_3_AVDD_2P8 [21,41]D_AGND [41]CAM1_RST_N [3]

VSYNC [41]

CCI_I2C_SDA1 [3,41]CCI_I2C_SCL1 [3,41]

CAM3_RST_N [3]

CAM0_RST_N [3]

CCI_I2C_SDA0 [3]CCI_I2C_SCL0 [3]

CAM_AF_2P8 [21]

D_AGND [41]

MIPI_CSI1_CLK_P[5,41]MIPI_CSI1_CLK_M[5,41]

MIPI_CSI1_L0_P[5,41]MIPI_CSI1_L0_M[5,41]

MIPI_CSI1_L3_P[5]MIPI_CSI1_L3_M[5]



MIPI_CSI1_L0_P[5,41]MIPI_CSI1_L0_M[5,41]

MIPI_CSI1_CLK_P[5,41]MIPI_CSI1_CLK_M[5,41]

MIPI_CSI0_CLK_P[5]MIPI_CSI0_CLK_M[5]


WIDE_CSI2_CLK_M [41]

WIDE_CSI2_CLK_P [41]

WIDE_CSI2_L0_M [41]

WIDE_CSI2_L0_P [41]

WIDE_CSI2_L1_M [41]

WIDE_CSI2_L1_P [41]

WIDE_CSI2_L2_M [41]

WIDE_CSI2_L2_P [41]

WIDE_CSI2_L3_M [41]

WIDE_CSI2_L3_P [41]

WIDE_CSI2_CLK_M_CON[41]

WIDE_CSI2_CLK_P_CON[41]

WIDE_CSI2_L0_M_CON[41]

WIDE_CSI2_L0_P_CON[41]







WIDE_CSI2_L2_M_CON [41]WIDE_CSI2_L2_P_CON [41]

WIDE_CSI2_CLK_M_CON[41]WIDE_CSI2_CLK_P_CON[41]

WIDE_CSI2_L0_M_CON[41]WIDE_CSI2_L0_P_CON[41]



FRONT_CSI2_CLK_M [41]

FRONT_CSI2_CLK_P [41]

FRONT_CSI2_L2_M [41]

FRONT_CSI2_L2_P [41]







FRONT_CSI2_CLK_M_CON[41]

FRONT_CSI2_CLK_P_CON[41]

FRONT_CSI2_L2_M_CON[41]

FRONT_CSI2_L2_P_CON[41]







FRONT_CSI2_CLK_P_CON[41]FRONT_CSI2_CLK_M_CON[41]

FRONT_CSI2_L0_P_CON[41]FRONT_CSI2_L0_M_CON[41]

FRONT_CSI2_L1_P_CON[41]FRONT_CSI2_L1_M_CON[41]

FRONT_CSI2_L2_P_CON [41]FRONT_CSI2_L2_M_CON [41]

FRONT_CSI2_L3_P_CON [41]FRONT_CSI2_L3_M_CON [41]

R_AGND [41]

R_AGND [41]CAM0_AVDD_1P8 [21]

VREG_L12A_1P8 [3,15,41]

FRONT_CSI2_L2_P[41]FRONT_CSI2_L2_M[41]

MIPI_CSI2_L2_M [5]FRONT_CSI2_L3_M[41]FRONT_CSI2_L3_P[41] MIPI_CSI2_L2_P [5]

FRONT_CSI2_CLK_P[41] MIPI_CSI2_L1_P [5]FRONT_CSI2_CLK_M[41]

MIPI_CSI2_L1_M [5]FRONT_CSI2_L1_P[41]FRONT_CSI2_L1_M[41] MIPI_CSI2_CLK_P [5]

FRONT_CSI2_L0_M[41] MIPI_CSI2_CLK_M [5]FRONT_CSI2_L0_P[41]

MIPI_CSI2_L3_M [5]WIDE_CSI2_L2_P[41]WIDE_CSI2_L2_M[41] MIPI_CSI2_L3_P [5]

WIDE_CSI2_L1_P[41] MIPI_CSI2_L0_M [5]WIDE_CSI2_L1_M[41]

MIPI_CSI2_L0_P [5]WIDE_CSI2_CLK_P[41]WIDE_CSI2_CLK_M[41]

WIDE_CSI2_L3_M[41]WIDE_CSI2_L3_P[41]

WIDE_CSI2_L0_M[41] FCAM_SEL [3]WIDE_CSI2_L0_P[41]

CAM_SW_EN [3]

CAM1_2_DVDD_1P05 [21]

Title

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Design Name = S88512AA1_1_21_20190515_1605

R4102

0;1A;0402

1 2

JP41024/L10

2

GND-4PIN

J4104

BB2R4-24KBJ03

123456789

101112 13

1415161718192021222324

2526 27

28

R41300;0.5A;0201 12

C4146

2.2uF;20%;6.3V;0201

R4142

0;0.5A;020112

C4152

C4127

NF_27pF;10%;50V;0201

R41310;0.5A;0201 12

TP4104

1

C4115

1.0UF;20%;6.3V;0201

R41170;0.5A;0201

12

C4122NF_27pF;10%;50V;0201

C4120C0201_NC R41390;0.5A;0201

12

R41340;0.5A;0201

12

C4153

4.7uF;20%;6.3V;0402

R41150;0.5A;0201

12

C41470.1uF;20%;6.3V;0201

R41380;0.5A;0201 12

JP41014/L8

2

C4148

4.7uF;20%;6.3V;0402

C4151

C4128

0.1uF;20%;6.3V;0201

R4145 0;0.5A;02011 2

R41430;0.5A;0201 12

C4123

0.1uF;20%;6.3V;0201

C4106

4.7uF;20%;6.3V;0402

R4106

0;0.5A;0201

1 2

R4121

0;0.5A;020112

TP4101

1

R41320;0.5A;020112

TP4110

1

C4138

18pF;10%;50V;0201

C4110

1.0UF;20%;6.3V;0201

R4107 0;0.5A;02011 2

C4113

4.7uF;20%;6.3V;0402

R4114

0;0.5A;0201

12

R41190;0.5A;0201 12

C4119

4.7uF;20%;6.3V;0402

TP4113

1

C4116

NF_27pF;10%;50V;0201

C4114

1.0UF;20%;6.3V;0201

R4144

0;0.5A;020112

GND-4PIN

J4103

BB2R4-24KBJ03

123456789

101112 13

1415161718192021222324

2526 27

28

C4105

4.7uF;20%;6.3V;0402

R4103 0;0.5A;02011 2

U4101

TS5MP646

VD

DA

1

GN

DA

2

DA4NA3

DA4PA4

OE A5

SEL A6

DB4NB1

DB4PB2

DA3NB3

DA3PB4

D4N B5

D4P B6

DB3NC1

DB3PC2

NC

1C

3

NC

2C

4

D3N C5

D3PC6

DB2ND1

DB2PD2

DA2ND3

DA2PD4

D2N D5

D2P D6

DB1NE1

DB1PE2

DA1NE3

DA1PE4

D1NE5

D1P E6

CLKBNF1

CLKBPF2

CLKANF3

CLKAPF4

CLKN F5

CLKP F6

C4121

NF_27pF;10%;50V;0201

C4117

0.1uF;20%;6.3V;0201

C4150

R41350;0.5A;0201 12

JP41034/L10

2

C4149

1.0UF;20%;6.3V;0201

TP4109

1

C4112

4.7uF;20%;6.3V;0402

R4140 0;0.5A;020112

C4126

NF_27pF;10%;50V;0201

C4132

NF_0201

R41410;0.5A;0201 12

GND4PIN

J4101

BAF04-30083-0500

123456789

101112131415 16

1718192021222324252627282930

3132 34

33

TP4111

1

C4102

NF_27pF;10%;50V;0201

GND-4PIN

J4102

BB2R4-24KBJ03

123456789

101112 13

1415161718192021222324

2526 27

28

C4118

NF_0201

R4146 NF_0;0.5A;020112R4118

0;0.5A;0201

12

JP41044/L10

2

R4109

0;0.5A;0201

1 2

R41160;0.5A;0201 12

TP4112

1

R41330;0.5A;020112

C4101

4.7uF;20%;6.3V;0402

R41360;0.5A;020112

R41370;0.5A;0201 12

TP4102

1

TP4103

1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LED_DRIVER

FLASH_DRIVERIR_LED

FLASH_LED1 [18]

RED_LED [18]

IRTX_OUT[3]

VPH_PWR[13,14,15,16,18,19,20,21,37,40,43,44,62,67,75]

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Design Name = S88512AA1_1_21_20190515_1605

R4202100K;5%;0201LED4201

LED-2+

12

R4201

6.8;1%;0805

D420219-217UTD/S3393/TR8(UN)

12

TVS4202NF_LESD8D5.0CT5GN

11

N2

2

Q4201WNM2046-3/TR1

2

3

C42011.0UF;20%;6.3V;0201

21


11

N2

2


11

N2

2

R4203

0;0.5A;0201

D4201IR26-61C/L510/R/2G(MI)

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FP LDO 3.0V

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,44,62,67,75] FP_TP_VDD3P0 [40,48]

FP_LDO_EN[3]

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Design Name = S88512AA1_1_21_20190515_1605

U4301


OUT1

GND12

EN3

IN4

GND25

R4301100K;5%;0201

C43091.0uF;20%;6.3V;0201

C43081.0uF;20%;6.3V;0201

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ACCELEROMETER

Magnetic Sensor

A+G SENSOR

ALP-SENSOR

SNS_I3C_SCL[3,44]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]SNS_I3C_SDA[3,44]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

ACCEL_INT[3]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

SNS_I3C_SDA[3,44]

SNS_I3C_SCL[3,44]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]SNS_I2C_SCL[3,61]

SNS_I2C_SDA[3,61]

ALSP_INT_N [3]

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,62,67,75]

GYRO_INT [3]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

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Design Name = S88512AA1_1_21_20190515_1605

L440233nH;3%;0201 1 2

C44114.7uF;20%;6.3V;0402

TP4403

1

C4410

0.1uF;20%;6.3V;0201

C4405

C0201_NC

C4404

2.2uF;20%;6.3V;0201

C4409

2.2uF;20%;6.3V;0201

C4406

C0201_NC

C4402

0.1uF;20%;6.3V;0201

R440310K;5%;0201

12

C4401

0.1uF;20%;6.3V;0201

TP4402

1

U4403

BMI120

SDO1

ASDX2

ASCX3

INT14

VD

DIO

5

GN

DIO

6

GN

D7

VDD8

INT29

GND110

GND211

CS

B12

SC

X13

SD

X14

GND-4PIN

J4401

BB2R4-10KBJ13

12345 6

78910

1112 13

14

L440133nH;3%;0201 1 2

U4402

AK09918C

VSSA1

SCLA2

VDDB1

SDAB2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

STATUS WITH SWITCH PININ OUT

H L

UIM1_DATA [3]UIM1_CLK[3]

UIM1_RESET[3]

UIM2_CLK[3]

UIM2_RESET[3]

SDC2_CMD[2]

SDC2_DATA_2[2]SDC2_DATA_3[2]

SDC2_DATA_1[2]

UIM2_DATA [3]

VREG_L22A_2P96[15]

SDC2_DATA_0[2]

SDC2_CLK[2]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,47,60,61,62,75,77]

VREG_L20A_1P8[8,15,45]

VREG_L19A_1P8[8,15,45]

UIM1_PRESENT [3]

SWITCH_DET[45]

SWITCH_DET[45]

UIM2_PRESENT [3]

SD_CARD_DET_N [3]

VREG_L19A_1P8 [8,15,45]

VREG_L20A_1P8 [8,15,45]

VREG_L5A_2P96[8,15]

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Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

R4526

1K;5%;0201

1 2

R4505 100;5%;0201

TVS4504LESD8D5.0CT5GN

11

N2

2

R4507 NF_100K;5%;0201


11

N2

2

R4511 33;5%;0201

C4502

1.0UF;20%;6.3V;0201

R4506 47;5%;0201

R452815K;5%;0201

12

R4509 33;5%;0201


11

N2

2

R4501 2.2;1%;0201

R4527

1K;5%;0201

1 2

C45034.7uF;20%;6.3V;0402

R4513 33;5%;0201R4514 33;5%;0201

SIM-A

SIM-B

T-F

J4501

SIM-T-CAF00-20137-1029

DAT2P1

CT/DAT3P2

CMDP3

VDDP4

CLKP5

VSSP6

DAT0P7

DAT1P8

GNDG1

GNDG2

GNDG3

GNDG4

GNDG5

GNDG6

GNDG7

GNDG8

GNDG9

GNDG10

GNDG11

GNDG12

VCC-SIMAAC11

RST-SIMAAC21

VCC-SIMBBC11

RST-SIMBBC21

CLK-SIMBBC31

DET_LEVERA1

GNDAC51

VPP-SIMAAC61

I/O-SIMAAC71

GNDBC51

VPP-SIMBBC61

I/O-SIMBBC71

DET_SWA2

VCC1-SIMAAC12

RST1-SIMAAC22

CLK-SIMAAC31

CLK1-SIMAAC32

GNDAC52

VPP1-SIMAAC62

I/O1-SIMAAC72

GNDBC52

VCC1-SIMBBC12

RST1-SIMBBC22

VPP1-SIMBBC62

CLK1-SIMBBC32

I/O1-SIMBBC72

VCC2-SIMAAC13

RST2-SIMAAC23

CLK2-SIMAAC33

GNDAC53

VPP2-SIMAAC63

I/O2-SIMAAC73

GNDBC53

VCC2-SIMBBC13

RST2-SIMBBC23

VPP2-SIMBBC63

I/O2-SIMBBC73

CLK2-SIMBBC33

R4510 33;5%;0201

R452915K;5%;0201

12

R4508

100;5%;0201

R4515

1K;5%;0201

1 2

R4503 47;5%;0201

R4516 100;5%;0201

C4501

1.0UF;20%;6.3V;0201

R4521100K;1%;0201

12

R4504 100;5%;0201

R4502 2.2;1%;0201


11

N2

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power On

Volume Up

Volume Down

Keys

Schematic design notice of "75_PERI_KEYPAD" page.DO NOT put pull-up resistor on PWRKEY

Note 75-2:

Note 75-1:

Volume Up : HOME Key / GNDVolume Down : KPROW0/KPCOL0

DEBUG_KYPDPWR_N[47]

DEBUG_KEY_VOL_DOWN_N[47]

KYPD_VOLP_N[16]

DEBUG_KEY_VOL_UP_N[47]

KYPDPWR_N [16,17]

RESIN_N [16]

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Design Name = S88512AA1_1_21_20190515_1605

R4601 1K;5%;0201

R4603 1K;5%;0201

R4602 1K;5%;0201

D4601LESD8D5.0CT5GN

11

N2

2D4602LESD8D5.0CT5GN

11

N2

2

D4603LESD8D5.0CT5GN

11

N2

2

J4601

CONN-4P

1234

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

UART

USB KEYS TEST

JTAG CONNECTOR

GNDBATTERY

BB2BB1

RF2PMI2PMI1 RF1 WCNPMU

DEBUG_KEY_VOL_DOWN_N [46]

DEBUG_KEY_VOL_UP_N [46]

DBG_UART_RX[3]

DEBUG_KYPDPWR_N [46]

DBG_UART_TX[3]

VBATT[19,36]

JTAG_TRST_N[2]

JTAG_TCK[2]

JTAG_TDI[2]

JTAG_TDO[2]

JTAG_TMS[2]

BATT_THERM_CON[36]

BATT_ID_CON[36]

JTAG_SRST_N[2]

USB0_HS_DM[2,19,48]

USB0_HS_DP[2,19,48]

USB1_VBUS_CONN[48]

USB_ID[19,48] VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,60,61,62,75,77]

FORCED_USB_BOOT [3]

USB_CC2[19,48]

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Design Name = S88512AA1_1_21_20190515_1605

SNJ4701

SN-3x3mm

1

TP4715TP-1MM

1

FM4704Fiducial Mark

1

TP4728TP-1MM

1

C47010.01uF;10%;16V;0201

TP4708TP-1MM

1

TP4702TP-1MM

1 TP4717TP-1MM

1

TP4714TP-1MM

1

屏蔽罩

SH4715

Shielding-case

1

HOLE14PTH-1.6MM

1

TP4729TP-1MM

1

TP4709TP-1MM

1

C47020.01uF;10%;16V;0201

TP4703TP-1MM

1

TP4723

1

TP4726

1

TP4724TP-1MM

1

HOLE15PTH-1.6MM

1

屏蔽罩

SH4711

Shielding-case

1

TP4704TP-1MM

1

屏蔽罩

SH4716

Shielding-case

1

TP4722

1

R4701 1K;5%;0201

TP4718TP-1MM

1

TP4725TP-1MM

1

屏蔽罩

SH4701

Shielding-case

1

R47041K;5%;0201

TVS4702

N1

1N

22

R4702 1K;5%;0201 屏蔽罩

SH4712

Shielding-case

1

HOLE17PTH-1.6MM

1

TP4711TP-0.5MM

1

TP4730TP-1MM

1

屏蔽罩

SH4714

Shielding-case

1

TP4713TP-1MM

1

TVS4703

N1

1N

22

屏蔽罩

SH4713

Shielding-case

1

TP4721

1

FM4706Fiducial Mark

1

屏蔽罩

SH4702

Shielding-case

1

TP4720

1

FM4703Fiducial Mark

1

HOLE12PTH-1.6MM

1

R470310K;5%;0201

TVS4701ESD9X5VU-2/TR

21

TP4719TP-1MM

1

TP4727

1

FM4705Fiducial Mark

1

TVS4704ESD9X5VU-2/TR

21

TP4712TP-0.5MM

1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Sub Board Connector

OVP

USB1_VBUS_CONN[47,48] VBUS_USB_IN[19]

USB0_HS_DM[2,19,47]USB_ID [19,47]USB0_HS_DP[2,19,47]USB_CC2 [19,47]

SPK_P[37,48]

SPK_P [37,48]SPK_N[37,48]SPK_N [37,48]

AMIC1_INP_CON [38]AMIC1_INM_CON [38]

USB1_VBUS_CONN[47,48]

MIC_BIAS1 [20]

SAR_MianANT_CIN1[61]SAR_MianANT_CIN2[61]

LTE_VFE28[61,67,69]GRFC10[3]GRFC11[3]

FP_TP_VDD3P0[40,43]FP_SPI_MOSI[3]

GRFC13[3]FP_INT_N [3]FP_RST_N [3]FP_SPI_SCLK [3]FP_SPI_CS_N [3]FP_SPI_MISO [3]

Shielding case_Gnd [48]

Shielding case_Gnd[48]

ANT_DET [18]

SPK_VSENS_N [37]SPK_VSENS_P [37]

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Design Name = S88512AA1_1_21_20190515_1605

JP48074/L8

2

R48030;0.5A;0201

R480147K;5%;0201

C4801

33pf;30%;50V;0201

U4801

ET9540L

ENA1

OUT1A2

OUT2A3

GND1A4 FLAG

B1

OUT3B2

IN1B3

GND2B4

OVLOC1

IN2C2

IN3C3

GND3C4

C4802

0.1uF;20%;25V;0201

R4802NF_10K;5%;0201

GND4PIN

J4801

CONN-34P-2ROW-GND4P

123456789

1011121314151617 18

19202122232425262728293031323334

3536 37

38

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

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V10Page Name = 57_Reserved


DEPARTMENT = WINGTECH-SH DESIGNER = Linguijun

Design Name = S88512AA1_1_21_20190515_1605

Title

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Design Name = S88512AA1_1_21_20190515_1605





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SDR660_MSS_GND

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


SDR660 MSS &GND

Each QPHY pair shall be routed in a channel togetherisolated from other QPHY pairs with surrounding gnd

QPHY_ETDAC_TEST

NOTE:One dedicated RFFE bus is required for SDR660 debug purposes

QPHY_CLK_M[6]

QPHY_CLK_P[6]

QPHY_UL0_M[6]

QPHY_UL0_P[6]

QPHY_DL0_M[6]

QPHY_DL0_P[6]

QPHY_DL1_M[6]

QPHY_DL1_P[6]

QPHY_DL2_M[6]

QPHY_DL2_P[6]

RFFE1_CLK[3]

RF_CLK1 [16] RFFE1_DATA[3]

WMSS_RESET[3]

QLINK_ENABLE [3]

QLINK_REQUEST [3]

GNSS_ELNA_CTRL [79]

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Design Name = S88512AA1_1_21_20190515_1605

R5801

0;0.5A;0201

1 2

QLINK_ETDAC_TEST

U5801DSDR660-0-180WLPSP-TR-03-0

GND_11

GND_49

GND_50115

GND_52124

GND_48106

GND_3891

QLINK_CLK_M81

QLINK_CLK_P96

QLINK_UL0_M87

QLINK_UL0_P72

QLINK_DL0_M88

QLINK_DL0_P103

QLINK_DL1_M111

QLINK_DL1_P127

QLINK_DL2_M135

QLINK_DL2_P119

ETDAC_CH0_M47

ETDAC_CH0_P39

ETDAC_CH1_M113

ETDAC_CH1_P104

CONTROL

U5801A

SDR660-0-180WLPSP-TR-03-0

XO_IN114

W_GRFC_6120

W_GRFC_7157

W_GRFC_5136

DNC_2165

QLINK_EN143

QLINK_REQ73

GNSS_ELNA_CTRL150

DNC_166

RFFE1_CLK166

RFFE1_DATA149

DNC_3173

WMSS_RESETN83

W_GRFC_057

W_GRFC_165

W_GRFC_274

GND

U5801B


GND_4499

GND_2449

GND_2958

GND_3267

GND_3684

GND_4398

GND_3789

GND_66158

GND_58138

GND_51116

GND_3061

GND_1634

GND_1840

GND_55129

GND_47105

GND_49109

GND_53125

GND_60140

GND_65155

GND_69163

GND_70172

GND_512

GND_719

GND_2348

GND_1328

GND_820

GND_72175

GND_67160

GND_64153

GND_45100

GND_24

GND_71174

GND_2755

GND_73180

GND_38

GND_1941

GND_921

GND_1022

GND_1736

GND_2042

GND_2856

GND_4297

GND_54128

GND_57134

GND_56131

GND_59139

GND_3992

GND_1430

GND_3579

GND_3162

GND_2245

GND_1531

GND_1224

GND_617

GND_1123

GND_61145

GND_63151

GND_2551

GND_3376

GND_2652

GND_62147

GND_68162

GND_3478

GND_4093

GND_2144

GND_4194

GND_46102

R5802

0;0.5A;0201

1 2

C5801NF

R5803

0;0.5A;0201

1 2





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SDR660_PRX_DRX_FBRX

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


a. DA outputs have no DC bias and they are DC grounded on chip.b. If following component (switch/PA) requires non-zero DC, then a series DC blocking cap is neededc. NC for unused LNA and DA Port

SDR660 Tx,PRX,DRX,FBRXRF_B41_DRX_RFIC[73]

RF_B40B41_PRX_RFIC [67]

RF_2G_LB_TX_RFIC [62]

RF_LTE_LB_TX_RFIC [67]

RF_2G_HB_TX_RFIC [62]

RF_MB2_TX_RFIC [67]

RF_HB2_TX_RFIC [67]

RF_B5_PRX_RFIC [64]

RF_B20_PRX_RFIC [64]

RF_B28B_PRX_RFIC [64]

RF_B28A_PRX_RFIC [64]

RF_TXDET[62]

RF_B20_DRX_RFIC[72]

RF_B28_DRX_RFIC[72]

RF_B7_DRX_RFIC[73]

RF_B40_DRX_RFIC[73]

RF_B39_DRX_RFIC[72]

RF_B34_DRX_RFIC[72]

RF_B2_DRX_RFIC[72]

RF_B8_DRX_RFIC[72]

RF_B5_DRX_RFIC[72]

WTR_GPS[79]

RF_B7_PRX_RFIC [65]

RF_B3_PRX_RFIC [65]


RF_B2_PRX_RFIC [65]

RF_B8_PRX_RFIC [64]

RF_B1_PRX_RFIC [65]

RF_B1B4_DRX_RFIC[72]

RF_B3_DRX_RFIC[72]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

59 81

V10Page Name = 59_SDR660_PRX_DRX_FBRX



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

59 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

59 81




Design Name = S88512AA1_1_21_20190515_1605

R5902

0;0.5A;0201

1 2

C5907

22pF;5%;50V;0201

L5930

15nH;3%;0201

C5912

22pF;5%;50V;0201

C5953 33pF;5%;50V;0201

C5916

22pF;5%;50V;0201

C590622pF;5%;50V;0201

C5975

22pF;5%;50V;0201

C596422pF;5%;50V;0201

C5921

22pF;5%;50V;0201

C5952

33pF;5%;50V;0201

C595033pF;5%;50V;0201

L5903

1.2nH;0.1nH;0201

C592622pF;5%;50V;0201

C590822pF;5%;50V;0201

C596722pF;5%;50V;0201

R5901

0;0.5A;0201

1 2

C5971

22pF;5%;50V;0201

L5932

15nH;3%;0201

R5908

0;0.5A;0201

1 2

RF

U5801E


DRX_HB1141

DRX_HB2133

DRX_HB3126

DRX_HB4117

DRX_UHB110

DRX_MB1171

DRX_MB2164

DRX_MB3156

DRX_MB4148

DRX_LB1179

DRX_LB2170

DRX_LB3178

DRX_LB4169

DRX_LB5177

DRX_LTEU_UHB101

TX_FBRX_M68

TX_FBRX_P60

GNSS_IN161

PRX_HB146

PRX_HB254

PRX_HB363

PRX_HB471

PRX_UHB80

PRX_MB116

PRX_MB225

PRX_MB332

PRX_MB438

PRX_LB17

PRX_LB215

PRX_LB36

PRX_LB414

PRX_LB55

PRX_LTEU_UHB86

TX_CH0_HB126

TX_CH0_MB133

TX_CH0_MB210

TX_CH0_LMB18

TX_CH0_LB12

TX_CH0_LB227

TX_CH1_UHB168

TX_CH1_HB167

TX_CH1_MB159

TX_CH1_LTEU176

L5927

15nH;3%;0201

L5909

1.2nH;0.1nH;0201

C594733pF;5%;50V;0201

L5938

1.2nH;0.1nH;0201

C5948

33pF;5%;50V;0201

C594233pF;5%;50V;0201

C594433pF;5%;50V;0201

L5901

1.2nH;0.1nH;0201

C5969

22pF;5%;50V;0201

C595833pF;5%;50V;0201

C5905

22pF;5%;50V;0201

U5902SAFFB1G56KB0F0A

UNBL11

GN

D1

2

GN

D2

3

UNBL24

GN

D3

5

C597422pF;5%;50V;0201

C5919

22pF;5%;50V;0201

C5938

33pF;5%;50V;0201

R59070;0.5A;0201

12

L5918

1.2nH;0.1nH;0201

C5904

22pF;5%;50V;0201

C5954

33pF;5%;50V;0201

C592922pF;5%;50V;0201

C597322pF;5%;50V;0201

C596133pF;5%;50V;0201

L5926

1.2nH;0.1nH;0201

L5904

1.2nH;0.1nH;0201

L5913

1.2nH;0.1nH;0201

C5901

22pF;5%;50V;0201

C595733pF;5%;50V;0201

C595533pF;5%;50V;0201

C5970

22pF;5%;50V;0201

C593933pF;5%;50V;0201

C5968

22pF;5%;50V;0201

L5933

15nH;3%;0201

R5903

49.9;1%;0201

L5936

3.3nH;0.1nH;0201

R5904

0;0.5A;02011 2

C595633pF;5%;50V;0201

L59372.4nH;0.1nH;0201

L5934

15nH;3%;0201

C5951 33pF;5%;50V;0201

L5923

1.2nH;0.1nH;0201

C5960

33pF;5%;50V;0201

L5931

15nH;3%;0201

C596522pF;5%;50V;0201

C597633pF;5%;50V;0201

L5925

15nH;3%;0201

C5972

22pF;5%;50V;0201

C596322pF;5%;50V;0201

R5905NF

12

C594033pF;5%;50V;0201

C5909

22pF;5%;50V;0201

R5906NF

12

C5903

22pF;5%;50V;0201

L5917

1.2nH;0.1nH;0201

C596222pF;5%;50V;0201

C5917

22pF;5%;50V;0201

C5946

33pF;5%;50V;0201

L5914

1.2nH;0.1nH;0201

C5977

22pF;5%;50V;0201

L5919

1.2nH;0.1nH;0201

L592915nH;3%;0201

C593322pF;5%;50V;0201

C592222pF;5%;50V;0201

L5910

1.2nH;0.1nH;0201

C5914

22pF;5%;50V;0201

C5943

33pF;5%;50V;0201

C596622pF;5%;50V;0201

C591022pF;5%;50V;0201

C5959

33pF;5%;50V;0201

C594133pF;5%;50V;0201

C594933pF;5%;50V;0201

C590222pF;5%;50V;0201

R59090;0.5A;0201

12

L5935

15nH;3%;0201

C5911

22pF;5%;50V;0201

C592522pF;5%;50V;0201

L5906

1.2nH;0.1nH;0201

C5945

33pF;5%;50V;0201

C5928

22pF;5%;50V;0201





LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

SDR660_PWR

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


SDR660 POWER

Pin 152,121,122within one group

VDD_DIG_1P0

VDD_ANALOG_1P2

VDD_DIG_1P8

Pin 43,37,107within one group

VREG_L1A_1P2[15]

VREG_L2A_1P0 [15]

VREG_L3A_1P0[15]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,61,62,75,77]

VREG_L13A_1P8 [15]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

60 81

V10Page Name = 60_SDR660_PWR



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

60 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

60 81




Design Name = S88512AA1_1_21_20190515_1605

PWR

U5801C


VDDA_1P0_RX177

VDDA_1P0_RX237

VDDA_1P0_RX243

VDDA_1P0_RX95

VDDA_1P0_RX2_153

VDDA_1P0_TX1144

VDDA_1P0_RX0154

VDDA_1P0_GNSS146

VDDA_1P0_TX0_113

VDDA_1P0_TX03

VDDA_1P0_RX0_1132

VDDA_1P8_TX1152

VDDA_1P8_ANA2121

VDDA_1P8_TX011

VDDA_1P8_ANA135

VDDA_1P8_ANA2122

VDDA_1P8_RX269

VDDA_1P8_FBRX50

VDDA_1P8_FBRX59

VDDA_1P2_RX270

VDDA_1P2_ANA075

VDDA_1P2_ANA090

VDDA_1P2_FBRX85

VDDA_1P2_TX029

VDDA_1P2_RX1108

VDDA_1P2_RX0130

VDDA_1P2_RX0137

VDDA_1P2_RX0_1123

VDDA_1P0_XO107

VDDD_1P0_QLINK118

VDDD_1P064

VDDD_1P082

VDDD_1P0142

VDDD_1P8112

R6004

0;0.5A;0201

1 2

SH6007

R6002

0;0.5A;0201

1 2

C60220.1uF;20%;6.3V;0201

C60030.1uF;20%;6.3V;0201

SH6010

SH6014

C60190.1uF;20%;6.3V;0201

C60010.1uF;20%;6.3V;0201

C60140.1uF;20%;6.3V;0201

C6002

4.7uF;20%;6.3V;0402

SH6012

C60130.1uF;20%;6.3V;0201

R6003

0;0.5A;0201

1 2

C60090.1uF;20%;6.3V;0201

C60150.1uF;20%;6.3V;0201

C60060.1uF;20%;6.3V;0201

C60180.1uF;20%;6.3V;0201

C60054.7uF;20%;6.3V;0402

SH6001

SH6013

C60100.1uF;20%;6.3V;0201

C60204.7uF;20%;6.3V;0402

C60164.7uF;20%;6.3V;0402

R6001

0;0.5A;0201

1 2

SH6002

SH6005

SH6003

C60080.1uF;20%;6.3V;0201

C60040.1uF;20%;6.3V;0201

C60070.1uF;20%;6.3V;0201

C60110.1uF;20%;6.3V;0201

SH6004

SH6006

C60214.7uF;20%;6.3V;0402

C60170.1uF;20%;6.3V;0201

SH6011

R6005

0;0.5A;02011 2

SH6009

C60120.1uF;20%;6.3V;0201

SH6015

SH6008

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

I2C需要1.8V上拉

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

SAR_MianANT_CIN2 [48]

SNS_I2C_SCL[3,44]

SNS_I2C_SDA[3,44]SAR_MianANT_CIN1 [48]

SAR_INT_GRFC0[3]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

SAR_DIV_CIN0 [69]

GRFC_ANT_DET [3]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75,77]

RF_Main [62]

LTE_VFE28[48,67,69]

ANT_DET[18]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

D

61 81

V10Page Name = 61_Primary_ANT



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

D

61 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

D

61 81




Design Name = S88512AA1_1_21_20190515_1605

R6110

0;0.5A;0201

12

R61042.2K;5%;0201

12

L610568nH;5%;0201

R61061M;5%;0201

12

L610468nH;5%;0201

C6112

33pF;5%;50V;0201

C61010.1uF;20%;6.3V;0201

C61021.0UF;20%;6.3V;0201

C6108100pF;30%;50V;0201

L6107NF

R6102

470;5%;0201

J6102NF

IN1

OUT2

GN

D1

3G

ND

24

C6113

100pF;5%;50V;0201

R6107100K;5%;0201

12

L6106

68nH;5%;0201

R6103

470;5%;0201

C6110

33pF;5%;50V;0201

C6103C0201_NCR6101

470;5%;0201

R6111

0;0.5A;0201

1 2

C6104C0201_NC

J6101RF-ANT-SOCKET-818002131

GN

D3

1G

ND

13

GN

D2

4

I/O2

C6114100pF;5%;50V;0201

C6109

33pF;5%;50V;0201

R6108

0;1A;0402

1 2

U6101SX9325

SDAB1

NIRQB2

CS0A3

SCLA1

GNDA4

CS1B4

VDDA2

CS2B3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

2G_PAIN_HB

TO_HMLB_Primary-ANT

RC filter for Qorvo TXM RF5228R3312= 50 ohmC3310= 10 pF(This value should be optimized for both MIPI total C-Load and RC Filter Performance)

Reserved Shunt C for MIPI C-load Tuning Control the Total Capacitance to 25pF+-3pF

High pass filter for G8 Tx in G7 Rxband noise rejection

2G_PAIN_LB

RF_TXDET[59]VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,67,75]

RF_Main[61]

LTE_VMIPI [62,67,70]

RFFE2_DATA [3,67,70,75]

RFFE2_CLK [3,67,70,75]

RF_B5_TRX_TXM[64]

RF_B34_PRX_TXM[65]

RF_B20_TRX_TXM[64]

RF_B8_TRX_TXM[64]

RF_B28B_TRX_TXM[64]

RF_B28A_TRX_TXM[64]

RF_B1_TRX_TXM[65]

RF_2G_HB_TX_RFIC [59]RF_B2_TRX_TXM[65]

RF_B1B3B4_TRX_TXM[65]

RF_B7_TRX_TXM[65]

RF_2G_LB_TX_RFIC [59]

RF_B34B39_TX_TXM[67]

RF_B40_TRX_TXM[67]

RF_B41_TRX_TXM[67]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,75,77]

LTE_VMIPI [62,67,70]

RF_B39_PRX_TXM[65]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

D

62 81

V10Page Name = 62_Primary_ASM



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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D

62 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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Date:

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62 81




Design Name = S88512AA1_1_21_20190515_1605

R6202

0;0.5A;02011 2

C6202

100pF;30%;50V;0201

C6211

33pF;5%;50V;0201

L6201NF

R6209

100K;1%;0201

C62030.1uF;20%;6.3V;0201

R62110;0.5A;0201

1 2

L6202NF

C6204

0.1uF;20%;6.3V;0201

R6206

0;0.5A;0201

1 2

C6215

3.3pF;0.25pF;50V;0201

C6209NF_18pF

C62172.2uF;20%;6.3V;0201

C6216

3.3pF;0.25pF;50V;0201

L6204

9.1NH;3%;0201

C6210NA_18pF

R6210

0;0.5A;02011 2

R6208

0;0.5A;0201

C6212

1.8pF;0.05pF;50V;0201

C6206

100pF;5%;50V;0201

C6214

33pF;5%;50V;0201

D6201ESD5651N-2/TR

N1

1N

22

R6207

0;0.5A;0201

1 2

C62081000pF;20%;50V;0201

C62182.2uF;20%;6.3V;0201

R62030;0.5A;0201

1 2

C6213

1.8pF;0.05pF;50V;0201

R6204

0;0.5A;02011 2

C620122pF;5%;50V;0201

L6203

4.3nH;0.1nH;0201

U6201RF5212ATR13

RFIN_L_OUT1

RFIN_L2

RFIN_H3

RFIN_H_OUT4

SCLK5

SDATA6

VIO7

VRAMP8

VCC/VPA9

VBAT/VSW10

GN

D1

11G

ND

212

GN

D3

13G

ND

414

GN

D5

15G

ND

616

CP

L_O

UT

17

GN

D7

18

NC

19

GN

D8

20G

ND

921

ANT22

GN

D10

23

NC/GND124

NC/GND225

TRX1226

TRX1127

TRX1028

TRX929

TRX830

TRX

731

TRX

632

TRX

533

TRX

434

TRX

335

TRX

236

NC

/GN

D3

37G

ND

1138

GN

DP

139

GN

DP

240

GN

DP

341

GN

DP

442

GN

DP

543

GN

DP

644

GN

DP

745

GN

DP

846

GN

DP

947

VRAMP_1

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

63 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

63 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

63 81




Design Name = S88512AA1_1_21_20190515_1605

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

B8 DPXL

B28A DPXL

B28B DPXL

B5 DPXL

B20 DPXL

RF_B8_PRX_RFIC [59]

RF_B8_PA_DPX[67]

RF_B8_TRX_TXM[62]

RF_B5_PA_DPX[67]

RF_B5_TRX_TXM[62]

RF_B28A_TRX_TXM[62]

RF_B28B_PRX_RFIC [59]

RF_B28B_PA_DPX[67]

RF_B28B_TRX_TXM[62]

RF_B5_PRX_RFIC [59]

RF_B28A_PRX_RFIC [59]

RF_B28A_PA_DPX[67]

RF_B20_PA_DPX [67]

RF_B20_TRX_TXM [62]

RF_B20_PRX_RFIC [59]

Title

Size

DESIGNER:

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DOCUMENT NO.:

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Date:

D

64 81

V10Page Name = 64_TRX_LB



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

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64 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

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64 81




Design Name = S88512AA1_1_21_20190515_1605

C6405

33pF;5%;50V;0201

L6409NF

C6402

18pF;5%;50V;0201

C641118pF;5%;50V;0201

L640315nH;3%;0201

FL6401SAYEY836MBA0F0A

TX3

ANT6

GN

D1

2

GN

D2

4

GN

D3

5

RX1

GN

D4

7

GN

D5

8

L6415

NF

FL6405SAYEY733MBC0F0A

TX3

ANT6

GN

D1

2

GN

D2

4

GN

D3

5

RX1

GN

D4

7

GN

D5

8

L64088.2nH;3%;0201

L64138.2nH;3%;0201

L6418NF

L6407NF

L64118.2nH;3%;0201

L640412nH;3%;0201

L6420NF

L6419NF

FL6402SFX897BYF0W

TX3

ANT6

GN

D1

2

GN

D2

4

GN

D3

5

RX1

GN

D4

7

GN

D5

8

L6401

4.3nH;0.1nH;0201


TX3

ANT6

GN

D1

2

GN

D2

4

GN

D3

5

RX1

GN

D4

7

GN

D5

8

C6412

33pF;5%;50V;0201

L64168.2nH;3%;0201

L64128.2nH;3%;0201

C6408

18pF;5%;50V;0201


TX3

ANT6

GN

D1

2

GN

D2

4

GN

D3

5

RX1

GN

D4

7

GN

D5

8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

B7 DPXL

B34/39 PRX

B3/4B1

B1/4

B3

说明：国内、印度版使用双双工器；海外版使用四工器，两者做兼容。

B3439

B2 DPXL

RF_B7_PA_DPX[67]

RF_B7_TRX_TXM[62]

RF_B7_PRX_RFIC [59]

RF_B3_PA_DPX[67]

RF_B1_TRX_TXM[62]

RF_B1B3B4_TRX_TXM[62]

RF_B34_PRX_TXM [62]

RF_B3_PRX_RFIC [59]

RF_B1_PA_DPX[67]

RF_B34B39_PRX_RFIC[59]

RF_B1_PRX_RFIC [59]

RF_B39_PRX_TXM [62]

RF_B2_PA_DPX[67]

RF_B2_TRX_TXM[62]

RF_B2_PRX_RFIC [59]

Title

Size

DESIGNER:

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65 81

V10Page Name = 65_TRX_MHB



Design Name = S88512AA1_1_21_20190515_1605

Title

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Design Name = S88512AA1_1_21_20190515_1605

Title

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65 81




Design Name = S88512AA1_1_21_20190515_1605

L6508

1.0nH;0.1nH;0201

L6506NF

L6523

0.6nH;0.1nH;0201

L65154.3nH;0.1nH;0201

C6513

3.0pF;0.25pF;25V;0201

FL6533SFHG60KQ602-A

6 UNBL_IN

1G

ND

1

2G

ND

2

3UNBL2_OUT

4G

ND

3

5G

ND

4

L6530NF

C650633pF;5%;50V;0201

L6517NF

L65293.3nH;0.1nH;0201

L6509NF

L6524

3.3nH;0.1nH;0201

L6525NF

FL6509SFWG00DB002

B39 / B341

B399

GND12

GND23

GND34

B346

GND45

GND57

GND68

GND710

FL6504SAYEY1G88BA0B0AR05-A

TX 3ANT6

GN

D1

2

GN

D2

4

GN

D3

5

RX 1

GN

D4

7

GN

D5

8

GN

D6

9

L65322.0NH;0.1nH;0201

C6511

33pF;5%;50V;0201

C65012.7pF;0.25pF;50V;0201

L6520NF

L65312.0NH;0.1nH;0201

R6508

0;0.5A;0201

1 2

L650710nH;3%;0201

L6514NF

C6504

33pF;5%;50V;0201

L65196.2NH;3%;0201

L6510NF

FL6501rf-SAPRY1G74BA0B0A

B1_TX Port1

B3_TX Port12

B1_ANT. Port3

GN

D4

B3_

AN

T. P

ort1

5

B1_RX Port 6

B3_RX Port17G

ND

18

L6503NF

C6510

33pF;5%;50V;0201

FL6506

SAYEY2G53BC0F0AR05

TX3

ANT6

GN

D1

2

GN

D2

4

GN

D3

5

RX1

GN

D4

7

GN

D5

8

L6516NF

R6509

0;0.5A;0201

1 2

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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Date:

Custom

66 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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Date:

Custom

66 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

66 81




Design Name = S88512AA1_1_21_20190515_1605

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

B38/41(110M)TRX

B3 TX Phase3 LMH PA Pin20 is LB5

B40 TRX

B1 TX

B7 TXB38/40/41 PRX

B8 TX

B28A TX

LPF for moremargin on Txspurious

3/4G_PAIN_MB

3/4G_PAIN_HB

4G PA input need LPF for harmonic rejection

3/4G_PAIN_LB

B28B TX

B5/BC0 TX

B20 TX

B34/39 TX

Close to PA0

RF_B40_TRX_TXM[62]

RF_B3_PA_DPX[65]

RF_HB2_TX_RFIC [59]

RF_MB2_TX_RFIC [59]

RF_B8_PA_DPX[64]

RF_B7_PA_DPX[65]

RFFE2_CLK [3,62,70,75]

RF_B5_PA_DPX[64]

RF_LTE_LB_TX_RFIC [59]

RF_B1_PA_DPX[65]

RFFE2_DATA [3,62,70,75]

GRFC3 [3]

RF_B41_TRX_TXM[62]

RF_B28A_PA_DPX[64]

RF_B28B_PA_DPX[64]


LTE_VMIPI [62,70]

LTE_VFE28 [48,61,67,69]

VPH_PWR [13,14,15,16,18,19,20,21,37,40,42,43,44,62,75]

RF_B20_PA_DPX[64]

RF_B34B39_TX_TXM[62]

RF_B2_PA_DPX[65]

VPA_APT_CH0[75]

VREG_L21A_2P704[15] LTE_VFE28 [48,61,67,69]

PA_THERM0 [16]

Title

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67 81

V10Page Name = 67_RF_MMPA_RF_TX



Design Name = S88512AA1_1_21_20190515_1605

Title

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Design Name = S88512AA1_1_21_20190515_1605

Title

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DESIGNER:

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67 81




Design Name = S88512AA1_1_21_20190515_1605

R6704

0;0.5A;02011 2

L6715

2.2nH;0.1nH;0201

C671033pF;5%;50V;0201

L6721

3.3nH;0.1nH;0201

C67123.3pF;0.25pF;50V;0201

C67200.1uF;20%;6.3V;0201

L67281.8nH;0.1nH;0201

R6706

0;0.5A;02011 2

R6702

0;0.5A;02011 2

R6711

0;0.5A;02011 2

C6752100pF;5%;50V;0201

C67113.3pF;0.25pF;50V;0201

C6746

4.7uF;20%;6.3V;0402

C67141.8pF;0.05pF;50V;0201

C67480.1uF;20%;6.3V;0201

C67532.2uF;20%;6.3V;0201

L67047.5nH;3%;0201

L6711

9.1nH;3%;0201

L670110nH;3%;0201

C67032.4pF;0.25pF;25V;0201

L67082.0NH;0.1nH;0201

L67201.8nH;0.1nH;0201

R6715

0;0.5A;0201

L67122.0NH;0.1nH;0201

U6701QM56020TR13-5K

GND11GND22RFIN_H3NC14SDATA5SCLK6VIO7VBATT8

NC310NC411RFIN_M12RFIN_L113RFIN_L214GND315

LB4

16LB

317

LB2

18LB

119

LB5

20M

B1

21

GND422

MB223

GND524

MB325

MB426

GND627

VCC2_228

VCC129

VCC230

GND731

MB532

HB133

GND834

HB235

GND936

HB

337

GN

D10

38

HB

439

GN

D11

40

HB

RX

141

HB

RX

242

GN

D12

43

GN

D13

44

GN

D14

45

GN

D15

46

GN

D16

47

GN

D17

48

GN

D18

49

GN

D19

50

NC29

GN

D20

51G

ND

2152

L67067.5nH;3%;0201

C6713

33pF;5%;50V;0201

C67311.0pF;0.05pF;50V;0201

L67132.0NH;0.1nH;0201

C67082.4pF;0.25pF;25V;0201

C6744100pF;30%;50V;0201

FL6702F6FC2G600H4PA

UNBL11

GN

D1

2G

ND

23

UNBL24

GN

D3

5

C6721

100pF;5%;50V;0201

FL6704885075

UNBL11

GN

D1

2G

ND

23

UNBL24

GN

D3

5 L67241.8nH;0.1nH;0201

R6707

0;0.5A;02011 2

L6719NF_0201

L670510nH;3%;0201

C67042.4pF;0.25pF;25V;0201

C6729

8.2pF;0.25pF;50V;0201

D6702NF

N1

1N

22

R6708

0;0.5A;02011 2

D6701

ESD5651N-2/TR

N1

1N

22

L6727NF_0201

C67402.4pF;0.25pF;25V;0201

C67092.4pF;0.25pF;25V;0201

C6722NF_0201

C67182.4pF;0.25pF;25V;0201

L67252.2nH;0.1nH;0201

C67052.4pF;0.25pF;25V;0201

R6710

0;0.5A;02011 2FL6701

RFLPF10051G8DM1T76

NC

11

GN

D1

2

NC

23

OUTPUT PORT4

GN

D2

5

INPUT PORT6

R6703

0;0.5A;02011 2

L6716

3.3nH;0.1nH;0201

L67102.0NH;0.1nH;0201

C6728100pF;5%;50V;0201

L67072.0NH;0.1nH;0201

C6745

1.8pF;0.05pF;50V;0201

C6733

100pF;5%;50V;0201

L67261.8nH;0.1nH;0201

C67162.4pF;0.25pF;25V;0201

C67172.4pF;0.25pF;25V;0201

R6701

0;0.5A;02011 2

C6741

2.4pF;0.25pF;25V;0201

C6724

1000pF;20%;50V;0201

C6723NF_0201

L67092.0NH;0.1nH;0201

C673527pF;5%;50V;0201

R6705

0;0.5A;0201

1 2

C67072.4pF;0.25pF;25V;0201

L670310nH;3%;0201

C6743NF_0201

C67392.4pF;0.25pF;25V;0201

C67192.4pF;0.25pF;25V;0201

R6713

0;0.5A;02011 2

C670112pF;5%;50V;0201

U6703MXD8015H

GND11

VDD2

RFOUT3

GND24

RFIN5

EN6

L6714

4.3nH;0.1nH;0201

R6712

0;0.5A;02011 2

L67171.5nH;0.1nH;0201

C670212pF;5%;50V;0201

L6718NF_0201

L6723NF_0201

C67510.1uF;20%;6.3V;0201

C6734

1.8pF;0.05pF;50V;0201

L67027.5nH;3%;0201

C6742100pF;30%;50V;0201

C670612pF;2%;50V;0201

C673633pF;5%;50V;0201

C67301.0pF;0.05pF;50V;0201

RT6701100K;1%;0201

R6709

0;0.5A;0201

L6722NF_0201

C67371.8pF;0.05pF;50V;0201

C6715

1.8pF;0.05pF;50V;0201

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

check封装

RF_DRX [70]

LTE_VFE28 [48,61,67]

GRFC4 [3]

GRFC5 [3]

SAR_DIV_CIN0 [61]

Title

Size

DESIGNER:

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V10Page Name = 69_Diversity_ANT



Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

L690268nH;5%;0201

C6908100pF;5%;50V;0201

J6904CONN-4P

1234

J69014-00-45979

1

2

R69100;0.5A;0201

12

L6909

100nH;3%;0201

C6905

10PF;5%;50V;0201

L6903NF

R6903

0;0.5A;0201

1 2

J69034-00-45979

1

2

C690627pF;5%;50V;0201

C6907

100pF;5%;50V;0201

C6901

12pF;5%;50V;0201

C6903

10PF;5%;50V;0201

R69040;0.5A;0201

12

J69054-00-45979

1

2

J69064-00-45979

1

2

R69080;0.5A;0201

12

U6902

RF1694A

RF11

RF22

GND13

VDD4

CTL

15

CTL26

GND27

RF48

RF39

RFC

10

L6905NF

C6904

33pF;5%;50V;0201

C6902

10PF;5%;50V;0201

R6901

0;0.5A;0201

1 2

L6904NF

L6908

100nH;3%;0201

C6910

33pF;5%;50V;0201

R69070;0.5A;0201

12

C6909100pF;5%;50V;0201

R6905

0;0.5A;0201

12

R6911

0;1A;0402

1 2

J69074-00-45979

1

2

J6902MM8030-2610RK0

IN1

OUT2

GN

D1

3G

ND

24

R6909

0;0.5A;0201

1 2

R6906

0;0.5A;0201

12

L6901100nH;5%;0201

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RF_B8_DRX_ASM[72]

RF_DRX [69]

LTE_VMIPI [62,67]

RFFE2_DATA [3,62,67,75]

RFFE2_CLK [3,62,67,75]

RF_B20_DRX_ASM[72]

RF_B5_DRX_ASM[72]

RF_B28_DRX_ASM[72]

RF_B34_DRX_ASM[72]

RF_B39_DRX_ASM[72]

RF_B2_DRX_ASM[72]

RF_B40_DRX_ASM[73]

RF_B1_B4_DRX_ASM[72]

RF_B7_DRX_ASM[73]

RF_B41_DRX_ASM[73]

RF_B3_DRX_ASM[72]

Title

Size

DESIGNER:

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DOCUMENT NO.:

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70 81

V10Page Name = 70_Diversity ASM



Design Name = S88512AA1_1_21_20190515_1605

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Design Name = S88512AA1_1_21_20190515_1605

U7001D5352

GN

D1

SDATA2

SCLK 3

VIO 4

VDD 5

GN

D1

6

ANT 7

GN

D2

8

GN

D3

9

GN

D4

10

B111

B4012

AUX413

B4114

B315

AUX316

B3417

B3918

AUX219

AUX120

B821

B522

GN

DP

23

L70023.3nH;0.3nH;0201

C70050.01uF;10%;16V;0201

C7004

18pF;5%;50V;0201

C7003NF_0201

L70013.3nH;0.3nH;0201

C7001

15pF;5%;50V;0201

C7002

NF_0201

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

71 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

71 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

71 81




Design Name = S88512AA1_1_21_20190515_1605

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Band1/4

B28B20

B8

B5/BC0B2

B34

B3 B39

RF_B8_DRX_RFIC [59]RF_B8_DRX_ASM[70]

RF_B5_DRX_RFIC [59]

RF_B28_DRX_RFIC [59]

RF_B20_DRX_ASM[70]

RF_B5_DRX_ASM[70]

RF_B1_B4_DRX_ASM[70] RF_B1B4_DRX_RFIC [59]

RF_B34_DRX_ASM[70]


RF_B2_DRX_ASM [70]RF_B2_DRX_RFIC [59]

RF_B28_DRX_ASM[70]

RF_B3_DRX_RFIC [59]

RF_B39_DRX_ASM[70]

RF_B3_DRX_ASM[70]



Title

Size

DESIGNER:

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V10Page Name = 72_DRX_LMB



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Design Name = S88512AA1_1_21_20190515_1605

R7201

0;0.5A;0201

12

C7203

4.7pF;0.25pF;50V;0201

R72090;0.5A;0201

12

FL7206SAFFB806MAA0F0A

UNBL11

GN

D1

2

GN

D2

3

UNBL24

GN

D3

5

R7204

0;0.5A;0201

1 2

FL7203SAFFB1G96AB0F0A

UNBL11

GN

D1

2

GN

D2

3

UNBL24

GN

D3

5

R7202

0;0.5A;0201

1 2

L72093.3nH;0.3nH;0201

R72100;0.5A;0201

12

L72153.3nH;0.3nH;0201

L7201

2.2nH;0.1nH;0201

L7217

3.9nH;0.1nH;0201

C7211100pF;5%;50V;0201

L72113.3nH;0.3nH;0201

FL7204SAFFB806MAA0F0A

UNBL11

GN

D1

2

GN

D2

3

UNBL24

GN

D3

5

L7227

6.2nH;0.1nH;0201

L7222

12nH;3%;0201

R7205

0;0.5A;0201

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

B7

B40

B38/41

RF_B7_DRX_ASM[70]

RF_B40_DRX_ASM[70] RF_B40_DRX_RFIC [59]

RF_B41_DRX_ASM[70]

RF_B7_DRX_RFIC [59]


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

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Date:

D

73 81

V10Page Name = 73_DRX_HB



Design Name = S88512AA1_1_21_20190515_1605

Title

Size

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73 81




Design Name = S88512AA1_1_21_20190515_1605

Title

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73 81




Design Name = S88512AA1_1_21_20190515_1605

L7307

2.4nH;0.1nH;0201

C7301

10PF;5%;50V;0201

FL7301SFHG56BA002

UNBL11

GN

D1

2

GN

D2

3

UNBL24

GN

D3

5

C7304

10PF;5%;50V;0201

L7302NF_0201

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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Date:

Custom

74 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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Custom

74 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

74 81




Design Name = S88512AA1_1_21_20190515_1605

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AQPOET

VDD_DIG_1P8

VPH_PWR[13,14,15,16,18,19,20,21,37,40,42,43,44,62,67]

VPA_APT_CH0[67]

VREG_L9A_1P8[3,8,12,15,16,17,20,37,44,45,47,60,61,62,77]

RFFE2_DATA [3,62,67,70]

RFFE2_CLK [3,62,67,70]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

D

75 81

V1.075_ET_APT

Wednesday, May 15, 2019

SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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D

75 81

V1.075_ET_APT


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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D

75 81

V1.075_ET_APT


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

C75024.7uF;20%;6.3V;0402

C750410uF;20%;6.3V;0402

QET4101

U7501QET4101-0-12WLNSP-TR-00-0

VDD_BATT1

DNC29

DNC110

VSW11

VOUT_LDO5

GND7

VBAT_SW12

VDD_1P84

USID6

SDATA2

SCLK3

GND_SW8

C75011.0UF;20%;6.3V;0201

l7501

1.0UH;20%;2520

C75051.0UF;20%;6.3V;0201

C750333pF;5%;50V;0201

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

76 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

76 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

76 81




Design Name = S88512AA1_1_21_20190515_1605

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

WCN3950

WL_CMD_CLK[6]

WLAN_BT_RFIO_2G_CH0 [78]

WL_CMD_DATA[6]

WLAN_RFIO_5G [78]

WL_Tx_BB_Q_N[6]

WL_Tx_BB_Q_P[6]

WL_Tx_BB_I_N[6]

WL_Tx_BB_I_P[6]

SLEEP_CLK[2,16]

WL_Rx_BB_Q_N[6]

WL_Rx_BB_Q_P[6]

WL_Rx_BB_I_N[6]

RF_CLK2 [16]

WL_Rx_BB_I_P[6]

VREG_L17A_1P304 [9,15]

FM_ANT[39]

VREG_L9A_1P8 [3,8,12,15,16,17,20,37,44,45,47,60,61,62,75]

VREG_L16A_1P8[9,15,79]

VREG_L23A_3P304 [15,78]

WCN_UART_CTS_N[3]

WCN_UART_RFR_N[3]

WCN_UART_RX_N[3]

WCN_UART_TX_N[3]

WCN_SW_CTRL[3]

QCA_SB_DATA[3]

QCA_SB_CLK[3]

WLAN_BT_COEX_CLK[6]

WLAN_BT_COEX_DATA[6]

MSS_LTE_COXM_RXD[3]

MSS_LTE_COXM_TXD[3]

XPST_CTRL [78]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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Date:

D

77 81

V1.077_WCN_IC


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

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D

77 81

V1.077_WCN_IC


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

D

77 81

V1.077_WCN_IC


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

C77134.7uF;20%;10V;0402

C7714

0.01uF;10%;16V;0201

C7709

0.01uF;10%;16V;0201

C7716

10pF;2%;50V;0201

C772010uF;20%;6.3V;0402

C77022.2uF;20%;6.3V;0201

C7717

1.0UF;20%;6.3V;0201

R7701

0;0.5A;0201

C7722

2.2pF;0.25pF;50V;0201

L7703

68nH;5%;0201

C7704

0.47UF;20%;6.3V;0201

C7706

10PF;5%;50V;0201

C7715

0.01uF;10%;16V;0201

C7701

1000pF;20%;50V;0201

C77084.7uF;20%;10V;0402

C77120.47UF;20%;6.3V;0201

MFG_NO

U7701

WL_CMD_CLK1

COEX_CLK2

CTS3

VDD33_WL_BT_2G_DRV_PM_LDO4

GND_WL_BT_2G_RXFE5

VDD18_IO6

WL_CMD_DATA7

COEX_DATA8

GND_PMU9

GND_BT_DA10

WL_BT_RFIO_2G11

SB_CLK12

LF_CLK_IN13

RXD14

GND_WL_BT_DRV15

VDD11D_PM16

GND_DIG_IO17

TXD18

RTS19

GND_WL_BT_2G_PA20

VDD33_WL_PA21

SB_DATA22

COEX_TXD23

COEX_RXD24

VDD33_WL_5G_DRV25

GND_WL_5G_BALUN26

VDD13_PM27

SW_CTRL28

GND_ISO29

VDD13_WL_BT_GPS30

GND_WL_5G_PA31

WL_RFIO_5G32

VDD18_XTAL33

GND_WL_BT_SYNTH_XTAL34

GP_EN35

GND_WL_5G_DRV36

GND_WL_5G_RXFE37

CLK_IN38

WL_BB_QP_RX39

GND_WL_BT_BB40

GND_WL_DPD41

GND_SEALRING142

GND_BT_FM_BBPLL_A43

WL_BB_QN_RX44

WL_BB_IN_RX45

WL_BB_IP_RX46

GND_GPS47

VDD13_BT_FM_BBPLL_A48

GND_FM_VCO49

WL_BB_QN_TX50

WL_BB_IP_TX51

GP_OUT52

GP_IN53

VDD13_FM54

WL_BB_QP_TX55

WL_BB_IN_TX56

GND_FM_RXFE57

FM_RX_HEADSET58

C7707

0.01uF;10%;16V;0201

C7723

2.2pF;0.25pF;50V;0201

C77052.2uF;20%;10V;0201

C7719

4.7uF;20%;10V;0402

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

WLAN_RFIO_5G [77]

WLAN_BT_RFIO_2G_CH0 [77]

GPS_IN [79]

VREG_L23A_3P304 [15,77]

XPST_CTRL [77]

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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D

78 81

V1.078_WIFI


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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D

78 81

V1.078_WIFI


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

D

78 81

V1.078_WIFI


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

U7801MXD8721

RF11

GND2

RF23

V24

ANT5

V16

L7804NF_0201

FL7801DP1005-A2455EAT/LF

GND3

COMMON4

H-PORT1

L-PORT2

FL7802F6HG2G441EG65

UNBL11

GN

D1

2G

ND

23

UNBL24

GN

D3

5

R7809

0;0.5A;0201

L78103.3nH;0.3nH;0201

J7808

4-00-459791

2

L780512NH;3%;0201

J7802MM8030-2610RK0

IN1

OUT2

GN

D1

3G

ND

24

R7803

0;0.5A;0201

L78093.3nH;0.3nH;0201

J7804

4-00-459791

2

L780612NH;3%;0201

R7810

0;0.5A;0201

R7807

0;0.5A;0201

R7811

0;0.5A;0201

L78113.3nH;0.3nH;0201

C780218pF;10%;50V;0201

L7813NF_0201

J78064-00-45979

1

2

L78074.7nH;0.1nH;0201

R7815NF_0201

R7804

0;0.5A;0201

L7815NF

J7805

4-00-459791

2

C7807

18pF;5%;50V;0201

L7812NF_0201

J7803

4-00-459791

2

J78014-00-45979

1

2

R7814NF_0201

R7805

0;0.5A;0201

C7801

4.7pF;0.25pF;50V;0201

L78083.3nH;0.3nH;0201

C7806

18pF;10%;50V;0201

C7804

4.7pF;0.25pF;50V;0201

R7802

0;0.5A;0201

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AGNSS

F6QA1G582H2JMQJS high attenuation SAW is required for saw +glna solution.

VREG_L13A_1P8[9,15,77]

WTR_GPS[59]

GPS_IN [78]

GNSS_ELNA_CTRL [58]

Title

Size

DESIGNER:

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DOCUMENT NO.:

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79 81

V1.079_GPS


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

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79 81

V1.079_GPS


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

Title

Size

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79 81

V1.079_GPS


SH-HW Liufenglei

S88512AA1_1_21_20190515_1605

C7906

100pF;30%;50V;0201

R7902

0;0.5A;0201

L79028.2nH;3%;0201

U7901AW5005DNR

GND11

GND22

RFIN3

VCC4

EN5

RFOUT6

C79031.0pF;0.05pF;50V;0201

C7904

3.9pF;0.05pF;50V;0201

R7906

0;0.5A;0201

FL7903SAFFB1G56KB0F0A

UNBL11

GN

D1

2

GN

D2

3

UNBL24

GN

D3

5

C7901

15pF;5%;50V;0201

L7901

8.2nH;3%;0201

C7902

3.9pF;0.05pF;50V;0201

L7903NF_0201

L79048.2nH;3%;0201

R7905

0;0.5A;0201

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

80 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

80 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

80 81




Design Name = S88512AA1_1_21_20190515_1605

LAST_EDITOR1 2-23-2007_10:06

A INITIAL RELEASE

APPROVED

14 35

DESCRIPTIONLTR

REVISIONS

6

DATE

28 7

A

B

C

D

A

B

C

D

EDITED BYVERSION


Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

REV:

Date:

Custom

81 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

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81 81




Design Name = S88512AA1_1_21_20190515_1605

Title

Size

DESIGNER:

Sheet of

DOCUMENT NO.:

DEPARTMENT:

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81 81




Design Name = S88512AA1_1_21_20190515_1605

Title REV: TABLE OF CONTENTS Date...WCN_SW _CTRL [77] S DCARD ET_N [45] USB_P HY_PS [19] WMSS_RES ET...

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Transcript of Title REV: TABLE OF CONTENTS Date...WCN_SW _CTRL [77] S DCARD ET_N [45] USB_P HY_PS [19] WMSS_RES ET...