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Measuring Terminal Capacitanceand Its Voltage Dependency forHigh-Voltage Power Devices

Funaki, Tsuyoshi; Phankong, Nathabhat; Kimoto,Tsunenobu; Hikihara, Takashi

Funaki, Tsuyoshi ...[et al]. Measuring Terminal Capacitance and Its Voltage Dependencyfor High-Voltage Power Devices. IEEE TRANSACTIONS ON POWER ELECTRONICS 2009,24(5-6): 1486-1493

2009-05

http://hdl.handle.net/2433/109805

© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material foradvertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, orto reuse any copyrighted component of this work in other works must be obtained from the IEEE.

1486 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 6, JUNE 2009

Measuring Terminal Capacitance and Its VoltageDependency for High-Voltage Power DevicesTsuyoshi Funaki, Member, IEEE, Nathabhat Phankong, Tsunenobu Kimoto, Senior Member, IEEE,

and Takashi Hikihara, Member, IEEE

Abstract—The switching behavior of semiconductor devices re-sponds to charge/discharge phenomenon of terminal capacitance inthe device. The differential capacitance in a semiconductor devicevaries with the applied voltage in accordance with the depleted re-gion thickness. This study develops a C–V characterization systemfor high-voltage power transistors (e.g., MOSFET, insulated gatebipolar transistor, and JFET), which realizes the selective measure-ment of a specified capacitance from among several capacitancesintegrated in one device. Three capacitances between terminalsare evaluated to specify device characteristics—the capacitancefor gate–source, gate–drain, and drain–source. The input, output,and reverse transfer capacitance are also evaluated to assess theswitching behavior of the power transistor in the circuit. Thus,this paper discusses the five specifications of a C–V characteriza-tion system and its measurement results. Moreover, the developedC–V characterization system enables measurement of the tran-sistor capacitances from its blocking condition to the conductingcondition with a varying gate bias voltage. The measured C–Vcharacteristics show intricate changes in the low-bias-voltage re-gion, which reflect the device structure. The monotonic capacitancechange in the high-voltage region is attributable to the expansionof the depletion region in the drift region. These results help tounderstand the dynamic behavior of high-power devices duringswitching operation.

Index Terms—C–V characteristics, high-voltage power device,terminal capacitance, voltage dependency.

I. INTRODUCTION

POWER electronics requires high efficiency and versatilepower conversion. High-voltage capability is preferable,

especially in high-power circuits, to reduce the conduction loss

Manuscript received October 1, 2008; revised February 21, 2009. Currentversion published May 29, 2009. This work was supported in part by the Min-istry of Education, Culture, Sports, Sciences and Technology in Japan, underGrant-in-Aid for Scientific Research 17686024, Grant 18360137, and the 21stCentury Centers of Excellence (COE) Program 14213201. Recommended forpublication by Associate Editor J. Shen.

T. Funaki is with the Division of Electrical, Electronic and Information En-gineering, Graduate School of Engineering, Osaka University, Suita 565-0871,Japan (e-mail: [email protected]).

N. Phankong is with the Department of Electrical Engineering, Grad-uate School of Engineering, Kyoto University, Kyoto 615-8510, Japan,and also with the Department of Electrical Engineering, Rajamangala Uni-versity of Technology Thanyaburi, Thanyaburi 12110, Thailand (e-mail:[email protected]).

T. Kimoto is with the Department of Electronic Science and Engineering,Graduate School of Engineering, Kyoto University, Kyoto 615-8510, Japan(e-mail: [email protected]).

T. Hikihara is with the Department of Electrical Engineering, GraduateSchool of Engineering, Kyoto University, Kyoto 615-8510, Japan (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2016566

of large currents. High-frequency switching enables minimiza-tion of bulky passive components and provides control func-tionality. The power switching device is the key component inrealizing this; therefore, development efforts focus on a powerdevice with a high breakdown voltage, low forward voltagedrop, and fast switching capability [1]–[3].

As a result, an Si-insulated gate bipolar transistor (IGBT)has been developed and improved to meet these requirements[4], [5]. Recently, a superjunction structure of Si power MOS-FET was proposed to realize a high breakdown voltage usinga p-n junction and fast switching capability by majority car-riers [6]–[8]. In addition to the Si-based power device, wide-bandgap semiconductor power devices have been researchedand developed to realize lower loss, higher voltage breakdown,and faster switching with a thin voltage blocking layer. SiC andGaN devices are good examples [3], [7], [9]–[21].

The capacitance between the terminals of a power device af-fects its switching behavior, because it must be charged anddischarged during turn-off and turn-on operations [22], [23].The capacitance of a power device increases as the thicknessof the voltage blocking layer is decreased to minimize conduc-tion resistance. The capacitance varies widely with the appliedbias voltage because of depletion in the voltage blocking layer.Therefore, it is necessary to quantify the capacitance betweenthe terminals of the power device as well as the capacitance’svoltage dependency. One method is to estimate the capacitancevalue with finite-element (FE) device simulation and validateit with circuit simulation or experiments [24]–[26]. However,this approach requires a detailed device structure, dimensions,and process parameters. Another method is to characterize thecapacitances experimentally. However, there is no commercialproduct that is able to measure the terminal capacitance of ahigh-voltage power device by applying the bias voltage up to itsrated value. JEDEC [27] and IEC [28] standardized the capac-itance measurement between the terminals of a power devicewith a capacitance bridge, but no actual configuration or circuittopology for the measurements are provided. Elferich et al. [26]measured the C–V characteristics of a power MOSFET andvalidated the FE device simulation; however, the measurementsetup is not clearly described and the applied voltage was low(0 ≤ Vds ≤ 20,−10 ≤ Vgs ≤ 0). Therefore, the authors devel-oped a C–V measurement system for high-voltage power de-vices. Funaki et al. [29] and [30] presented the C–V measure-ment system for high-voltage power diodes with evolving [31]and clarified the punch-through structure of SiC Schottky barrierdiodes (SBDs) from the measured results. This study developsa C–V measurement system for gate-controlled, high-voltage

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FUNAKI et al.: MEASURING TERMINAL CAPACITANCE AND ITS VOLTAGE DEPENDENCY 1487

power devices, e.g., power MOSFET, JFET, and IGBT. Thereare three terminals in a single device, and five specifications ofthe measurement circuit are presented to measure the capaci-tance between gate–source (Cgs), gate–drain (Cgd), and drain–source (Cds), and to measure input (Ciss), output (Coss), andreverse transfer (Crss = Cgd) capacitances. The capacitancesCgs , Cds , and Cds are measured to clarify the device structureand physical behavior, and Ciss , Coss , and Crss are used to esti-mate their influence on circuit operation.

The developed measurement circuit can apply a bias voltagebetween drain and source, and simultaneously to the gate withreference to the source potential. Thus, the circuit can measurethe C–V characteristics for both normally OFF and normallyON devices [32]. Also, it enables measurement of the capac-itances from the blocking condition to the conducting condi-tion with varying gate bias voltage. For instance, an IGBT is ahigh-voltage power device, and its measurements illustrate thephysical phenomenon occurring in the device, which dependson the applied drain (collector) and gate bias voltage.

II. CAPACITANCE OF A POWER DEVICE

AND MEASUREMENT CIRCUIT

This section examines the makeup of the capacitive compo-nent in a power transistor when assuming a planar gate devicestructure and a vertical drift region-type double-diffusion MOS-FET (VDMOSFET) [3]. Further, the paper discusses a circuitfor measuring the capacitance between the power device termi-nals; the circuit can apply a bias voltage between the drain andthe source, and the gate and the source, up to the rated voltageof the device.

A. Terminal Capacitance of VDMOSFET

Fig. 1(a) shows the cross section of one cell in a VDMOS-FET chip. The main dielectrics for inducing capacitance in thecell are the depletion layer formed in the semiconductor andthe gate oxides. The capacitances arising from the gate oxidehave a constant value, irrespective of the voltage applied acrossit. However, the capacitance arising from the depletion layer,which is formed in the semiconductor, changes with the ap-plied voltage across it, where the capacitance is treated as adifferential capacitance dQ/dV . Here, dQ denotes the chargedepleted to the incremental bias voltage dV . The capacitancecomponents that reside in the VDMOSFET are integrated intothe terminal capacitances Cgs , Cgd , and Cds , when seen fromthe terminal of the electrode in a discrete device, as shown inFig. 1(b). These terminal capacitances are configured by thecapacitive components shown in Fig. 1(a) as

Cgs = Cm + Coxs + 11/Cox c +1/C c

Cgd = 11/Cox d +1/Cg d j

Cds = Cdsj.

(1)

Here, Cm is the capacitance between the gate electrode andthe source electrode across the gate oxide, Coxs is the capac-itance of the gate electrode and source n+ region, Coxc is thecapacitance of the gate electrode and the top surface of the p+

region, Cc is the capacitance of the depletion region for the p+

Fig. 1. Example of a gate-controlled transistor to illustrate device capacitance.(a) Cross section of a VDMOSFET cell. (b) Equivalent capacitances betweenterminals of VDMOSFET.

region under the gate, Coxd is the capacitance of the gate elec-trode and top surface of the drain region across the gate oxide,Cgdj is the capacitance of the depletion region for the drain un-der the gate, and Cdsj is the capacitance of the depletion regionfor the drain under the source.

The combination of terminal capacitances in the power devicedetermines circuit operation. The input capacitance is the equiv-alent capacitance when the transistor is seen from the gate ter-minal to drive the gate; it can be expressed as Ciss = Cgs + Cgd .The reverse transfer capacitance (Crss) is the same as Cgd . Itinduces the well-known Miller effect and deteriorates the gatedriving response because of the effectively increased capaci-tance by the multiplier factor of device transconductance [22].The output capacitance corresponds to the capacitance seenfrom the drain terminal, and its charge/discharge operation bythe drain current affects the main circuit response. It can beexpressed as Coss = Cds + Cgd . Thus, five capacitance specifi-cations are needed to characterize the device.

B. Cgs Measurement Circuit

Fig. 2 shows the circuit for measuring Cgs . This circuit canperform four-terminal (Kelvin sense) measurements—Hpot andLpot (for detecting the small ac voltage of the measurement sig-nal) and Hcur and Lcur (for detecting the current of the measure-ment signal). The four measurement terminals are connected toan LCR meter or impedance analyzer.

C1 and C2 block the bias gate voltage, transferring only theac measurement signal from terminals Hpot and Hcur . Theseblocking capacitors enable application of the gate–source biasvoltage (Vgs), and the circuit measures the capacitance char-acteristics related to channel condition, such as accumulation,depletion, and inversion. Moreover, the blocking capacitanceenables the measurement of Cgs for a normally ON device byapplying a gate voltage and making the device channel operate inthe blocking condition. The voltage source Vgs and Vds imposethe dc bias voltage, and the C–V characteristics are measured bysweeping one of them. The ac measurement signal at the sourceterminal is blocked by L1 (because of its high impedance atthe operating frequency); therefore, it is transferred to termi-nals Lcur and Lpot . L1 shorts the source terminal to dc ground





Fig. 2. Cgs measurement circuit.

Fig. 3. Cgd (Crss ) measurement circuit.

and establishes the dc bias voltages Vgs and Vds at the deviceterminals with reference to ground potential. Diodes D1–D12and ZD1–ZD4 provide protection. The RC circuit at the voltagesource input and the monitor output constitute a low-pass filterto block the measurement signal, and apply and measure the dcbias voltage. C7 shorts the drain terminal when measuring anac frequency and blocks dc from the measurement.

C. Cgd (Crss) Measurement Circuit

Fig. 3 shows the circuit diagram for measuring Cgd (Crss).This circuit has two groups of blocking capacitors for the drainand source terminals to ensure ground potential at the sourceterminal. C1 and C2 block the dc bias voltage of Vds , andC7 and C8 block the dc bias voltage of Vgs . The capacitancestransfer the ac measurement signal from Hcur and Hpot toLcur and Lpot , respectively. The source terminal is directlygrounded, and the capacitance component in the device related

Fig. 4. Cds measurement circuit.

to the source terminal is excluded from the measurement. Thedc bias voltages Vds and Vgs are applied and monitored throughthe RC filter.

D. Cds Measurement Circuit

Fig. 4 shows the circuit diagram for measuring Cds . C1 andC2 block the dc bias voltage Vds and transfer the ac measurementsignal from Hcur and Hpot terminals. The dc bias voltages Vdsand Vgs are applied and monitored through the RC filter circuit.Inductor L1, connected to the source terminal, blocks the mea-surement ac signal and transfers it to Lcur and Lpot . However,it shorts the source terminal to dc ground and helps establishthe dc bias voltage with reference to the source terminal. C6,connected to the gate terminal, blocks the dc voltage and estab-lishes the dc potential of the gate terminal, but shorts ac signalsto ground. Therefore, the capacitive component connected tothe gate terminal is excluded from the measurement since it isshunted to the ground.

E. Ciss Measurement Circuit

Fig. 5 shows the circuit diagram for measuring the input ca-pacitance Ciss . This circuit differs from the former measurementcircuits in that it measures the combined capacitance of Cgs andCgd , which have different dc potentials for the drain and source.C1, C2, C7, and C8 block the dc bias voltages of Vds and Vgs ,and transfer the ac measurement signal from Hcur and Hpot toLcur and Lpot , respectively. The dc bias voltages Vds and Vgsare applied and monitored through the RC filter. Inductor L1shorts dc signals at the source terminal to ground, establishesthe reference potential for the dc bias voltage, and blocks theac measurement signal from shorting to ground. The blocked acmeasurement signal is transferred to Hcur and Hpot terminalsthrough the bypass capacitors C9 and C10. Consequentially, thecapacitance between the drain and source terminals are elimi-nated by bypass capacitors C1, C2, C9, and C10.





Fig. 5. Ciss measurement circuit.

Fig. 6. Coss measurement circuit.

F. Coss Measurement Circuit

Fig. 6 shows the circuit diagram for measuring the outputcapacitance Coss , which is the combined capacitance of Cdsand Cgd—the capacitances have different dc potentials at thegate and source terminals. Capacitors C1 and C2 block thedc bias voltage of Vds and transfer the ac measurement signalfrom terminals Hcur and Hpot . The dc bias voltages Vds andVgs are applied and monitored through the RC filter. L1 shortsdc signals to ground at the source terminal and establishes thereference potential for the dc bias voltage. It also blocks the acmeasurement signal from shorting to ground and helps transfer itto terminals Lcur and Lpot . C6 blocks the dc bias voltage of Vgsfrom the source and passes the ac measurement signal, whichis then transferred to Lcur and Lpot terminals; L1 provides ahigh ac resistance to ground. C6 bypasses and eliminates thecapacitance between the gate and source (Cgs).

The values of the blocking and bypass capacitances are se-lected to have sufficiently small impedance relative to the ca-pacitance measurement or elimination ability in the device.

Fig. 7. Frequency characteristics of the blocking capacitor. (4.7 µF, 630 V,film-type capacitor, Cs + Rs measurement.)

TABLE ITEST RESULTS FOR REFERENCE CAPACITANCE (nF)

Film-type capacitors are adopted because of their superior high-frequency performance, but high-voltage-blocking large capac-itors tend to be bulky and have relatively large effective seriesinductance (ESL). Fig. 7 shows the frequency characteristics ofthe capacitance used for blocking high voltages as measuredby an impedance analyzer (Agilent 4294A). The largest ca-pacitance used in the measurement circuit has a self-resonantfrequency around 300 kHz because of the capacitance and ESL,as shown in Fig. 7. JEDEC [32] suggests that the measurementfrequency be low enough to prevent the introduction of the errorstemming from parasitic components, and frequencies below2 MHz are preferred. Therefore, 100 kHz was selected as themeasurement frequency.

III. MEASUREMENT OF C–V CHARACTERISTICS

This section certifies the measured capacitance using the de-veloped capacitance measurement circuit, based on a referencecapacitance set whose values are known a priori. The measuredC–V characteristics of an example device are presented andtheir features discussed as associated with the device structureand composition.

A. Certification of the Measurement Circuit

The developed capacitance measurement circuit is connectedto a HIOKI 3522 LCR meter to quantify the capacitance throughmeasurement terminals Hcur , Hpot , Lcur , and Lpot . At the be-ginning of setting up the experiment, open- and short-circuit





Fig. 8. Measured C–V characteristics for V ce . (a) Cge , Cgc , and Cce (Vge = 0 V). (b) Cies and Co es (Vge = 0 V). (c) Cge for different Vge . (d) Comparisonbetween measured value and datasheet. (Vge = 0 V). (e) Cgc (Cres ) for different Vge .

calibration of the measurement circuit is performed for LCR me-ter operation. Although the developed circuit applies a bias volt-age between terminals, a dc short-circuit current flows throughthe bias voltage source. Therefore, a 0-V dc bias voltage isapplied during circuit calibration.

Three capacitances Ca, Cb, and Cc, whose values are givenin the margin of Table I and are similar to those of an actualsemiconductor device, are used to validate the measurementcircuit. The test capacitors are connected in delta to imitate theterminal capacitance of a power device, and six possible combi-nations of the terminal connection are tested for the five capac-itance measurements. The measured values for the respectivecombinations of reference capacitance connections are given inTable I. The relative percentage error of the actual value is alsogiven in parentheses. The compound capacitances Cgs + Cgdand Cds + Cgd , which are, respectively, equivalent to Ciss andCoss , are also shown in the table for comparison.

The measurement errors for Cgd and Ciss were confirmed asless than 1%—a low error. The error in measuring Cgs tends tobecome large when Cds is larger than Cgs . This can be attributedto measurement signal leakage in the blocking inductor L1 andbypass capacitor C7 (see Fig. 2). The opposite effects are foundin the measurement of Cds . The error in Cds becomes largewhen Cgs is larger than Cds . This is attributed to measurementsignal leakage in blocking inductor L1 and bypass capacitor C6(see Fig. 4). Thus, the errors of compound capacitance Cgs +Cgd tend to become larger than directly measured Ciss , exceptwhen Cds is small. The error in the measured Coss becomeslarge when Cgd is larger than Cds . Leakage of the measurementsignal through L1 in Fig. 6 cannot explain this phenomenon.Hence, this can be attributed to the residue of the measurementsignal for the bypass capacitor C6 (see Fig. 6), i.e., the detectionterminal for Cds is directly connected to the LCR meter throughLcur and Lpot terminals, but the detection terminal for Cgd is





Fig. 9. Measured C–V characteristics for V ge . (a) Cge . (b) Cgc (Cres ).

indirectly connected to the LCR meter through C6. Therefore,the Coss measurement circuit is amenable to Cgd value, and theerrors of directly measured Coss tend to become larger than thecompound capacitance Cds + Cgd when Cgd is small.

The extracted error falls within 5% using the measurementcircuit parameters, as shown in Figs. 2–7. This error can bereduced by increasing the value of the blocking and bypassingelements, but the accuracy given in Table I is sufficient to charac-terize the device because of the dispersion of the characteristicsamong devices.

B. Measured Results

The measured C–V characteristics are exemplified here byconsidering a planar gate IGBT with a 600-V-rated voltage(IRG4BC20S) as an example, and the relationship of the ca-pacitance characteristics to the device structure is discussed.

Fig. 8(a) illustrates the relationship of the measured Cge(=Cgs), Cgc(= Cgd), and Cce(= Cds) to the collector voltage withVge = 0 V. Cge is larger than Cce and Cgc because of theclosely spaced gate and emitter electrodes at the surface of thedevice. It barely changes with the applied Vce , because Vcedoes not affect the expansion of the depletion region across thegate and emitter. Also, depletion in the drift layer depends onVce . Therefore, Cce and Cgc decrease with increase in Vce inaccordance with the expansion of the depletion region. Thereare irregular capacitance changes around Vce = 10 V, whichcan be attributed to the transition of the expanding depletionregion from the JFET region of the planar gate IGBT to theentire drift region. The decrease of the capacitance in Cce andCgc stops around Vce = 300 V, which indicates the terminationof the depletion region expansion in the drift layer because ofthe punch-through structure of the device.

Fig. 8(b) illustrates the directly measured Cies(= Ciss)and Coes(= Coss) and the calculated Cies(= Cge + Cgc) andCoes(= Cce + Cge) from the measured Cce , Cge , and Cgc . Therespective results coincide, validating the adequacy of the mea-sured results. Fig. 8(d) compares the measured (Cies , Coes , Cres)and datasheet values. The datasheet provides capacitances up toVge = 50 V and validates the measured capacitances.

Fig. 8(c) shows Cge to Vce for different Vge . The accumulationof charge (holes) occurs at the device channel and results in adecrease in Cc , as shown in Fig. 1(a), when a gate voltageof Vge = −20 V is applied. Capacitance Cge becomes larger

Fig. 10. Measured V ge –Ice characteristics.

than the depleted condition of the channel by the time Vge =0 V. This phenomenon is shown clearly in Fig. 9(a), whereCge is measured to Vge and Vce is changed as the parameter.Capacitance Cge begins to decrease when Vge becomes higherthan −6 V and it reaches a minimum around Vge = 3 V. Thisindicates the depletion of the accumulated charge (holes) atthe channel with increase in gate voltage Vge . The inversionat the channel begins to occur with increasing gate voltageswhen Vge exceeds 3 V, and Cge increases to the threshold gatevoltage. The threshold gate voltage of this device is 5 V, asshown in Fig. 10, and the channel conducts for a higher gatevoltage. Fig. 8(e) shows Cge (Cres) to Vce for different Vge . Theaccumulation phenomenon is also seen at the top of the JFETregion in a planar device [around Cgdj in Fig. 1(a)], and Cgcvaries with Vge especially in the low Vce region (Vce < 10 V).It also shows that negative Vge reduces Cgc . This phenomenonis clearly confirmed in Fig. 9(b), where Cgc is measured at Vgeand Vce is the parameter being changed. The accumulation atthe top of the JFET region tends to occur when voltages withdifferent polarities are applied across that part, resulting in anincrease in Cgdj [see Fig. 1(c)]. Then, Cgc becomes large forlow Vce within the −6 V < Vge < 3 V region.

The capacitance measurement is by no means restricted tomerely determining the capacitance between terminals, but itcan also clarify a wide variety of physical phenomenon occur-ring in the device.

IV. CONCLUSION

The capacitances between the terminals of a power deviceare important in understanding the dynamic behavior of the





device, such as its switching operation. The device capacitancesare not constant and change with the voltage applied betweenthe terminals. Therefore, a C–V characterization system forgate-controlled power devices was developed in this study. Fivemeasurement circuits were proposed to measure the three com-binations of capacitances between the device terminals, andthree combinations of device capacitance for circuit operation.The adequacy of the proposed measurement system was veri-fied using a reference capacitance and the factor of error wasdiscussed. The developed capacitance characterization systemcan measure capacitance from the blocking condition to theconducting condition while changing the gate bias voltage. Thevariation of the depletion and accumulation condition in thedevice was reflected in the device capacitance. The measuredcapacitance explained the device structure and the physical phe-nomenon occurring in the device.

ACKNOWLEDGMENT

The authors thank to Prof. J. C. Balda from the University ofArkansas for discussions regarding C–V measurements.

REFERENCES

[1] B. J. Baliga, Modern Power Devices. New York: Wiley, 1987.[2] B. J. Baliga, Power Semiconductor Devices. Boston, MA: PWS-Kent,

1995.[3] B. J. Baliga, Silicon Carbide Power Devices. Singapore: World Scien-

tific, 2006, pp. 15–33.[4] B. J. Baliga, M. S. Adler, R. P. Love, P. V. Gray, and N. D. Zommer, “The

insulated gate transistor: A new three-terminal MOS-controlled bipolarpower device,” IEEE Trans. Electron Devices, vol. ED-31, no. 6, pp. 821–828, Jun. 1984.

[5] K. Fujii, P. Koellensperger, and R. W. De Doncker, “Characterization andcomparison of high blocking voltage IGBTs and IEGTs under hard- andsoft-switching conditions,” IEEE Trans. Power Electron., vol. 23, no. 1,pp. 172–179, Jan. 2008.

[6] X.-B. Chen and J. K. O. Sin, “Optimization of the specific on-resistance ofthe COOLMOS,” IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 344–348, Feb. 2001.

[7] Z. Liang, B. Lu, J. D. van Wyk, and F. C. Lee, “Integrated CoolMOSFET/SiC-diode module for high performance power switching,” IEEETrans. Power Electron., vol. 20, no. 3, pp. 679–686, May 2005.

[8] Y. Chen, Y. C. Liang, and G. S. Samudra, “Design of gradient oxidebypassed superjunction power MOSFET devices,” IEEE Trans. PowerElectron., vol. 22, no. 4, pp. 1303–1310, Jul. 2007.

[9] J. L. Hudgins, G. S. Simin, E. Santi, and M. A. Khan, “An assessmentof wide bandgap semiconductors for power devices,” IEEE Trans. PowerElectron., vol. 18, no. 3, pp. 907–914, May 2003.

[10] A. R. Hefner, R. Singh, J. Lai, D. Berning, S. Bouche, and C. Chapuy,“SiC power diodes provide breakthrough performance for a wide range ofapplications,” IEEE Trans. Power Electron., vol. 16, no. 2, pp. 273–280,Mar. 2001.

[11] B. Ozpineci and L. M. Tolbert, “Characterization of SiC Schottky diodesat different temperatures,” IEEE Power Electron. Lett., vol. 1, no. 2,pp. 54–57, Jun. 2003.

[12] Y. Jian, L. Zhenxian, and J. D. van Wyk, “High temperature embeddedSiC chip module (ECM) for power electronics applications,” IEEE Trans.Power Electron., vol. 22, no. 2, pp. 392–398, Mar. 2007.

[13] T. Funaki, J. Balda, J. Junghans, A. Kashyap, A. Mantooth, F. Barlow,T. Kimoto, and T. Hikihara, “Power conversion with SiC devices atextremely high ambient temperatures,” IEEE Trans. Power Electron.,vol. 22, no. 4, pp. 1321–1329, Jul. 2007.

[14] T. Funaki, J. C. Balda, J. Junghans, A. S. Kashyap, F. D. Barlow, H.A. Mantooth, T. Kimoto, and T. Hikihara, “SiC JFET dc characteristicsunder extremely high ambient temperatures,” IEICE Electron. Exp., vol. 1,no. 17, pp. 523–527, 2004.

[15] T. Funaki, J. C. Balda, J. Junghans, A. Jangwanitlert, S. Mounce, F. D. Bar-low, H. A. Mantooth, T. Kimoto, and T. Hikihara, “Switching character-istics of SiC JFET and Schottky diode in high-temperature dc–dc powerconverters,” IEICE Electron. Exp., vol. 2, no. 3, pp. 97–102, 2005.

[16] P. Shah, B. Geil, M. Ervin, T. Griffin, S. Bayne, K. Jones, and T. Old-ham, “Advanced operational techniques and pn–pn–pn structures for high-power silicon carbide gate turn-off thyristors,” IEEE Trans. Power Elec-tron., vol. 17, no. 6, pp. 1073–1079, Nov. 2002.

[17] G. Spiazzi, S. Buso, M. Citron, M. Corradin, and R. Pierobeon, “Perfor-mance evaluation of a Schottky SiC power diode in a boost PFC applica-tion,” IEEE Trans. Power Electron., vol. 18, no. 6, pp. 1249–1253, Nov.2003.

[18] T. R. McNutt, A. R. Hefner, H. A. Mantooth, J. Duliere, D. W. Berning,and R. Singh, “Silicon carbide PiN and merged PiN Schottky power diodemodels implemented in the saber circuit simulator,” IEEE Trans. PowerElectron., vol. 19, no. 3, pp. 573–581, May 2004.

[19] T. McNutt, A. Hefner, A. Mantooth, D. Berning, and R. Sei-Hyung, “Sil-icon carbide power MOSFET model and parameter extraction sequence,”IEEE Trans. Power Electron., vol. 22, no. 2, pp. 353–363, Mar. 2007.

[20] A. M. Abou-Alfotouh, A. V. Radun, H. R. Chang, and C. Winterhalter, “A1-MHz hard-switched silicon carbide DC–DC converter,” IEEE Trans.Power Electron., vol. 21, no. 4, pp. 880–889, Jul. 2006.

[21] T. Nomura, M. Masuda, N. Ikeda, and S. Yoshida, “Switching charac-teristics of GaN HFETs in a half bridge package for high temperatureapplications,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 692–697,Mar. 2008.

[22] J. M. Miller, “The dependence of the amplification constant and internalplate circuit resistance of a three-electrode vacuum tube upon the structuraldimensions,” Proc. IRE, vol. 8, pp. 64–72, 1920.

[23] S. Pittet and A. Rufer, “The equivalent electron density concept for staticand dynamic modeling of the IGBT base in soft- and hard-switchingapplications,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2223–2233, Nov. 2007.

[24] T. Biondi, G. Greco, M. C. Allia, S. F. Liotta, G. Bazzano, and S. Rinaudo,“Distributed modeling of layout parasitics in large-area high-speed siliconpower devices,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1847–1856, Sep. 2007.

[25] S. Rael and B. Davat, “A physics-based modeling of interelectrode MOScapacitances of power MOSFET and IGBT,” IEEE Trans. Power Elec-tron., vol. 23, no. 5, pp. 2585–2594, Sep. 2008.

[26] R. Elferich, T. Lopez, and N. Koper, “Accurate behavioural modeling ofpower MOSFETs based on device measurements and FE-simulations,”presented at the 2005 Eur. Conf. Power Electron. Appl., Dresden,Germany, Sep. 11–14, Paper 0708.

[27] JESD6 Measurement of Small Values of Transistor Capacitance, JEDECStandard, 1967.

[28] Semiconductor Devices, IEC Standard 60747, 2006.[29] T. Funaki, S. Matsuzaki, T. Kimoto, and T. Hikihara, “Characterization

of punch-through phenomenon in SiC-SBD by capacitance-voltage mea-surement at high reverse bias voltage,” IEICE Electron. Exp., vol. 3,no. 16, pp. 379–384, 2006.

[30] T. Funaki, T. Kimoto, and T. Hikihara, “Evaluation of high frequencyswitching capability of SiC Schottky barrier diode, based on junction ca-pacitance model,” IEEE Trans. Power Electron., vol. 23, no. 5, pp. 2602–2611, Sep. 2008.

[31] Impedance Measurement Handbook. Agilent Technol., Santa Clara, CA,AN-5950-3000, Jul. 2006, pp. 27–28.

[32] T. Funaki, T. Kimoto, and T. Hikihara, “Evaluation of capacitance-voltagecharacteristics for high voltage SiC-JFET,” IEICE Electron. Exp., vol. 4,no. 16, pp. 517–523, 2007.

Tsuyoshi Funaki (S’92–M’00) received the B.E. and M.E. degrees in electricalengineering and the Ph.D. degree from Osaka University, Suita, Japan.

He joined Osaka University as a Research Associate in 1994 and became anAssistant Professor in 2001 and a Professor in 2008. In 2002, he joined KyotoUniversity, Kyoto, Japan, as an Associate Professor. From 2004 to 2005, he wasa Visiting Scholar in the Department of Electrical Engineering, University ofArkansas, Fayetteville, where he was engaged in collaborative research on SiCdevices and their application.

Prof. Funaki is a member of the Institute of Electrical Engineers of Japan, theInstitute of Electronics, Information and Communication Engineers of Japan,the Institute of Systems, Control and Information Engineers, the Society ofAtmospheric Electricity of Japan, and the Institution of Engineering and Tech-nology, London, U.K.





Nathabhat Phankong was born in Yala, Thailand, on May 18, 1975. He re-ceived the B.Eng. and M.Eng. degrees in electrical engineering from KingMongkut’s University of Technology Thonburi, Bangkok, Thailand, in 1999and 2003, respectively. He is currently working toward the Ph.D. degree at thePower Device Modeling Group, Kyoto University, Kyoto, Japan.

He is also an Instructor in the Department of Electrical Engineering, Ra-jamangala University of Technology Thanyaburi, Thanyaburi, Thailand. Hiscurrent research interests include semiconductor device modeling, power elec-tronic system design, and characteristics of power devices.

Mr. Phankong is a member of the Institute of Electrical Engineers of Japanand the Institute of Electronics, Information and Communication Engineers ofJapan.

Tsunenobu Kimoto (M’03–SM’06) received the B.E. and M.E. degrees inelectrical engineering and the Ph.D. degree from Kyoto University, Kyoto,Japan, in 1986, 1988, and 1996, respectively.

In April 1988, he was with Sumitomo Electric Industries, Ltd., where he wasengaged in research on amorphous Si solar cells and semiconducting diamondmaterial. In 1990, he was a Research Associate at Kyoto University. FromSeptember 1996 to August 1997, he was a Visiting Scientist at LinkopingUniversity, Sweden, where he was involved in fast epitaxy of SiC and high-voltage Schottky diodes. He is currently a Professor in the Department ofElectronic Science and Engineering, Kyoto University. His current researchinterests include SiC epitaxial growth, optical and electrical characterization,ion implantation, MOS physics, and high-voltage devices. He has also beeninvolved in nanoscale Si devices and novel materials for nonvolatile memory.He has authored or coauthored more than 250 papers in scientific journals andinternational conference proceedings.

Prof. Kimoto is a member of the Japan Society of Applied Physics, theInstitute of Electronics, Information and Communication Engineers of Japan,and the Institute of Electrical Engineers of Japan.

Takashi Hikihara (S’84–M’88) was born in Kyoto, Japan, in 1958. He receivedthe B.E. degree from the Kyoto Institute of Technology, Kyoto, Japan, in 1982,and the M.E. and Ph.D. degrees from Kyoto University, Kyoto, in 1984, and1990, respectively.

From 1987 to 1997, he was with the faculty of the Department of ElectricalEngineering, Kansai University, Suita, Japan. From 1993 to 1994, he was aVisiting Researcher at Cornell University. In 1997, he joined the Department ofElectrical Engineering, Kyoto University, where he is currently a Professor. Heis an Associate Editor of European Journal of Control and the Vice Editor of thejournal Systems Control and Information. His current research interests includenonlinear science and its application. He is also involved in system control andnanotechnology.

Prof. Hikihara is a member of the Institution of Engineering and Technology,London, U.K., the Institute of Electronics, Information and CommunicationEngineers of Japan, the Institute of Electrical Engineers of Japan, the AmericanPhysics Society, the Society for Industrial and Applied Mathematics, etc.




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