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Timing simulation:

Timing simulation takes NETLIST, library models of the cells and constraints (clock

period, skew, setup and hold time) as INPUTS and gives OUT as delay through the

combinational logic.

Timing simulation allows you to check that implemented design meets all timingrequirements and behaves as you expected in the device. Timing simulation helps

you to find

- Post synthesis implementation functionality changes.

- Dual-port RAM collisions.

- Missing component generics for VHDL.

- Missing module defparams for verilog.

- Missing or improperly applied timing constraints.

- Operation of asynchronous paths.

Timing constraints:

Timing constraints used to control clock freq, setup and hold times for synchronous

inputs and clock-to-output time for synchronous outputs.

Setup time

For an edge triggered sequential element, the setup time is the time interval before

the active clock edge during which the data should remain unchanged

Hold time

Time interval after the active clock edge during which the data should remain

unchanged

Both the above 2 timing violations can occur in a design when

clock path delay > data path delay

Pulse width

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It is the time between the active and inactive states of the same signal

Signal (Clock/Data) slew

Amount of time it takes for a signal transition to occur.

Clock Latency

Difference between the reference (source) clock slew to the clock tree

endpoint signal slew values

Rise latency and fall latency are specified

Slack

It is the difference between the required (constraint) time and the

arrival time (inputs and delays).

Negative slack indicates that constraints have not been met, while

positive slack indicates that constraints have been met.

Slack analysis is used to identify timing critical paths in a design by the

static timing analysis tool

Critical path

Any logical path in the design that violates the timing constraints

Path with a negative slack

Clock skew

- Its a measure of difference between any two leaf pins in a clock tree

- It is also defined as the difference in time that a single clock signal takes to

reach two different registers.

TESTING:

Boundary scan:

- In boundary scan, all flip flops enter a test mode where they are controllable

and observable.

- After functional verification, normal flip flops are replaced by scan flip flops.

- Only D flip flops must be used.

- Clocks must not be generated internally

Controllable: Difficulty in setting a signal to 0 or 1.

Observable: Difficulty of reading a specific signal.

STATIC SIMULATION ANALYSIS:

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Effective methodology for verifying the timing characteristics of a design

without the use of test vectors

Conventional verification techniques are inadequate for complex designs

Simulation time using conventional simulators

Thousands of test vectors are required to test all timing paths using

logic simulation

Increasing design complexity & smaller process technologies

Increases the number of iterations for STA