TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS … · 2006-02-23 · timing-driven physical...
Transcript of TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS … · 2006-02-23 · timing-driven physical...
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TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS
USING RESONANT CLOCKING
BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV
February 28, 2005
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Research Objective
Objective: Electronic design
automation and synchronization of
digital IC systems with “rotary”
resonant clocking technology.
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Clocking at GHz• Problems:
– Low-skew low-jitter uncharacteristic– Timing violations– Power dissipation
• Some solutions– Multi-domain clocking– Skew-tolerant multi-phase clocking
• Alternative technologies– Optical clocking– Transmission-line based clocking
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Resonant Clocking
ConstantVariableTraveling Wave
VariableConstantStanding Wave
ConstantConstantCoupled LC
VoltagePhaseOscillator Type
1
1: Abstract from IBM Research http://www.reseach.ibm.com/compsci/project_spotlight/vlsi/
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Transmission Line
• Long interconnect
• L (variation with process) ≈1%
• C (Variation with process) < 30%
• Vp(variation with process) ≈15%
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Mobius Termination
• Shunt connected inverters between lines• fosc ~ 1/√L• 2 laps to complete 360o phase
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Rotary Clock Waveforms
Waveforms for line voltage and line current at 2.4GHz
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Rotary Clocking
• Low-jitter– ~6ps for 2.4GHz 0.25um
• 1% of clock period
• Non-sinusoidal clock signal– 20ps rise and fall times (0.25um)
• 5% of the clock period
• 16GHz theoretical upper limit in0.25um
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Rotary Cycles
• 360o Phase/ring– Multi-phase!
• No distribution, generatedacross the die
• Energy preserving
• Self-replenishing
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ASIC Implementation
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Capacitive Loading
• Reduce propagation velocity– Independent of parasitic capacitance
– Increase current in wires, but no CV2f power
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Rotary Wires for ASIC
Synchronous components
Rotary distribution
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Modes of Operation
• ASIC drive– Global rotary clock to synchronize any number of:
• Derived clocks• Other global signals – Reset, Enable, Step, Scan
– Retain standard FFs– Minimal flow impact
• Direct Drive– Maximum power benefit.– One high frequency clock grid over whole chip directly
driving all FFs.– Custom FFs for lowest power.– Modified flow.
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DFF Load
• High internal capacitance– High dynamic power consumption
• Direct drive: Rotary clock drives Nfet and Pfet pass devices directly
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Latch Load
• Less clocked C: save CV2f power• No need to gate clock (only data)
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Rotary Modes
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CAD: Extraction and Simulation
• RLC extraction for rotary
• RC for data
• Fast SPICE for confirmation
• Internal STA engine
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CSS FEA SIB LE?
D ESIG N EN T RY
RO A SIZE
PART IT IO N IN G
REG IST ER IN SERT IO N
CSS on PA RT IT IO N I CSS on PA RT IT IO N N
CSS on T O P B LO CK
REG IST ER M APPIN G
LO G IC PLACEM EN T
Y ESN O
C LO C K SK EW SC H ED U LIN G
RO A FEASIB LE?Y ESN O
PA R TITIO N IN G
PLA C EM EN T
Physical Design Flow
Partitioning
CSS
Placement
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CAD: Placement & Route 1
• Select rotary rings• Physical implementation
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CAD: Placement & Route 2
ClockPin
• Identify communicating register-to-register paths
• Partitioning
• Static timing analysis
• Clock skew scheduling– 28% average
improvement
– Parallelization
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CSS Parallelization
• 10k registers 25k local paths– 2.5 hours
• 10*10 rotary clocking• 150 registers 500 paths
– 2 secs
• Speed up:– 44X without parallelization– 1286X with parallelization
• Sub-optimality
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CAD: Placement & Route 3
• Pre-place register banks• Map registers to phase• Proceed with logic synthesis
0o 180o 90o = T/4 delay270o
45o
135o
315o
225o
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Conclusions
• Look-ahead to next-generation
• Rotary clocking
• Non-zero clock skew
• Parallelization
• Implementation results to follow
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TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS
USING RESONANT CLOCKING
QUESTIONS?
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DESIGN AND TIMING ANALYSIS OF LEVEL-SENSITIVE DIGITAL INTEGRATED
CIRCUITS
BACKUP SLIDES
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Clock Period Minimization Problem - 1
• Objective function : min T
• Problem variables
– For each register Ri
• Earliest/latest arrival times ai, Ai
• Earliest/latest departure times di, Di
• Clock signal delay ti
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Clock Period Minimization Problem - 2
• Problem Parameters
– For each register Ri
• Clock-to-output delay DCQ
• Data-to-output DDQ
• Setup time Si
• Hold time Hi
– For each local data path Ri → Rj
• Data propagation time DPif
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Practical Causes of Clock Skew
• Size Mismatches
–Buffer Size, Interconnect length
• Process Variations
–Leff, Tox etc.
• Temperature Gradients
• Power Supply Voltage Drop
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Rotary Implementation
• Odd number of crossovers–Multi-phase
• Relative phase information on ring–Non-zero clock skew
• Cross-coupled inverters–Low power
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Capacitive Loading of the Rotary Ring
• 4.5 pF each side0.13u x 10834 e-18 / micron [sq] =
12.7 fF on each gate
Assume 10 fF on each line for wiring cap. of spur
= 22.7 fF * 200 loads – 4.5 pF each side
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Benefits of Rotary Clock Architecture
• No practical upper frequency limitation
• No practical size limitation• Negates the dynamic clock power• Guaranteed near-zero skew• Precise skew scheduling possible• Negligible jitter
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Benefits of Rotary Clock Architecture (cont’d.)
• Largely independent of:– Process variations
– Temperature variations
– Supply voltage
• Inherently low noise– No SSN generated by clock.
– Differential• Greater immunity to noise
• Less generation of noise
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Benefits of Rotary Clock Architecture (cont’d)
• Works for all existing IC processes
• Short and predictable design cycle
• Automated CAD tooling