Timing Constraints: Are they constraining designs or designers?

Subramanyam SripadaSynopsys Inc3/13/2015

Constraint Analysis/Debug/Management

Budgeting Issues Functional

Scan

Test

Low_Power

More Modes

More Files/More complexconstraints IP Blocks

Reused Cores

Blocks

Timing Constraints

Synthesis, P&R, Signoff

Difficult integrationof chip-levelconstraints

Constraint Issues

• Incomplete, inconsistent or conflicting constraints

• Inconsistent block-level and top-level constraints

• Automatic generation of timing constraints vs verification of manually generated timing constraints

• Detection, Debugging and Fixing• Dealing with MMMC constraints

Panel Details

• Need of clean SDC for design flows• Challenges in generating clean SDC• State of current EDA tools• What is needed from EDA tools?• Panelists

– Texas Instruments– Ausdia– Intel– FishTail– Altera– Synopsys

Krishna Panda

Krishna Panda is STA Technologist at Texas Instruments. He has been responsible Timing and Signal Integrity Signoff for the past three technology Node. He is a Member of Technical Staff at TI. Joined Texas Instrument in 2002. He has a Bachelor’s Degree in Electronics Engineering from Mumbai University and has 20+ years of ASIC design experience.

Sam Appleton

Sam co-founded Ausdia, and drove the early product planning, product development and market analysis for Timevision. Prior to Ausdia, Sam held a variety of technical leadership roles at Azul Systems, Reshape, Cosine Communications and Silicon Graphics. At Azul Systems, Sam drove the implementation & physical methodology for three generations of custom SMP processors, from 500 to 900Mhz and 1.2B transistors.

Sam received a Ph.D. in Electronic Engineering from the University of Adelaide, focused on high-performance asynchronous circuit & logic design. He has personally been involved in more than 20 tape outs from 1um to 28nm.

Bruce is part of the newly acquired Axxia network processor group at Intel in Allentown PA, working on design methodologies. His areas of focus include static timing analysis, constraint verification, timing closure and low power design techniques.

He has been at Intel (previously Avago Technologies, LSI, Agere Systems, Lucent – Microelectronics, AT&T) for 20 years. Prior to that, he was a Field Application Engineer at Racal Redac in NJ, and a Design Engineer at Raytheon in Tewksbury MA.

He has received a Masters of Science in Electrical Engineering from Northeastern University, and a Bachelor of Science in Electrical Engineering from the State University of New York at Stony Brook.

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Bruce Zahn

Ajay Daga

Ajay received his PhD in Computer Engineering from The University of Michigan, Ann Arbor in 1994. Ajay worked in Mentor Graphics and Synopsys before founding, funding and growing FishTail revenues.

Tom Spyrou

Tom Spyrou has worked for over 25 years as an EDA Technologist and has gained extensive experience in areas including Static Timing Analysis, Logic Synthesis, Power Grid Analysis, Database Technology and Floor-planning. He has lead the development of leading edge commercial engines and products such as PrimeTime, Voltage Storm, First Encounter, and the Open Access Database. He has a BS from CMU in ECE and and MS from Santa Clara. He is currently the Architect of Altera’s new TimeQuest2 STA tool.

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Qiuyang Wu

Qiuyang Wu has been in the EDA industry for 15 years, with expertise in STA, Synthesis, P&R, also extensive experiences in parallel programing and large-scale distributed processing.  As an architect for hierarchical timing and methodology in PrimeTime with Synopsys, his current focus ranges from macro modeling, hierarchical analysis, constraint management. He holds master’s degrees in physics and computer science in 2000.