TIMING ANALYSIS OF LOGIC-LEVEL DIGITAL CIRCUITS

USING UNCERTAINTY INTERVALS

A Thesis

by

JOSHUA ASHER BELL

Submitted to the Office of Graduate Studies ofTexas A&M University

in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

August 1996

Major Subject: Computer Science

TIMING ANALYSIS OF LOGIC-LEVEL DIGITAL CIRCUITS

USING UNCERTAINTY INTERVALS

A Thesis

by

JOSHUA ASHER BELL

Submitted to Texas A&M Universityin partial fulfillment of the requirements

for the degree of

MASTER OF SCIENCE

Approved as to style and content by:

Duncan M. Walker Dhiraj K. Pradhan

(Chair of Committee) (Member)

M. Ray Mercer Richard A. Volz

(Member) (Head of Department)

August 1996

Major Subject: Computer Science

iii

ABSTRACT

Timing Analysis of Logic-Level Digital Circuits Using

Uncertainty Intervals. (August 1996)

Joshua Asher Bell, B.S., Texas A&M University

Chair of Advisory Committee: Dr. Duncan M. Walker

Competitive design of modern digital circuits requires high performance at

reduced cost and time-to-market. Timing analysis is increasingly used to deal with the

more aggressive timing constraints inherent in high performance designs and the increased

complexity of current VLSI technology. Reliance on synthesis and modular design to

reduce cost and time-to-market has resulted in increased occurrence of non-functional

paths which must be dealt with during timing analysis.

In this work, an incremental timing analysis procedure is developed. Several

techniques are introduced to improve the implicit trimming of false paths during path

generation. The use of Recursive Learning to find indirect conflicts during the path

building is studied. Dynamic dominators are introduced and used to prevent the checking

of multiple paths with equivalent constraints. The technique of forward trimming is

developed to discover blocked paths early and guide the search toward the true longest

path. These techniques are shown to improve the search process during the path building

phase of the incremental path generation routine.

In addition, an improved dynamic sensitization criteria is presented which

incorporates the actual delay of circuit elements. The delay of the circuit elements is

dependent on the manufacturing process parameters. A min/max delay model is used to

iv

incorporate these variations of delay into the sensitization criteria. An uncertainty interval

is used to represent transitions in the circuit since the exact time of the transition is

unknown. The performance of the implicit path elimination techniques and the improved

dynamic sensitization criteria is demonstrated through experimental results on some

combinational benchmark circuits.

v

ACKNOWLEDGMENTS

I would like to express my sincere gratitude to my committee chair, Dr. Duncan

Moore Henry Walker, for the guidance and support he provided throughout the course of

my studies. In addition, I would like to thank Dr. Dhiraj Pradhan and Dr. M. Ray Mercer

for consenting to be on my committee and for their guidance and insight during the

planning and preparation of this work. I would also like to thank my fellow students in

Dr. WalkerÕs research group for providing many useful discussions and comments.

Special thanks to Giam-Minh Luong with whom I had most of the discussions. I greatly

appreciate the theoretical insights provided by my committee members and colleagues

during the development of this work.

In addition I would like to thank Ellen Mitchell, Shridhar Muppidi, and the rest of

the system support staff. These people proved to be a valuable resource when system

problems arose, which seemed to happen to me quite often. The technical support

provided by these people allowed me to concentrate on my research. For this I am

extremely grateful.

Finally, I would like to thank my family and friends who provided emotional

support during those times when I needed it most. I would also like to thank my father for

convincing me that attending graduate school was the right choice and my mother for

convincing me that it is now time to leave school at least temporarily.

vi

TABLE OF CONTENTS

Page

ABSTRACT................................................................................................................... iii

ACKNOWLEDGMENTS ................................................................................................v

TABLE OF CONTENTS.................................................................................................vi

LIST OF FIGURES .......................................................................................................viii

LIST OF TABLES...........................................................................................................ix

I. INTRODUCTION.........................................................................................................1

II. OVERVIEW ................................................................................................................3

A. FALSE PATH PROBLEM................................................................................5B. SENSITIZATION CRITERIA ..........................................................................6C. PATH JUSTIFICATION PROCEDURES.......................................................16D. PATH DETERMINATION METHODS .........................................................18

III. IMPROVED DYNAMIC SENSITIZATION ............................................................20

A. UNCERTAINTY INTERVALS......................................................................20B. SENSITIZING UNCERTAINTY INTERVALS..............................................22C. DEPENDENCE ON DELAY MODEL ...........................................................25

IV. PATH GENERATION IN TIMING ANALYSIS .....................................................27

A. PREPROCESSING STEPS.............................................................................28B. THE PATH STORE ........................................................................................29C. PATH GENERATION....................................................................................30D. REFINED IMPLICIT FALSE PATH ELIMINATION ...................................31

V. FINAL JUSTIFICATION ..........................................................................................37

VI. RESULTS ................................................................................................................39

A. MODIFIED STATIC SENSITIZATION.........................................................39B. STATIC SENSITIZATION.............................................................................40

Page

C. DYNAMIC SENSITIZATION WITH UNCERTAINTY INTERVALS ..........43

vii

VII. CONCLUSION.......................................................................................................48

A. SUMMARY....................................................................................................48B. FUTURE WORK............................................................................................50

REFERENCES...............................................................................................................52

VITA..............................................................................................................................55

viii

LIST OF FIGURES

Page

Figure 1: Circuit Model ....................................................................................................4

Figure 2: A Static False Path.............................................................................................9

Figure 3: Overestimation of Static Sensitization..............................................................10

Figure 4: Portion of C432 ...............................................................................................11

Figure 5: Dynamic Sensitization Example ......................................................................13

Figure 6: Unsensitizable under Floating Mode ................................................................15

Figure 7: Expanding Uncertainty Interval .......................................................................21

Figure 8: Sensitizing a Rising Transition.........................................................................23

Figure 9: Sensitizing a Falling Transition........................................................................23

Figure 10: Minimal Criteria for Rising Transition ...........................................................24

Figure 11: Minimal Criteria for Falling Transition ..........................................................25

Figure 12: Incremental Path Generation..........................................................................31

Figure 13: Dynamic Dominator ......................................................................................34

Figure 14: Application of Forward Trimming .................................................................36

ix

LIST OF TABLES

Page

Table 1: Static Sensitization with Dynamic Dominators..................................................41

Table 2: Static Sensitization with Forward Trimming .....................................................42

Table 3: 100 Static Paths.................................................................................................43

Table 4: Dynamic Sensitization with Dynamic Dominators ............................................45

Table 5: Dynamic Sensitization with Forward Trimming ................................................46

Table 6: 100 Dynamic Paths ...........................................................................................47

1

________________The journal model is IEEE Transactions on Computer-Aided Design of Integrated

Circuits and Systems.

I. INTRODUCTION

Timing analysis is an essential step in all phases of development of integrated

circuits. Among the most important of these phases are the design, optimization, and

testing. One of the most useful results from timing analysis is the determination if a

specific design will operate at a desired speed. To guarantee this the largest propagation

delay of the circuit must be less than the system clock cycle time. Many timing analysis

tools have used the longest structural path in a circuit as an estimate of this delay.

Unfortunately, the longest structural path is often unsensitizable. That is, for these paths

there is no set of inputs that can cause a transition to propagate from the input to the

output. Tools that report the structural longest path can overestimate the delay of a circuit.

Modern digital circuit design is marked by a rapid increase in performance

accompanied by a decrease in cost and time-to-market. To attain these opposing goals

designers are forced to turn to design tools to assist in the development of integrated

circuits. Higher performance is achieved through decreased clock cycle times and more

aggressive timing constraints. As a result, timing analysis tools must be more accurate in

estimating the circuit delay. Modern high performance circuits are noted for having many

paths of nearly equal length. The exact delay of these paths is dependent on

manufacturing process parameters and the operating environment. It is often impossible

to determine a single path which bounds the delay of the circuit. Any path whose delay

may exceed the clock speed under some set of process parameters and operating

environment must be tested. In generating these tests, timing analysis tools are faced with

2

increased occurrence of false paths brought on by extended use of logic synthesis and

modular design techniques used in an effort to reduce cost and time-to-market.

In this paper, the determination of a set of longest sensitizable paths and path

delays for a circuit given its logic-level description is described. Previous path

sensitization techniques and path search algorithms are discussed. An accurate dynamic

path sensitization technique using uncertainty intervals is given and an approach for using

this to determine a set of longest paths is developed. A timing analysis system is

implemented and some combinational benchmark circuits are used to demonstrate

performance.

3

II. OVERVIEW

The purpose of timing analysis is to ensure that a circuit meets all timing

specifications and will operate correctly at speed. To ensure this the longest propagation

delay of the circuit must be tested. Figure 1 shows the circuit model used for this work.

Under this model circuits are assumed to operate off a single system clock. A functional

path starts at a primary input (PI) or memory element and terminates at a primary output

(PO) or memory element. In addition, it must be possible to propagate a transition along

the path for some combination of inputs. The combination of inputs is considered an

input vector. Two input vectors are required to test a path. The first initializes the circuit

values and the second launches the transition on the input to the path. Under the single

system clock assumption, the PIs are assumed to be initialized to the input vector and

simultaneously switched to the value of the second input vector at t0. A PI has a transition

if the values supplied by the two input vectors are different. The delay of the path is

calculated as the sum of the delay of the circuit elements on the path. For a circuit to

operate correctly the delay of the longest path must be shorter then the system clock cycle

time. Otherwise an incorrect logic value may be clocked into a memory element or arrive

late on a primary output. This may be the result of setting the system clock cycle time too

low or a delay fault may exist.

Delay faults have been modeled as path delay faults[1, 2] or gate delay faults[3, 4].

The gate delay fault model targets slow-to-rise or slow-to-fall faults at every gate input or

output in the circuit. The path delay fault model targets delay faults distributed along the

entire path. This work is primarily focused on detecting path delay faults where variance

4

in the delay of each circuit element on the path may result in a path delay which exceeds

the clock cycle time. In the remainder of this paper only the combinational logic portion

of the circuit is considered and all inputs are assumed to be primary inputs (PIs) and all

outputs are assumed to be primary outputs (POs).

latch

PIs POs

Combinational

Logic Block

Figure 1: Circuit Model

In this work, timing analysis is studied at the logic-level. Circuits are assumed to

consist of AND, NAND, OR, NOR, XOR, XNOR, NOT, and BUFFER gates of varying

number of inputs. More complex gates are represented as a logically equivalent

combination of these gates. The longest propagation delay of a circuit is determined by a

critical path connecting a primary input to a primary output via logic gates. The logic

gates and interconnect are responsible for the delay of the critical path. Variations in

parameters during the manufacturing process make it impossible to accurately predict the

5

exact delay of the circuit components. However, it is possible to account for the

variations by providing a range of possible delay values for the circuit components. It is

assumed that delay information including minimum, maximum, and nominal delay is

available for the circuit components.

The following sections provide some background on previous timing analysis

research. The problem of false paths is described. Sensitization criteria used to check for

false paths are given. Previous path justification methods for sensitizing a path are shown.

Finally, several approaches for determining the propagation delay of a circuit are

discussed.

A. FALSE PATH PROBLEM

A large amount of research has gone into the development of automatic timing

analysis systems. One of the earliest examples of such a tool was PERT[3]. This tool

determined the maximum delay based on the longest topological path in the circuit. This

system greatly simplified the problem by ignoring the functionality of the circuit. With

simplification the problem of finding the longest propagation path and delay reduces to

finding the longest path and its delay in a graph. This problem can be solved in linear

time to the size of the graph by applying graph-theoretic algorithms[5, 6]. This approach

is simple and efficient enough to be applied to even large circuits. However, by ignoring

the functionality of the circuit some paths may be reported that are not meaningful. When

including the functionality of the circuit no set of inputs exist which can cause a transition

to propagate along these paths. Such paths are said to be false paths. They do not

contribute to the function or delay of the circuit and should not be included in timing

analysis. By taking into account only the structure of the circuit tools such as PERT

6

searched all paths and reported the longest one regardless of functionality. As a result

these tools overestimate the delay of circuits where false paths exist. However, a

guaranteed upper bound to the circuit delay was provided by this method.

At one time it was considered acceptable to ignore false paths in timing analysis.

Afterall, this resulted only in overestimating the delay of the circuit, but the correct

behavior is still guaranteed. In addition, few false paths existed in circuits as designers

attempted to eliminate them except where needed for specific reasons. Those that did

exist were well documented and could be marked for elimination from timing analysis.

In modern timing analysis it is not acceptable to ignore false paths. Modern digital

circuit design is pushing for higher performance at lower cost. The higher performance is

achieved in part through tight timing constraints. The overestimation caused by false

paths is no longer acceptable. In addition, circuits tend to have greater numbers of false

paths as circuit designers turn toward logic synthesis and modular design methodologies

to reduce cost. Even though individual modules may not have false paths, some may still

be created when the modules are combined into a complete circuit.

B. SENSITIZATION CRITERIA

As described earlier a path is said to be false if no combination of primary inputs

will allow a transition to propagate from input to output. For the transition to propagate

specific conditions must be met at each gate along the path. These conditions are called

the path sensitization criteria. A path is sensitizable if a set of primary inputs exist which

cause the criteria to be met for each gate along the path. If the path does not meet the

criteria it is unsensitizable and is assumed to not contribute to the delay or function of the

circuit under this sensitization criteria. However, the sensitizability of paths is dependent

7

upon the sensitization criteria. A path which is sensitizable under one criteria may not be

under another. As a result, timing analysis is dependent on the sensitization criteria

chosen. Different sensitization criteria may result in varying estimates of the delay of a

circuit. The sensitization criteria selected greatly influences the quality and usefulness of

a timing analysis tool.

Several properties are considered essential for a good sensitization criteria. The

first is that the sensitization criteria not underestimate the delay of the circuit. That is, for

each path reported as true there must be a path at least as long in the circuit. Tight timing

constraints are realized by overestimating the length of the critical path as little as

possible.

The second property of sensitization criteria stems from the imperfect timing

information of a circuit under test. Conditions such as process parameters during

fabrication and thermal and electromagnetic properties of the operating environment can

affect the delay of the circuit elements. To deal with this process engineers provide a

range of timing values. As a result, the circuit under test is in fact a family of circuits

where the delay of each element varies based on manufacturing and operating conditions.

Each member of this family is topologically and functionally equivalent. The set of total

paths in the circuit can be divided into two groups. The first are those which are

sensitizable in all circuits regardless of delay variations. These paths are said to be robust.

If a sensitization criteria targets these paths it is said to follow the monotone speedup

property[7]. Paths which are non-robust are not sensitizable in all of the family of

circuits. These paths are dependent on the delay of the circuit elements and may be

8

sensitizable under some manufacturing and operating conditions and not under others.

Most sensitization conditions ignore this group of paths.

Sensitization criteria are defined in terms of controlling and non-controlling logic

values. A logic value is considered to be controlling if it can independently determine the

output value of that gate. For example, the controlling value of gate G denoted by c(G) =

Ò0Ó if G is an AND or NAND gate and c(G) = Ò1Ó for OR and NOR gates. Logic values

which cannot independently determine the output of a gate G are non-controlling values

for gate G and are denoted by n(G). In addition, the on-path input to a gate refers to the

input through which the transition propagated from the input to the output along the path

and all other inputs are referred to as side inputs.

In the following pages, several existing sensitization criteria are described. The

necessary conditions for propagating a transition are shown. Some possible drawbacks of

the criteria are discussed with examples where applicable.

1. Static Sensitization

One of the earliest forms of sensitization criteria is known as static sensitization

and was first reported in [8]. This criteria recognizes that for a transition to propagate to

an output a non-controlling value is necessary on the side inputs to the gates on the path.

As a result, static sensitization consists of a single condition. The side inputs to the gates

on the path must be set at their non-controlling values for the entire time it takes the signal

to propagate along the path. It has been recognized in [7, 9] that this criteria may

underestimate the actual delay of the circuit. Consider figure 2, under the static

sensitization criteria input b is required to maintain both a static 1 and a static 0 value.

The 0 value results from the initial OR gate and the 1 value from the final AND gate.

9

This is obviously in conflict and the path would be reported as a false path under this

criteria. However, if input b is a 0 value when input a transitions and changes to a 1

before the path transition reaches the final AND gate then the transition on a would

propagate along the entire path. Such a path is said to be dynamically sensitizable, but

would be claimed to be a false path under static sensitization criteria. For this reason,

static sensitization criteria was claimed to provide a lower bound to the delay of a

circuit[8].

a

bc

de

Figure 2: A Static False Path

Later research realized that static sensitization criteria could also overestimate the

delay of the circuit[9-11]. Consider the circuit shown in figure 3 taken from the example

in [10]. In this circuit the path a-d-e is sensitizable under the static sensitization criteria.

However, it is fairly obvious that no transition occurs at e for either a rising or falling

transition at a. The realization that static sensitization can both overestimate and

underestimate the delay of the circuit led to the introduction of a modification to the static

sensitization criteria in [11].

10

1

0

2

3a b

c

d

e

Figure 3: Overestimation of Static Sensitization

The problem with the static sensitization criteria which causes it to overestimate

the circuit delay is that the conditions do not require a transition to propagate along the

path. For path a-d-e to be statically sensitized b and c must be set to static 0 values. This

does not produce a conflict in the circuit, however it does force input a to be a static value

thus preventing a transition from propagating along the path. A simple solution to this

problem is to require that the side inputs be set to non-controlling values independent of

the primary input to the path. This criteria is introduced as the modified static

sensitization criteria in [11].

11

LogicBlock

G1

G2

1

1

1

11

1

Figure 4: Portion of C432

The modified static sensitization criteria eliminates the possibility of

overestimating the delay of the circuit. Unfortunately, it also claims many more true paths

to be false. This causes the criteria to greatly underestimate the true delay of the circuit.

Figure 4 was drawn directly from ISCAS benchmark circuit c432. It is obvious that the

output to gate G1 is dependent on the primary input transition thus failing the modified

static criteria. However, since the transition on G1 arrives much before the path transition

on G2 a non-controlling value would be present at the time the path transition arrives. As

a result the path would be a true path regardless of the dependency on the primary input.

Static sensitization was the earliest criteria used to eliminate false paths from

timing analysis. Since static values are used on side inputs the criteria meets the condition

of monotone speedup. However, since it is not possible to determine if it overestimates or

underestimates the delay of the circuit the usefulness of this criteria is questionable [9].

12

With the modified static criteria a lower bound to the path delay is guaranteed, but the

condition greatly underestimates the delay of the circuit. As a result this condition is not

very useful.

2. Dynamic Sensitization

In an effort to remedy the underestimation of the circuit delay inherent in static

sensitization, the dynamic sensitization criteria was proposed[7, 12, 13]. For a path to be

dynamically sensitizable the side inputs are required to be non-controlling only at the

arrival time of the transition to the on-path input to the gate. This criteria is much more

exact than static sensitization and would provide the true delay of the circuit if exact

timing information were available. However, as described earlier, timing analysis is

actually performed on a member of a family of circuits. The circuits are functionally and

structurally equivalent, but vary in timing information. In most cases, the worst case

delay of each circuit element is assumed when timing analysis is performed under the

exact delay model.

13

a

w(2)

u(2)

1

2

2

2

v(1)

x

y

out0

2

3

2

02

4

0

0

Figure 5: Dynamic Sensitization Example

The exact delay model assumption for timing analysis causes the dynamic

sensitization criteria to underestimate the delay of a circuit in some cases. That is, by

restricting the delay of each circuit element to its worst case delay it is possible to claim a

path to be false when it is in fact sensitizable for some subset of the family of circuits.

The circuit in figure 5 was used in [7] to demonstrate the possibility for dynamic

sensitization to underestimate the delay of a circuit. In this circuit, with the delay of each

element shown, a rising transition on a at t0 results in a rising transition on w at t2 and a

falling transition on u at time t3. This causes the value on x and the output to the circuit to

remain a constant 0. However, if the delay of element u is reduced to 0 the falling

transition on u occurs at time t1 and a rising transition and a falling transition occurs on x

14

at times t3 and t4 respectively. For this case a non-controlling value is present on x

between t3 and t4 allowing a transition on y to propagate to the output.

In some ways the dynamic sensitization criteria is an improvement over static

sensitization. If the exact delay of the circuit elements was known this criteria would

provide the true delay of a circuit. Even though it is not possible to know the exact delay

of the circuit elements, dynamic sensitization does provide a closer lower bound.

However, it fails to satisfy the monotone speedup property in that the sensitizability of

paths under this criteria is dependent on the delay of the circuit elements.

3. Floating Mode Sensitization

Floating mode sensitization criteria was developed to overcome the drawbacks of

previous sensitization techniques. In this criteria all gates are assumed to be initialized to

a stable, but unknown logic value. To generate a transition a pair of input vectors (V1,V2)

is required. The unknown stable values would be generated by the initial vector V1.

Floating mode sensitization is concerned with the behavior of V2 only. The second input

vector is applied at time t0 and transitions in logic values are propagated throughout the

circuit. Floating mode defines a stable time (ST) for each gate which designates the time

at which that gate reaches a stable value. For example, if a gate G has stable time ST(G)

= t1 then the last transition on G occurs prior to time t1 and gate G maintains a stable value

after that. The following two conditions must hold for a path to be sensitizable under the

floating mode sensitization criteria.

1. If the stable value of the on-path input ei is controlling and has a stable

time ST(ei), then the side inputs must be either a non-controlling stable value

or a controlling stable value with stable time greater than or equal to ST(ei).

15

2. If the on-path input has a non-controlling stable value then each of the side

inputs must also have non-controlling stable values with stable time less than

or equal to the stable time of the on-path input.

This criteria has been shown to be robust in that the requirement that controlling

side inputs arrive later than the on-path inputs prevents long false paths from becoming

sensitizable and masking the true circuit delay. An example of where this might occur

was given for dynamic sensitization. However, floating mode sensitization may claim

some sensitizable paths to be false so long as they are shorter than the longest true path

[9]. Figure 6 presents the circuit used to describe such a situation. In the circuit node f

assumes a controlling value and ST(f) < ST(g). Therefore the path is unsensitizable under

the floating mode criteria, but the falling transition at the input clearly causes a transition

to occur at the output of the circuit.

1

12

22 2

2

a

b

cd

e

f

g h

0 2 4 6

2 4

4 5

Figure 6: Unsensitizable under Floating Mode

16

Of these sensitization criteria floating mode provides the most accurate timing

information. It overestimates the delay, but is more closely bound than other sensitization

criteria. It also satisfies the robustness criteria under bounded delay model. However, this

criteria does have several drawbacks. It may claim paths to be false if they are shorter

than the longest sensitizable path. This becomes a problem when a set of paths is

required. In addition, floating mode is only concerned with the second of the two input

sensitization vectors. It does not determine the input vector required to initialize the path.

C. PATH JUSTIFICATION PROCEDURES

Once a sensitization criteria is selected, path justification is used to determine an

input vector that satisfies all the constraints of the sensitization criteria. This can be

considered as a logic satisfiability problem and is a known NP complex problem. Despite

this several procedures have been developed and applied to the path sensitization problem.

Many of these solutions come from automatic test pattern generation (ATPG) research

which has the similar problem involved with the activation and observation of stuck-at-

faults.

The earliest justification procedure applied to the path sensitization problem was

the D-algorithm[14]. This algorithm used a decision tree to target unjustified gates. At

each unjustified gate a possible justification is selected and implications are performed.

The selection becomes a decision and is added to the list of decisions. If a conflict occurs

the alternate logic values are attempted. If the alternate value also produces a conflict this

decision is removed and the previous decision is inverted. The process continues on

unjustified gates until the circuit is justified. This process works fairly well if the path is

justifiable. However, the process of backtracking the decision tree in the case of a conflict

17

is expensive. As a result, when paths are not sensitizable and the search space must be

exhaustively searched the D-algorithm may require a large amount of computation. This

process was used in [8] to justify paths under the static sensitization criteria.

In [15] the ATPG technique of PODEM [16] was applied to justification of

statically sensitizable paths. This technique differed from the D-algorithm by targeting

only the primary inputs as opposed to each internal node. That is, in PODEM the

unjustified gates are traced back to the primary inputs and only these decisions were

placed on the decision tree and implied throughout the circuit. This algorithm is more

efficient than the D-algorithm, but a systematic enumeration of the search space required

for false paths is still computationally expensive.

The ATPG technique of FAN [17] has also been applied to the path sensitization

problem. This technique is an improvement over both the D-algorithm and PODEM and

combines some qualities of each. The FAN algorithm recognizes that most conflicts

occur at internal fanout points and targets these points in the circuit. The unjustified gates

are traced back to the fanout points which are placed on the decision tree if conflicting

decisions occur. This technique was used in [11] to justify paths under the floating mode

criteria.

In ATPG the problem of excessive backtracks is dealt with by providing a

predetermined cutoff limit. All faults that require excessive backtracks are discarded

resulting in a slight decrease in fault coverage. The results of such a backtrack limit are

much more detrimental in path sensitization. The confidence of circuit delay estimation is

lost if a path is discarded and a shorter path is later found to be sensitizable. The

technique of Recursive Learning [18] is used in [11] to help eliminate discarded paths.

18

Recursive Learning determines indirect implications and given enough time, can

determine all necessary primary input assignments for a set of circuit values. Due to the

computational expense it is applied only when the backtrack limit is reached.

Another technique applied to the false path problem is the use of Ordered Binary

Decision Diagrams (OBDDs)[19]. OBDDs provide a compact representation of the

functionality of combinational circuits. As a result the determination of a primary input

vector which sensitizes the path can be determined without any backtracking. However,

OBDDs have been shown to explode for certain types of circuits. In these cases it is not

possible to construct an OBDD. This technique was used in [20] and [21].

D. PATH DETERMINATION METHODS

Another focus of research for timing analysis has been on the determination of

potential paths. Methods used to produce potential paths can be divided into two main

categories. The first attempts to quickly enumerate structural potential paths. These

approaches are based on the PERT process. A modification to this procedure was given in

[20] which introduced the use of branch slacks and a heap data structure to produce a set

of long paths in order.

The second category attempts to implicitly eliminate false paths. As the number of

false paths in modern digital circuits increases due to the use of logic synthesis and

modular design it becomes increasingly important to use implicit false path elimination.

These algorithms attempt to ascertain the sensitizability of the path during the search

process. Many paths can be eliminated simultaneously by determining the sensitizability

of the partial path early in the search process.

19

One of the earliest algorithms to perform implicit path elimination was described

in [8] and further developed in [22]. This approach used direct implications to look for

conflicts during the search process. When a conflict is found that portion of the search

space is trimmed off. This implicitly eliminates large numbers of false paths. In [21]

potential paths were produced in this manner and sensitization was done to determine the

point in the device parameter space where the delay of the path was maximized and

remained sensitizable.

In [15] ATPG techniques were applied to the path determination problem. In this

approach the special signal values P(N) were used to represent the values 1(0) on a path.

A P value was placed on a PI and propagated throughout the circuit. At any point a list of

the frontier of P(N) values is processed based on a cost function and an objective is

chosen to be pushed toward an output. If a conflict occurs the previous decision is

reversed. This approach processes multiple paths simultaneously, however it cannot

generate the paths in order and does not handle multiple input transitions.

In [23] a powerful FAN based justification routine was developed using Recursive

Learning. This technique was used to determine the minimal constraints which cause

conflicts in false paths. These constraints can then be used to implicitly eliminate large

numbers of false paths. This approach was based on the floating mode sensitization

criteria and was targeted at finding only the longest path, although it could be extended to

find a set of longest paths.

20

III. IMPROVED DYNAMIC SENSITIZATION

Several of the sensitization criteria found in the literature have been described

earlier in this paper. Of all of the criteria, dynamic sensitization provided the most

accurate model of the actual transitions occurring in a circuit. However, dynamic

sensitization has been shown to have several drawbacks.

The most obvious drawback of dynamic sensitization is the dependence on an

exact model for the delay of the circuit. It was shown in [7] that dynamic sensitization

can underestimate the delay of a circuit when nominal or worst case timing information is

used. This problem is exacerbated by the fact that it is not possible to accurately predict

the exact delay of circuit elements. The delay will vary depending on the manufacturing

process parameters and operating conditions.

In addition, dynamic sensitization fails to satisfy the monotone speedup property.

This property was defined in [7]. A criteria meets this property if it correctly determines a

path P1 to be sensitizable, where for each path P2 in any member of the family, the delay

of P1 is at least as long as P2. A criteria that meets the monotone speedup property does

not underestimate the delay of the circuit.

A. UNCERTAINTY INTERVALS

The problems inherent with dynamic sensitization stem from the inability to

exactly determine the delay of circuit elements prior to fabrication and testing of the

actual circuit. However, the delay of these elements is often characterized by engineers

and can be estimated to fall within a certain range. This model is referred to as the

bounded delay model in [10] and treated extensively in [24]. With this model, the delay of

21

each circuit element is represented by a bounded delay [DL(G),DH(G)]. In [9] a

distinction is made between the bounded delay model where DL(G) = 0 and the min/max

delay model where DL(G) is a closer lower bound to the true delay of the circuit element.

In this work the use of min/max gate delay information to improve dynamic sensitization

of paths is studied.

To incorporate the min/max delay information into the dynamic sensitization

criteria the use of uncertainty intervals are proposed. When a transition occurring at time

zero propagates through a circuit element the exact time of the transition on the output of

the circuit element becomes unknown. It occurs at some point between DL(G) and DH(G).

Similarly, a transition which has propagated into the circuit and arrives at the input to a

gate at some point in the interval of tl to t2 will propagate to the output of the gate at some

point in the interval t1+ DL(G) and t2 + DH(G). This is shown in figure 7. In this manner,

assuming DH is larger than DL, uncertainty intervals expand as they propagate forward

through a circuit.

t1 t2t1+DL(G)

t2+DH(G)

G

Figure 7: Expanding Uncertainty Interval

22

B. SENSITIZING UNCERTAINTY INTERVALS

Through the use of uncertainty intervals it is possible to determine if paths are

sensitizable for the entire range of delay values or only for some subset. The case where

paths are sensitizable over the entire range of delay values are referred to as always

sensitizable. Paths which are only sensitizable for a subset of the delay values are referred

to as sometimes sensitizable. These paths may in fact turn out to be unsensitizable if the

combination of delay values required to sensitize the path is not possible. Different

sensitization conditions are required to determine if a path is always or sometimes

sensitizable. These sensitization constraints determine if it is possible to propagate a

transition from a PI to a PO along the path.

1. Always Sensitization Criteria

To guarantee that the path is sensitizable for all possible delay variations maximal

constraints are required. These constraints must propagate the entire uncertainty interval

along the path. In addition, to guarantee that this transition is the final transition along

this path the side input must remain non-controlling when the transition results in a non-

controlling value on the path. This condition is not necessary when the on-path transition

results in a controlling value. Figures 8 and 9 show an example of the always

sensitization criteria for a rising and falling transition on an AND gate.

23

t1 t2

t1+DL(G)

t2+DH(G)

G

Figure 8: Sensitizing a Rising Transition

t1 t2t1+DL(G)

t2+DH(G)

G

Figure 9: Sensitizing a Falling Transition

2. Sometimes Sensitization Criteria

It is also possible to determine if a path is sensitizable for any combination of

delay values. In this case the only requirement is that it be possible for a transition to

propagate through the gate. The entire uncertainty interval is not propagated by the

constraints. This is done by using minimal constraints to propagate the transition along

the path. In the case of a transition to a non-controlling value the side inputs must

stabilize to a non-controlling value by the last possible time that the on-path transition

may occur. This is the minimal constraint required for such a transition to be the final

24

transition along the path. Such a constraint is not necessary to propagate the final value of

a transition to a controlling value. However, it is necessary for the a non-controlling value

to occur on the side inputs for some minimal time prior to the transition in order to

guarantee that a transition occurs on the output of the gate. Since the exact time of the

transition is unknown it is not possible to apply this constraint during the path building. A

check of potential paths must be performed to guarantee that it is possible for the side

input to be non-controlling at the time the on-path input transition occurs. Figures 10 and

11 show an example of the sometimes sensitization criteria for a rising and falling

transition on an AND gate.

t1 t2

t1+DL(G)

t2+DH(G)

G

Figure 10: Minimal Criteria for Rising Transition

25

t1 t2

tx > t1+DL(G)

t2+DH(G)

G

δ

δ

txtx

Figure 11: Minimal Criteria for Falling Transition

C. DEPENDENCE ON DELAY MODEL

The range of values given for the delay of each circuit element is determined by

the delay model chosen to represent the circuit elements. If a minimal range is provided

where the delay of the gate is represented as a single value then no uncertainty intervals

would appear in the circuit. This would result in a sensitization criteria identical to the

classical dynamic sensitization criteria and it would be possible to underestimate the delay

of the circuit as described above. However, the paths which are not sensitizable would be

trimmed off during the path building phase leaving only the paths which are sensitizable

under the given delay values.

Another extreme would be to provide an infinite range of delay values for each

circuit element. This would result in infinite uncertainty intervals at each point in the

circuit. The paths produced under the sometimes and always sensitization criteria would

be very different with infinite uncertainty intervals.

Under the always case the side inputs would be set to non-controlling values for

the entire uncertainty interval. This is equivalent to setting the side inputs to a static value

26

during the path building. This would report statically sensitizable paths where the side

inputs are independent of the primary input transition. It has been shown that static

sensitization underestimates the delay of the circuit [9].

Under the sometimes sensitization criteria it would not be possible to set any

constraints during the path building. This would cause the path building to degenerate

into a structural search of the circuit with a final check required to determine if it is

possible to propagate a transition along the path. This is equivalent to the search process

used by PERT and can overestimate the delay of circuits where false paths exist.

The accuracy of the improved dynamic sensitization technique is dependent on the

accuracy of the min/max delay model. As the range of the min/max delay values

increases more paths will be reported as justifiable at some point in the range of delay

values and fewer will be reported as always justifiable. On the other hand, if the range is

too small to encompass the actual possible delay values on the gate then it becomes

possible to underestimate the delay of the circuit in the same manner as dynamic

sensitization. The best results are achieved by reducing the min/max range as much as

possible, while still encompassing all possible manufactured delay values.

27

IV. PATH GENERATION IN TIMING ANALYSIS

A major component of every timing analysis system is the generation of potential

paths. This path generation is done either through explicitly enumerating all paths [12,

25], or through the implicit elimination of false paths [7, 13, 26]. As modern digital

circuits are tending to contain more false paths it becomes increasingly important to

implicitly eliminate false paths. The explicit elimination of false paths is too costly in the

cases where false paths exist.

Previous work on timing analysis has concentrated on the determination of the

longest functional path in a circuit. This path is said to be the critical path of the circuit

and determine the delay of the circuit. However, as digital circuits are tending toward

many nearly identical length paths and variations in manufacturing process parameters

and operating conditions make it impossible to determine the exact delay of circuit

elements a single critical path cannot be determined. It is necessary to generate a set of

longest paths which contains the critical path set. The set of paths can be further

processed to account for correlation of process parameters, thus reducing the test set size

required to test for global disturbances in process parameters which may affect the delay

of the circuit. In this approach we concentrate on incrementally generating a set of

functional paths which may be used to detect path delay faults. In addition, we propose

several refinements to improve the elimination of false paths.

The method chosen for determining paths allows for operation in batch or

incremental mode. In batch mode the number of paths required is entered at run time and

the program concludes when the required number of paths is reported. In incremental

28

mode additional paths can be generated upon request. The following sections describe the

preprocessing required, the path store used to maintain a list of partial paths, and several

refinements for trimming false paths.

A. PREPROCESSING STEPS

Some preprocessing is required prior to beginning the path generation. During the

preprocessing phase the circuit netlist is loaded and represented as a graph with n primary

inputs and m primary outputs. Each gate, PI, and PO is represented as a node in the graph

with edges representing circuit interconnect. Delay information for each gate is loaded at

this time.

In addition to loading the circuit, some information about each gate is determined

at this time. The first is the maximum distance from each gate to a PO. This value is

calculated at each node in the circuit and represented as Omax(G). The maximum

Omax(G) of all PIs is the delay of the longest structural path in the circuit. This can be

calculated through a simple depth first search.

In addition to the value Omax calculated for each gate, two additional values are

determined during the preprocessing of the circuit. These values represent the earliest

(Imin) and last (Imax) possible time a transition may occur at gate G assuming that any PI

may transition at time zero. This is useful during the implication process. Since

transitions can occur only within the range from Imin to Imax any constraint required on

either side of the range can be extended to cover everything outside the range on that side.

These values are calculated assuming that all primary input transitions will occur at time

zero. However, it is possible to relax this initial condition to allow input transitions to

occur over a range. This will increase the difference between Imin and Imax for each gate

29

in the circuit resulting in reduced constraints applied to the circuit during the path

building.

B. THE PATH STORE

The path generation phase then proceeds with the initialization of the path store.

The store contains the current partial paths that may be extended to potential long paths.

The paths are sorted in order of longest potential delay. This is referred to as esperance in

[26] and calculated as the length of the partial path plus the delay of the current gate plus

the largest potential delay to a PO. In addition, paths with identical esperance are sorted

in order of decreasing distance to a PO. That way larger partial paths which require less

computation to complete will be pushed to an output first. The path store is initialized

with the primary inputs and an esperance equal to Omax for each PI.

The path store is the most memory intensive portion of the implementation. The

representation of the circuit is linear in the size of the circuit. However, the size of the

path store is linear in the number of potential paths which must be stored. During the

traversal of a path of length d where each gate on the path has fanout f the worst case

number of potential paths that must be represented in the store is (f-1)d since the fanout

selected to extend the path does not need to be represented in the store. In most real

circuits the average fanout is fairly small and any fanouts which are blocked do not need

to be represented in the path store. However, it is still possible for the size of the path

store to grow exponentially. When operating in batch mode where the number of paths

required is known the size of the store can be controlled by dropping partial paths which

cannot contribute to the path set. However, this is not possible in incremental mode where

the number of required paths is not known. In this case a maximum is placed on the size

30

of the store and partial paths with the smallest esperance are dropped from the bottom of

the store. The highest dropped esperance is reported to assure that it is smaller than the

length of the path set and would not have contributed to the path set.

C. PATH GENERATION

Each iteration of the path generation routine begins by checking the path store for

the largest partial path with the highest esperance. In this manner the paths can be

generated in decreasing order of path length based on the information available. When a

partial path is selected the fanouts are processed. The path is extended through the fanout

with the highest esperance. All other fanouts are added to the path store.

The requirement to extend a partial path through a gate is that a transition must

propagate to the output of the gate. This is checked by applying the constraints based on

the sensitization criteria to the side inputs of the gate. The constraints of the superset of

paths which are sometimes justifiable are used for the dynamic sensitization case. The

determination if the path is always justifiable is left for the final justification.

31

Start Preprocessing-Calculate O max,Imin ,Imax

Initialize PathStore with PIs

Get Largest PPfrom Path Store

Extend PathApply ConstraintsPerform ImplicationsAdd fanout to Store

Conflict?

End

ReachedPO?

Passjustification?

NO

YESNOYES

NO

YES

Anotherpath?

NO

YES

Figure 12: Incremental Path Generation

Once the constraints have been applied to the current gate direct implications are

used to propagate the constraints throughout the circuit. A direct implication on a gate is

one where an input or output of that gate can be directly determined from the other values

assigned to that gate. The values are assigned to the gate either by the propagation

constraints or by previous direct implications. A conflict is said to occur when an invalid

32

set of assignments exists on a given gate. Conflicts found using direct implications are

referred to as local conflicts. If a conflict occurs a new partial path is retrieved from the

path store and the process continues from there. When a partial path is extended to a PO a

full justification of the path is performed to guarantee that a combination of PIs exist

which will propagate a transition along the path. Additional paths can be retrieved from

the path store and extended to POs until the requested number of paths has been reported.

This can be done interactively with the user requesting additional paths, or in batch mode

where the number of paths is determined at execution time. Figure 12 provides a flow

chart of this procedure. The next section describes several refinements and the following

chapter discusses the final justification procedure.

D. REFINED IMPLICIT FALSE PATH ELIMINATION

The power of the incremental path determination technique is in the ability to

implicitly eliminate false paths from the search space. We have included several

refinements directed toward eliminating false paths earlier. As a result the search process

is improved.

1. Recursive Learning

Recursive Learning [18] is a technique which is able to identify all necessary

assignments required to satisfy a set of value assignments in a circuit. The technique is

directed toward the gates left unjustified after direct implications are performed.

Necessary assignments are computed by temporarily injecting all combinations of

possible values that would justify these gates and observing the result after direct

implication. Any values that are required in all possible justifications are considered

necessary under the current set of value assignments. The technique can be called

33

recursively to compute the necessary assignments for the direct implications of each

previous justification. In this manner, given enough time, recursive learning can compute

all necessary primary input assignments to sensitize the circuit. The time complexity of

this technique grows exponentially in the recursion depth, but memory requirements grow

linearly.

Implicit elimination of false paths is done through the direct implication of the

constraints at each gate along the path. When local conflicts are found further processing

of that partial path is discontinued. If local conflicts do not exist the partial path is

extended to an output. The potential path is not guaranteed sensitizable at this point since

only direct implications were performed which find only local conflicts. Therefore final

justification is required to determine the set of primary inputs necessary to sensitize the

path. False paths that reach a PO must be explicitly eliminated.

Through the use of Recursive Learning indirect conflicts can be found. This

potentially improves the search by detecting false paths earlier than direct implications

alone and reducing the explicit elimination of false paths. However, it was found that the

occurrence of indirect conflicts which were useful for trimming the search was limited.

As a result, the cost of using Recursive Learning in this manner outweighed the benefit for

most circuits.

2. Dynamic Dominator

As a partial path is extended forward constraints are added to side inputs. These

constraints are propagated throughout the circuit. In many cases they will propagate

forward such that the constraints required to propagate a transition are already present on

the side inputs to a gate when that gate is added to the partial path. When this occurs no

34

additional constraints are necessary and the addition of that gate to the partial path has no

effect on the false path determination. If multiple paths are dominated by a single gate

such that no constraints are added between the fanout point and the dominator only a

single path must be determined to be false to eliminate both paths. An example of this is

given in figure 13. This subcircuit is found extensively in ISCAS benchmark circuit

c6288.

x1

x2

x3

x4

0

0 1

0

0

1

Figure 13: Dynamic Dominator

The usefulness of this heuristic is highly dependent on the structure of the circuit.

The most benefit would be derived from a path with d gates each having fanout f where

each fanout reconverges with the path and no constraints are required to traverse any of

the fanouts. This would result in fd possible paths which must be traversed. However, this

technique recognizes that at each gate n only a single fanout must be traversed to test for a

false path. As a result only one of the fd possible paths must be traversed. In the case of

c6288, the subcircuit shown above is repeated 15 times prior to detection of a conflict.

Without the use of dynamic dominators the elimination of 215 paths would be required

instead of a single path.

35

The worst case for this heuristic would result from a path with high fanout where a

constraint is required for the path to traverse any one of the fanouts. In this case the

technique would search each of these fanouts and fail to find a dominator. Each of these

paths would still have to be searched during the path building. A limit is used to prevent

excessive overhead of this technique. A limit of two is sufficient to find the dominator in

the example above providing exponential improvement in c6288 and limited improvement

in other ISCAS circuits while incurring little overhead in circuits where dominators do not

exist.

3. Forward Trimming

In some cases when the constraints are applied and direct implications are

performed the possibilities for extending a partial path to an output are reduced. In the

extreme case the path is blocked completely. During the preprocessing phase the value

Omax(G) was calculated based only on the structure of the circuit. Forward trimming

recalculates this number from the end of the partial path forward, based on the structure

and the current value assignments of the circuit. In this manner blocked paths can be

eliminated earlier and the search can be guided more accurately toward the longest

functional path. Figure 14 shows an example where the path through the logic block

cannot propagate to the output. The path is blocked by the constraint on the input NAND

gate which propagates forward as a controlling value on the output NAND gate. This sets

the value of the output and prevents the transition from propagating along the longest

path. With forward trimming the search process does not traverse the logic block, but

continues through the inverter instead.

36

Logic

Block1

0

1

Figure 14: Application of Forward Trimming

Without forward trimming the search process would have been much less efficient.

Since the path is not blocked until the final NAND gate the search process would have

attempted to traverse through the logic block until it reached the final NAND gate and

determined that the path is blocked. This would be done for each possible path through

the logic block. If the logic block has n gates each with a fanout of f then a maximum of

fn paths would have to be traversed. With forward trimming this entire logic block is

trimmed off and the search is guided toward an unblocked path. Forward trimming is

implemented as a depth first search which executes in linear time on the size of the circuit.

In the worst case blocked paths do not occur and the overhead of forward trimming is

wasted. In cases where blocked paths do not occur it is a simple matter to generate a

potential path. In cases where blocked paths do occur the linear time overhead of forward

trimming is an acceptable tradeoff for the exponential improvement it provides.

37

V. FINAL JUSTIFICATION

Once a potential path is generated it is necessary to perform a full justification of

the path. The reason for this is that only direct implications are performed during the path

building to implicitly eliminate false paths with local conflicts. Indirect conflicts may still

exist which cause a potential path to be false. In addition, the justification is used to

determine a set of primary input values that can be used to sensitize the path. A path is

sensitized if the sensitization criteria is satisfied for all gates on the path under a given set

of input values.

A FAN style decision tree based justification routine is used to sensitize the

potential path. This process begins by applying all the constraints necessary to propagate

a transition along the path. The direct implications are performed and a list of unjustified

gates is accumulated. An unjustified gate is one where one or more inputs or outputs

remain unspecified such that it is possible for a conflict to occur at that gate. Since direct

implications failed to justify these gates multiple possible justifications exist. These

unjustified gates become the current objectives and are targeted during the justification

routine.

The decision routine selects a current objective and chooses a possible justification

for it working toward the PIs. This gate then becomes a new current objective. The

process of selecting current objectives and choosing a justification is continued until either

a fanout point is reached or a PI is reached. If conflicting assignments are required on a

fanout point the decision process is ceased and that decision is returned. If a PI is reached

38

the decision is added to the head objectives. When the list of current objectives is empty

then a head objective decision is returned.

The justification routine then assigns the value to the gate returned by the decision

routine and performs direct implications in the circuit. If a conflict occurs the previous

decision and implications are removed from the circuit. If the inverted value has not been

attempted then it is applied to the circuit, otherwise the decision is removed from the list

of decisions and the previous decision is inverted. If no conflict occurs the list of

unjustified gates is updated and the process continues until either the decision tree is

exhausted and the path is reported as unjustifiable or no unjustified gates exist and the

sensitized path and input vector is reported.

An additional iteration is needed when dynamic sensitization with uncertainty

intervals is used to determine if the path is justifiable for the entire range of delay values.

The minimal constraints for sometimes justifiable paths were used during the path

building phase. If the final justification fails with these constraints then the path is not

justifiable. If it passes then the path is determined to be justifiable for some combination

of delay values. The constraints are then increased to those required for the path to be

justifiable over the entire range of delay values. Justification of the path is then repeated

to determine if the path is justifiable for the entire range of delay values.

39

VI. RESULTS

The incremental path sensitization approach described in chapter four has been

implemented along with the implicit path elimination techniques of Recursive Learning,

dynamic dominator, and forward trimming. Experiments were performed using static,

modified static, and dynamic sensitization with uncertainty intervals. These techniques

were implemented in over 10,000 lines of C++ code. Execution was performed on a

SPARCserver 1000 with 128 MByte of main memory. The ISCAS 85 combinational

benchmark circuits [27] were used as input for the static sensitization experiments using a

unit delay model. For experiments on the dynamic sensitization with uncertainty intervals

a conservative minimum and maximum representation of circuit element delay was

required. To achieve this the standard cell MCNC layouts of the ISCAS circuits were

used. Simulations were performed on the standard cells to determine the minimum and

maximum delay. This information was then used in conjunction with an extracted netlist

description of the layouts to test the improved dynamic sensitization criteria.

A. MODIFIED STATIC SENSITIZATION

The modified static sensitization routine required that the side inputs to the path be

set at the non-controlling value and be independent of the primary input transition. This

requirement resulted in extremely optimistic delay estimations for the ISCAS benchmark

circuits. Under this criteria, excessive numbers of long false paths existed which must be

eliminated prior to finding the circuit delay. As a result, a large amount of processing is

required to determine the longest sensitizable path under the modified static criteria. Due

to the extremely optimistic nature of the results this model was discarded. In addition, it

40

was found that the cost of using Recursive Learning during the path determination was

greater than the benefits achieved through its use.

B. STATIC SENSITIZATION

The static sensitization criteria produced sensitizable paths much closer to the true

delay of the circuit. Table 1 shows the results of experiments for the ISCAS benchmark

circuits using the basic incremental search routine and using the dynamic dominator

technique to trim the search space. The table lists the structural (SPL) and functional

(FPL) path length for each of the ISCAS circuits. In addition to the execution time, the

number of conflicts in direct implications(Cd), and the number of blocked paths(Cb) are

given for each circuit. The sum of Cd and Cb represent the number of times the program

is forced to retrieve a new partial path from the path store during the path determination

process. It can be seen from the table that the dynamic dominator technique improves the

search process for several circuits. The execution time is improved for c2670 and for

c6288 which did not complete using only the basic approach. In the cases where the

technique did not improve the search only a minimal overhead was required.

41

Table 1: Static Sensitization with Dynamic Dominators

Circuit SPL FPL Basic Dynamic Dominator

time(s) Cd Cb time Cd Cb

c432 17 17 .77 32 4 .77 32 4

c499 11 11 .09 0 3 .10 0 3

c880 24 24 .08 0 0 .09 0 0

c1355 24 24 .33 0 5 .36 0 5

c1908 40 37 121.1 0 1488 121.9 0 1488

c2670 37 30 103.8 0 776 59.1 0 640

c3540 47 45 10.78 12 110 12.4 12 110

c5315 49 47 6.75 2 61 8.5 2 57

c6288 124 123 * 181.3 0 270

c7552 43 40 55.54 8 179 59.4 8 172

In table 2 the results are shown for determination of the longest statically

sensitizable path using the forward trimming technique and a combination of both

techniques. Through comparison of the results using forward trimming with the results of

the basic approach given in table 1 it can be seen that forward trimming provides a

marked improvement for nearly all of the ISCAS benchmark circuits. The program did

not complete in reasonable time for c6288 using forward trimming alone, but combining

both techniques further improved the search process for this circuit.

42

Table 2: Static Sensitization with Forward Trimming

Circuit SPL FPL Forward Trimming Both

time(s) Cd Cb time(s) Cd Cb

c432 17 17 .66 32 0 .81 32 0

c499 11 11 .05 0 0 .08 0 0

c880 24 24 .12 0 0 .16 0 0

c1355 24 24 .25 0 0 .33 0 0

c1908 40 37 8.81 0 0 8.99 0 0

c2670 37 30 39.68 0 208 37.21 0 208

c3540 47 45 5.19 8 2 6.21 8 2

c5315 49 47 5.37 2 0 3.69 2 0

c6288 124 123 * 56.81 0 0

c7552 43 40 26.99 8 3 26.83 8 3

In table 3 the results for gathering the 100 longest paths using the static

sensitization criteria are presented. In most cases the execution time required is

significantly less than 100 times the time required to determine a single path. This is most

significant in cases such as c2670 where many paths larger than the longest path must be

eliminated prior to finding the longest path. This does not have to be repeated for

subsequent paths. In some cases such as c6288, the time required per path is greater then

for the first path. This occurs when paths which are difficult to justify are encountered

and the time spent performing justification increases.

43

Table 3: 100 Static Paths

Circuit SPL FPL 100 Paths

time(s) Cd Cb

c432 17 17 11.11 287 0

c499 11 11 9.77 0 0

c880 24 24 9.62 0 0

c1355 24 24 16.77 0 0

c1908 40 37 141.3 0 0

c2670 37 30 79.62 0 208

c3540 47 45 129.1 165 128

c5315 49 47 52.38 5 4

c6288 124 123 19690 2 0

c7552 43 40 123.6 10 8

C. DYNAMIC SENSITIZATION WITH UNCERTAINTY INTERVALS

The third set of experiments were performed using the dynamic sensitization

criteria with uncertainty intervals. These experiments were executed on the ISCAS format

netlists extracted from the MCNC benchmark layouts. Simulations of the standard cells

used in the MCNC layouts were performed to determine the minimum and maximum

delay. Process parameter variations were accounted for to determine conservative

minimum and maximum delay values for use in these experiments. The worst case delay

values are used when reporting the structural and functional path lengths.

Table 4 shows the results of dynamic sensitization using the basic incremental

algorithm alone and with the dynamic dominator technique. This combination of

conservative min/max delay values and the dynamic sensitization criteria results in fewer

44

constraints applied during the path building phase. As a result most potential paths are

extended to the output where they must be justified. Final justification is performed using

the sometimes sensitization criteria to determine if it is possible to sensitize the path for

some subset of the delay values. If this test passes, then the justification procedure is

repeated using the always sensitization criteria to determine if the path is sensitizable for

the entire range of delay values. With the conservative min/max delay values there is a

large difference between the constraints applied by these two criteria. The result is that

most reported paths are sometimes justifiable with a couple of exceptions. Circuit c880 is

well know to be an easy case and it is reported that this path is always justifiable. The

longest path in circuit c2670 is also reported as an always sensitizable path. However,

several paths were discarded as not justifiable before this path was found. This resulted in

the increased execution time shown in Table 4. Since most potential paths are directly

extended to the output the usefulness of dynamic dominators is diminished. However,

noticeable improvement in execution time and reduction in blocked paths was shown on

circuit c1355 with the use of this technique.

45

Table 4: Dynamic Sensitization with Dynamic Dominators

Circuit SPL FPL S A basic Dynamic Dominator

time(s) Cd Cb time(s) Cd Cb

c432 37.23 37.23 1 0.20 0 1 0.26 0 1

c499 18.53 18.53 1 0.09 0 0 0.09 0 0

c880 16.74 16.74 1 0.30 0 0 0.45 0 0

c1355 22.84 22.76 1 2.15 0 25 1.41 0 12

c1908 37.21 36.66 1 0.49 0 1 0.54 0 1

c2670 49.79 49.33 1 49.26 0 3 50.75 0 3

c3540 57.43 55.38 1 3.83 1 9 3.97 1 9

c5315 46.36 46.36 1 0.35 1 1 0.44 1 1

c6288 99.11 99.06 1 2.72 1 1 2.78 1 1

c7552 121.47 120.80 1 0.56 0 0 0.57 0 0

In addition to the dynamic dominator technique, the dynamic sensitization criteria

was tested using forward trimming alone and combined with the dynamic dominator

technique. Table 5 shows the results of these experiments for each of the ISCAS

benchmark circuits. The forward trimming technique shows slight improvement in

execution time and number of blocked paths during the execution on circuit c1908 and

c3540. However, since most paths are extended to the output and determined to be

sometimes justifiable very little overall improvement is gained by these techniques under

this sensitization criteria.

46

Table 5: Dynamic Sensitization with Forward Trimming

Circuit SPL FPL S A Forward Trimming both

(1) time(s) Cd Cb time(s

)

Cd Cb

c432 37.23 37.23 1 0.25 0 1 0.28 0 1

c499 18.53 18.53 1 0.08 0 0 0.09 0 0

c880 16.74 16.74 1 0.34 0 0 0.32 0 0

c1355 22.84 22.84 1 2.70 0 25 1.73 0 12

c1908 37.21 36.66 1 0.39 0 0 0.55 0 0

c2670 49.79 49.33 1 51.67 0 3 61.15 0 3

c3540 57.43 55.38 1 3.45 1 3 3.44 1 3

c5315 46.36 46.36 1 0.44 1 1 0.50 1 1

c6288 99.11 99.06 1 4.72 1 1 3.98 1 1

c7552 121.47 120.80 1 0.98 0 0 1.02 0 0

In table 6 the results for collecting 100 paths using the dynamic sensitization with

uncertainty intervals are presented. In addition to the timing and conflict information, it is

reported if the paths are sensitizable over the entire range of delay values or only for some

subset of the delay values. The functional path length shown is the path length of the one

hundredth path. Since most paths are extended directly to the output the execution time of

these experiments was expected to be near one hundred times the execution time of the

single path. Variations from this result from the additional execution time required to

complete justification for paths which are always justifiable, processing of paths which are

not justifiable, and additional blocked paths and conflicts which are encountered during

the search for the one hundred paths.

47

Table 6: 100 Dynamic Paths

Circuit SPL FPL S A 100 Paths

(100) time(s) Cd Cb

c432 37.23 34.95 97 3 30.09 71 129

c499 18.53 18.19 89 11 49.88 0 31

c880 16.74 14.58 0 100 63.07 0 0

c1355 22.84 21.90 90 10 110.10 32 155

c1908 37.21 33.86 100 0 44.55 7 30

c2670 49.79 48.13 37 63 1556 19 21

c3540 57.43 51.37 100 0 294.50 139 127

c5315 46.36 41.39 91 9 60.61 74 20

c6288 99.11 98.01 100 0 1193 52 9

c7552 121.47 84.49 51 49 161.9 27 8

48

VII. CONCLUSION

A. SUMMARY

To compete in todayÕs marketplace, designers have been forced to push digital

circuits to new levels of performance and quality. However, these opposing goals are

difficult to achieve. Higher performance designs require tighter timing constraints which

are more difficult to verify. These circuits also tend to have many paths of nearly

identical length which must be tested. In addition to the performance and quality goals,

designers must reduce time-to-market in order to be successful. This is, in part, achieved

through the use of automated logic synthesis and modular design. These techniques result

in increased numbers of nonfunctional paths which would previously have been

eliminated during the manual circuit design process. On top of this, the increased

complexity of advanced VLSI technology has made it difficult for any designer to

understand the timing of an entire circuit. For all of these reasons both the importance and

the difficulty of timing analysis has increased.

In this work, timing analysis of logic-level digital circuits has been studied.

Special emphasis has been placed on improving the implicit elimination of false paths

during the search process. The techniques studied for improving the elimination of false

paths include Recursive Learning, forward trimming, and dynamic dominators. Results

were given to demonstrate the effectiveness of these techniques.

Recursive Learning was applied to the search process to look for indirect conflicts

during the path search. These conflicts would be missed by simple direct implications

resulting in false paths being extended to the outputs. Not until final justification is

49

performed would these paths be determined to be false. This was found to be of little use

and in most cases the cost of using Recursive Learning in this manner outweighed the

possible benefits. Most false paths were found using only direct implications during the

search process. Very few paths failed the final justification procedure.

The second technique used to improve the path search process was the use of

dynamic dominators. This technique looked for multiple reconvergent paths where no

additional constraints were applied between the fanout and fanin point. When this occurs

it is only necessary to determine if one of them is a false path. It was found that in circuits

such as c6288 where such a structure is repeated many times an exponential improvement

in performance is achieved. In circuits where such structures do not exist this technique

provides no benefit, however it does not require much overhead.

The third technique used to improve the search process is forward trimming. This

technique recomputes the maximum distance from each node in the fanout cone of the last

node on the partial path to the outputs. This value is used to guide the search toward the

longest path. Through the use of forward trimming the search is guided more accurately

toward the longest path and away from blocked paths. This technique provides limited

improvement during execution on nearly all ISCAS benchmark circuits. Substantial

improvement was noticed on c1908 where the search process was blocked many times

without forward trimming.

In addition to these techniques for improving the search process, a new

sensitization criteria was presented. This criteria involved the use of uncertainty intervals

to represent the region where a transition is known to occur when a range of possible

delay values is assumed for each circuit element. The criteria for paths to be sensitizable

50

over the entire range of delay values was presented. Also, the reduced constraints

required for a path to be sensitizable for some subset of delay values is described. This

technique provides a more accurate representation of the switching characteristics of a

circuit. It also generates both input vectors required to test such a path even if multiple

input transitions are required.

B. FUTURE WORK

An immediate extension of this work is the determination of the longest functional

path through a single gate. This should be possible simply by constraining the search

space to nodes in either the fanin or fanout cone of that gate. This would greatly reduce

the search space resulting in the elimination of fewer false paths which should improve

the performance. Such paths are useful in testing for gate delay faults.

In addition, it should be possible to modify the approach to determine the shortest

paths in a circuit. This would require modifications of the sensitization criteria and the

search procedure. The sensitization criteria would have to be inverted to guarantee that

the transition propagated is the first transition to pass through a gate instead of the last one

which is currently found. The search procedure would simply have to be modified to start

with the structural path with the smallest esperance and work up instead of starting with

the largest esperance and working down. Determination of the shortest path is useful in

asynchronous or multiclock systems where assumptions are made about the minimum

path length.

The dynamic sensitization criteria with uncertainty intervals presented in this work

depends on the accuracy of the minimum and maximum delay values provided for each

circuit element. A large range of delay values results in expanded uncertainty intervals

51

and reduced constraints on the circuit. Since the size of the uncertainty region is additive

along each gate of the path a slight increase in the size of the delay range results in a large

increase in the size of the uncertainty interval at the output of the path. Alternatively, a

slight reduction in the range of delay values would greatly reduce the size of the

uncertainty intervals and increase the constraints on the circuit. Future research should be

directed toward reducing the delay range.

A possible method for reducing the size of the uncertainty intervals is to recognize

the dependencies within the circuit. The delay of a gate is influenced directly by

transitions on its inputs and indirectly by transitions and logic values elsewhere in the

circuit. In addition, variations in delay due to process parameters are often correlated

across a wafer. As a result the delay of circuit elements will tend to have similar variation

from the nominal gate delay value. It may be possible to incorporate some of this

information in the search process to reduce the expansion of the uncertainty intervals and

increase the constraints on the circuit. This would reduce the number of paths which are

reported as justifiable for some combination of delay values. Additional processing is

currently needed to determine if a combination of delay values is possi