Time Borrowing And Clock Skew

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Time Borrowing

And Clock Skew

SUBMITTED BY:-

Sarbjeet Singh

ECE Regular 2011

Roll No. 616

NITTTR CHD

PRESENTED BY Sarbjeet Singh

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Objective

Time BorrowingClock SkewIEEE PAPER

ResultsConclusions

Sarbjeet Singh

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Time Borrowing

• In a flop-based system:Data launches on one rising edgeMust setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges

• In a latch-based systemData can pass through latch while transparentLong cycle of logic can borrow time into nextAs long as each loop completes in one cycle


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Time Borrowing Example

Latc

h

Latc

h

Latc

h

Combinational LogicCombinational

Logic

Borrowing time acrosshalf-cycle boundary

Borrowing time acrosspipeline stage boundary

(a)

(b)

Latc

h

Latc

hCombinational Logic Combinational

Logic

Loops may borrow time internally but must complete within the cycle

1

2

1 1

1

2

2


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How Much Borrowing?

Q1

L1

1

2

L2

1 2

Combinational Logic 1Q2D1 D2

D2

Tc

Tc/2 Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

borrow setup nonoverlap2cT

t t t

2-Phase Latches

borrow setuppwt t t

Pulsed Latches


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Clock Distribution

Clock

Cannot really distribute clock instantaneously

with a perfectly regular period


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Clock Skew: Spatial Clock Variation

Clock SkewDifference in clock arrival time at two spatially distinct points

A

B

A

B

Skew

Compressed timing path


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Clock Skew

We have assumed zero clock skew

Clocks really have uncertainty in arrival timeo Decreases maximum propagation delayo Increases minimum contamination delayo Decreases time borrowing


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Review: Skew Impact

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tskew

CL

Q1

D2

F1

clk

Q1

F2

clk

D2

clk

tskew

tsetup

tpcq

tpdq

tcd

thold

tccq

setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

• Ideally full cycle isavailable for work

• Skew adds sequencingoverhead

• Increases hold time too


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Skew: Latches

Q1

L1

1

2

L2 L3

1 12

CombinationalLogic 1

CombinationalLogic 2

Q2 Q3D1 D2 D3

sequencing overhead

1 2 hold nonoverlap skew

borrow setup nonoverlap skew

2

,

2

pd c pdq

cd cd ccq

c

t T t

t t t t t t

Tt t t t

2-Phase Latches

setup skew

sequencing overhead

hold skew

borrow setup skew

max ,pd c pdq pcq pw

cd pw ccq

pw

t T t t t t t

t t t t t

t t t t

Pulsed Latches


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Skew Tolerance

Flip-flops are sensitive to skew because of hard edgesData launches at latest rising edge of clockMust setup before earliest next rising edge of

clockOverhead would shrink if we can soften edge

Latches tolerate moderate amounts of skewData can arrive anytime latch is transparent


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Solutions

• Reduce clock skew– Careful clock distribution network design– Plenty of metal wiring resources

• Analyze clock skew– Only budget actual, not worst case skews– Local vs. global skew budgets

• Tolerate clock skew– Choose circuit structures insensitive to skew

• Post-fabrication adjustment– Intel, IBM, etc


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Quan Yuan , Hai-gang Yang , Fang-yuan Dong , Tao Yin, “Time Borrowing Technique for Design of Low-Power High-Speed Multi-Modulus Prescaler in Frequency Synthesizer” ,IEEE International Symposium on Digital Object Identifier, pp. 1004 - 1007, 18-21 May 2008.


IEEE PAPER

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Abstract

A low power continuous phase-switching multimodulus prescaler is proposed, based on a “time-borrowing” method.

In this phase-switching control strategy significantly reduces the delay of the phase-switching control loop so the multi-modulus prescaler can work with higher input frequencies and obtain the maximum modulus for a lower power supply.

Such a multi-modulus prescaler fabricated in a 0.35μm CMOS process divides the 2.4GHz input frequency by 48 up to 64 for a minimum power supply voltage of 2.5V.

Its maximum power dissipation is only 4.85mW.


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Existing Prescaler Model

First


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• The problem with this prescaler is that ,the VCO of a frequency synthesizer is estimated to typically consume more than 50% of the total PLL power.

Second

• The asynchronous prescaler is based on the phase-switching technique.


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• It has two divide-by-2 stages in cascade and only the first divide-by-2 flip-flop operates at the highest input frequency.

• But , it may suffer from unwanted glitches.

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• To remove the glitches, a re-timer circuit is added to properly synchronize the input signals of the phase switching block, which unfortunately increases the circuit complexity and hence consumes more power and area.


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Proposed Multi-Modulus Prescaler• The proposed continuous phase-switching multi-modulus prescaler with

the “time borrowing” method

• The idea is to prepare some intermediate signals in advance before the next phase is selected.

• The delay of the whole phase switching control loop TLOOP = TAND + TCON + TSEL .

• The pulse-generator and the four divide-by-2 stages are parts of the phase-switching control loop, but their delay do not appear in the TLOOP.

• This is done through use of the low-level part of the current phase in the phase-switching output signal (F4).

• Thus, the delay time over the phase-switching control loop can be minimized so the control signals (CON) would quickly become available.


04/12/2023 12:13 AM 20PRESENTED BY Sarbjeet Singh

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Divide-By-2


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Phase Controller


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Phase selector


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Pulse Generator


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Layout


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Results


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Conclusions

The delay of the phaseswitching control loop can be reduced significantly.

Prescaler works at a frequency up to 2.4GHz at a 2.5V supply with the division range of 48-64 and its maximum power dissipation is only 4.85mW.

Our design has demonstrated a considerable improvement in terms of the power-to-speed ratio.


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Refferences

A. Wafa and A. Ahmed, “High-Speed RF Multi-Modulus Prescaler Architecture for Fractional-N PLL Frequency Synthesizers,” 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), pp. 241-244, May 2004.

Quan Yuan , Hai-gang Yang , Fang-yuan Dong , Tao Yin, “Time Borrowing Technique for Design of Low-Power High-Speed Multi-Modulus Prescaler in Frequency Synthesizer ” ,IEEE International Symposium on Digital Object Identifier, pp. 1004 - 1007, 18-21 May 2008.

http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1329347


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???Qus


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Thank you


Time Borrowing And Clock Skew

Education

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