Tile Input Options for Phase-1

Tile Input Options 1

Tile Input Options for Phase-1

• Topic in a nut-shell:– Phase-1 FEXes receive digital signals from upgraded LArg

(new FE plus DPS)– Tile does not upgrade until Phase-2– Need to maintain legacy analogue path until FEXes are fully

commissioned– What is the best input route for Tile to FEXes?

• Thanks to many people who contributed to these slides and discussion

14th May 2013


PRELIMINARIES

14th May 2013


The Three Options

• Numbering consistent with twiki below

14th May 2013

TCPP PPM JEMTileCal L1A

FEXes L1AHow to connect?

RX

https://twiki.cern.ch/twiki/bin/viewauth/Atlas/TileInputOptions


Option 1: ‘Tile DPS’• Requires splitting of signals at TCPP• Tile DPS modules similar to LArg DPS

14th May 2013

NewTCPP PPM JEMTileCal L1A

Tile DPS FEXes L1A

RX



Option 2: PPM RTM• Requires new RTM for PPM• Also requires new LCD daughter-card

14th May 2013


FEXes L1A

RTM

RX



Option 3: JEM• Requires new JEM daughtercard• Also same upgrade to PPM LCD daughtercard

14th May 2013


FEXes L1A

RX



The overall picture

14th May 2013


IDR review request

• Establish a process, using external expertise, to evaluate the three options presented for directing Tile Calorimeter signals into jFEX. The evaluation should factor in the technical and funding risks, and the resources available to implement the options. A baseline should be established before the TDR.

• Passing note: need input to eFEX and jFEX!

• Will first review what steps we’ve taken

• Then move onto details of findings

14th May 2013


Review procedure


• Set up a group of 10 members drawn from L1Calo, TDAQ, Tile, Larg and outside, with representation of each of the options– Christian Bohm, Philippe Farthouat, Stephen Hillier, Francesco Lanni, Robin Middleton,

Thilo Pauly, Srini Rajagopalan, Carlos Solans Sanchez, Uli Schafer, Hans-Christian Schulz-Coulon

– Plus several ‘ex-officio’• Martin Aleksa, Phil Allport, Chris Bee, Ana Henriques Correia, Stefano Veneziano, Martin Wessels

• Regular meetings on a Friday subsequent to presentations in TDAQ week – https://indico.cern.ch/conferenceDisplay.py?confId=232458

14th May 2013


Criteria for Decision• Establish a process, using external expertise, to evaluate the three

options presented for directing Tile Calorimeter signals into jFEX. The evaluation should factor in the technical and funding risks, and the resources available to implement the options. A baseline should be established before the TDR.

• Technical feasibility• Disruption to existing system• Installation and commissioning effort• Latency• Physics performance• Cost and effort requirements

14th May 2013


Time-scale for decision


• Note: Planning for MoU also requires a decision

• TDR timescale is short– Partial TDR time-line Robin Middleton has proposed for the L1Calo sections

• 23rd April: Draft 0.1• 31st May: Baseline Finalized• 15th June: Full Draft for L1Calo Feedback

14th May 2013


Original proposed milestones• Monday 25th March

– Agree process and encourage continuing investigations, such as:• Each system to study design for the important criteria• Finalize physics studies of LSB choice and noise

• Wednesday 10th April– Dedicated meeting in TDAQ week with open discussion– Decide if more work and open meetings required

• Post-TDAQ week– Core group to meet and discuss as required– Ask for additional information if needed

• ATLAS Upgrade week: May 13th – 17th – Report from core group to be presented

• Initially in joint Calo/TDAQ meeting– Aim for agreement from all sides

• End of May: Upgrade Steering Group– Decision presented and finalized

14th May 2013

TODAY


MORE DETAILS ON OPTIONS:A FEW KEY FEATURES

14th May 2013


Option 1: Tile DPSData branching

• Replace 64 TCPPs in 4 crates

• 256 Tile input cables

• 128 calo output cables

• 128 muon output cables

• Add ADCs and digital output

14th May 2013


Option 1: Tile DPSData processing

14th May 2013

• Use pre-existing LArg DPS technology and crates

• Similar (if not identical) infrastructure, algorithms, firmware etc

• Just 1 or 2 extra DPS modules• Option to include Tile D-layer

from Day-1– Possible advantages for jet punch-

through


Option 2 and 3:Double speed data transmission

• Both options require more data out of PPM

• Achieved via new MCMs (2015) and new LCD (2018)

• Internal double data rate already tested with nMCM

• 32 PPMs in two crates require new LCD

14th May 2013


Option 2:Data Branching via PPM REX

• New RTM for 32 PPMs in two crates

• Contains FPGA for data conversion and optical outputs

• Legacy digital cables as before, signals pass through RTM

14th May 2013


Option 3:Data branching via JEM

• JEM receives double data rate in new input daughtercards

• Three of these retransmit optical signals

• Signal transmission over 11m LVDS cables to be tested

14th May 2013


EVALUATION

14th May 2013


Group evaluation of options

• Initially I summarized my thoughts• We sought extra input on some items

– Though not all issues can be addressed on this time-scale• Looked in more detail at some topics• Discussed evaluations• Christian Bohm set up twiki for documentation and

comments– Evolved with input from several people

• Upcoming slides are a summary of the twiki as it stands

14th May 2013



General remarks

• Option 1 digitization is a new development, where we already have a digitization solution that is known to be working– But it is no tougher than than the LArg FE upgrade

• The output of each option to eFEX and jFEX should be identical, no matter the route to get there– For the core Tile towers anyway, and it should be similar to HEC

output

• Most of the rest of the twiki addresses the criteria for the decision

14th May 2013


Technical Feasibility

• The ‘active-TCPP’ has not yet been demonstrated, particular in its effect on the legacy signals– But, as before, this solution is similar to the LArg FE, and should be no more

difficult• Transmission of double data rate over LVDS has yet to be

demonstrated for Option 3– Though some of the path is already tested with the nMCM, so Option 2 is

closer to being proved

• Overall, none of the solutions look to be ‘challenging’– Solutions near at hand, or at least if the solution does not work, then Phase-

1 Upgrade is already in trouble• No reason to believe any option is harder than the others14th May 2013


Disruption to existing system/Installation and commissioning effort

• Option 3 appears to be favoured– Purely replacement of daughter-cards– Small amount of extra optical cabling, but this is necessary anyway for all solutions

• Option 1 and 2 require re-cabling– Option 1: at least 384 analogue cables in four crates– Option 2: about 500 LVDS cables in two crates

• Re-cabling in both cases will mean adjustment to strain relief– From bitter experience, handling lighter LVDS cables is a lot easier than the heavy

analogue cables• Daughter-card replacements can be done in small quantities

– TCPP replacement likely to be one crate at a time (at least)

• Note, even with differences, probably small perturbation to overall disruption in LS2 due to LArg upgrade and addition of FEXes

14th May 2013


Latency

• Latency will be tight, and this is a key criteria• For Option 2 and 3, latency for signals to FEXes will be a

2-3 BCs more than current availability at processors– Inevitable with addition of optical encoding

• Estimates for Option 1 in line with LArg processing and other options– Probably no big difference to other routes

• Conclusion: though latency is critical, there’s probably not a big difference in the three options

14th May 2013


Physics Performance• This divides into two areas:

– Can we improve the signal quality to the processors?– Does extra data (Tile D-layers) help the trigger?

• Signal Processing– New filters, correction techniques may improve performance

• Flexibility not available with currents MCMs• But these are already being replaced in 2015

– Comparison of processing resources in FPGAs• Tile DPS will use advanced powerful FPGAs

– But each one is expected to process several hundred channels– Possible advantage by cross-correlating with other channels

• PPM nMCMs are smaller, but only process four channels each– Overall, PPM will have more processing resources

14th May 2013


Physics Performance• This divides into two areas:

– Can we improve the signal quality to the processors?– Does extra data (Tile D-layers) help the trigger?

• Tile D-layer– Could be available in Tile DPS from day-1

• Slightly more expensive, baseline comparison is without this option– For Option 2 or 3 could provide this data, but only when legacy system de-

commissioned– Possibility to improve jet resolution?

• Note that signals were designed for muon output• High gain, saturate at 12 GeV

• Judge that there may be some advantage in Option 1– But usefulness is yet to be proven

14th May 2013


Cost Requirement

• Comparison of options without D-layer– Core costs only

• For details see the backup slides– Option 1: €145,000– Option 2: €80,000– Option 3: €110,000

• Of course all these depend on exact choice of FPGAs etc

14th May 2013


Effort Requirement

• To be honest we haven’t gone into this in detail– And we are all at the whim of funding agencies

• However, worth assessing likely available effort– Option 1: Strong expectation that support for this

will be funded and bring in new effort– Option 2: Effort clearly available within PPM group– Option 3: PPM effort again clear, but JEM effort will

be split between this and other upgrade projects• Note this commits effort to long-term maintenance of

PPMs/JEMs

14th May 2013


Impact on Phase-2 Upgrades

• Bold statement that hasn’t been challenged

• There should be no impact– This is purely a stop-gap solution for LS2 to LS3– Hardware will be ‘junked’ in LS3

• So vice-versa, I argue that there’s no Phase-2 ‘synergy’ argument for any option

14th May 2013


Summary Table

• Caveat: Differences, where they have been identified, are not necessarily very large1 = best, 3 = worst

14th May 2013

Item Option 1 Option 2 Option 3 Comment

Feasibility = = =

Commissioning 3 2 1 Small cf LArg Upgrade

Latency = = =

Physics Perf. 1 2 2 Need to study D-layer

Cost 3 1 2

Effort = = = Availability of JEM effort?

Phase-2 Impact = = =


Conclusion

• The core group has not reached a full consensus– Though there was a preference among many for Option 3 at the last

meeting• We would be grateful for further insights from this meeting

today– Ideally we would reach a decision

• Otherwise, we will meet again next week to decide how to proceed– Again ideas welcome– One option is to write a short document to be made available for a

small group to make a decision– Still would like to finish this in time for the Upgrade SG

14th May 2013


BACKUP

14th May 2013

Tile Input Options 3314th May 2013

Tile Input Options 3626th April 2013

Tile Input Options for Phase-1

Documents

Transcript of Tile Input Options for Phase-1