Threshold Voltage Control through Layer Doping of Double Gate … · 2010-10-04 · Index...

240 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.3, SEPTEMBER, 2010

Manuscript received May. 24, 2010; revised Sep. 24, 2010. * Dep. Physics, Pavanatma College, Kerala, India, 685604. ** Research & PG Dep. Phy, St. Thomas College, Palai, Kerala, India. E-mail : [email protected]

Threshold Voltage Control through Layer Doping of Double Gate MOSFETs

Saji Joseph*, George James T.*, and Vincent Mathew**

Abstract—Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

Index Terms—DG MOSFET, layer doping, counter doping, threshold voltage, leakage current

I. INTRODUCTION

The intimate coupling between the gates and the channel enables the Double Gate MOSFET (DG MOSFET) effectively control the short channel effects (SCEs), and makes it the most scalable of all MOSFET designs [1]. In particular, DG MOSFET with an intrinsic channel is considered to be the best candidate for device downscaling, as it possesses advantages such as (a) absence of the dopant fluctuation effect, which contributes to the variations of the threshold voltage and drive current [2-10] and (b) enhanced carrier mobility owing to the absence of depletion charges which can significantly contribute to the effective electric field, thus degrading the mobility [11]. However, intrinsic channel DG MOSFETs need to rely solely on gate work function to achieve multiple threshold voltages on a chip due to the absence of body doping, which is an efficient tool to adjust the threshold voltage in DG MOSFETs with doped channels [11, 12]. In the past few years, many efforts including implanted metals [13], fully silicided gates [14-16], alloy metals [17-19], novel high-κ dielectric materials [20] and metal bilayers [21] have been reported, but none has been completely successful in integrating metals with tunable work function in DG MOSFETs due to technological difficulties [22]. Therefore, DG MOSFETs with suitably doped channels seem to be the easiest option from a fabrication point of view, and are seriously being investigated to set appropriate threshold voltages [12, 23, 24].

Although heavy channel doping can suppress SCEs to some extent and fix threshold voltage, it has already been established that such high doping will severely degrade

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.3, SEPTEMBER, 2010 241

the mobility in the channel and increase leakage current caused by the band to band tunneling (BTBT) from the channel to the drain [25], and will contribute to threshold voltage rolloff resulting from the significant discrete dopant fluctuation effect [26]. Therefore, the possibility of using body doping as a tool in DG MOSFETs to tune the threshold voltage seems very limited.

In this work, we present a device structure which incorporates the high mobility and less leakage current of the intrinsic channel device as well as the threshold voltage tunability of the doped channel device. The proposed device is identical to the conventional DG MOSFET in all respects, except that a layer of channel silicon along the transport direction is moderately doped. This doped layer in the channel of the device provides simultaneously, an intrinsic region having reasonably high mobility, less leakage current due to BTBT, less dopant fluctuation effect etc., and a doped region capable of setting the threshold voltage to the desired value. The advances in doping technology such as atomically controlled chemical vapor deposition [27-29] make it possible to control the concentration and location of doping profiles in extremely thin layers of Si channels very precisely and to limit the thickness of the doped layers to within a few atomic layers. The results of our simulations have shown that the characteristics of this novel device are superior to that of a device with a fully doped channel.

In the following sections, we compare the transport properties and threshold voltage tunability of such layer-doped DG MOSFETs. Section II discusses the structure of the DG MOSFET with layer doping and the simulation scheme employed to obtain the transport characteristics of such a device. In section III, the effect of both p-type and n-type layer doping of the channel on important device parameters is presented and compared with that of the devices with intrinsic channels and doped channels.

II. DEVICE STRUCTURE AND SIMULATION

SCHEME OF LAYER-DOPED DG MOSFET

The structure of the proposed device is a double gate MOSFET with heavily n-doped (ND=1020 cm-3) source and drain regions. Si is the channel material and SiO2 is

the gate dielectric with metal gate contacts. Two thin layers of the channel close to the top and bottom gate oxide layers parallel to the transport direction are moderately p/n-doped as shown in Fig. 1(a) (gate-layer devices). The doping level of these two layers of Si can be adjusted independently to set the threshold voltage. The intrinsic layer between the two doped layers will act as a region of high mobility for charge transport. Alternately, it is also possible to design a channel with p/n-doped region at the middle and the intrinsic layers on either side, close to the gate oxide films as in Fig. 1(b) (mid-layer devices).

In order to study the effect of doping one or two thin layers of the channel of the DG MOSFET, we simulated a device with channel length (LG) 15 nm, and total channel thickness (TSi) 4 nm. The total channel thickness, which includes the thickness of the doped layer(s) and the intrinsic layer(s), is kept constant when devices with different doped-layer thickness are simulated. The oxide thickness is kept at 1 nm for all devices so as to keep the

(a)

(b)

Fig. 1. Layer-doped Double Gate MOSFET structures. (a) A gate-layer doped structure where two thin layers of the channel close to the top and bottom gates are doped, while the middle layer is left undoped and (b) a mid-layer doped structure where a thin layer in the middle of an otherwise intrinsic channel is doped.

242 SAJI JOSEPH et al : THRESHOLD VOLTAGE CONTROL THROUGH LAYER DOPING OF DOUBLE GATE MOSFETS

gate tunneling effects minimum. We assume a metal gate contact with work function 4.21 eV and the source and drain regions included in the simulation domain are 3.2 nm in extension having a uniform doping of 1020 cm-3. In the simulation, the doping profile of the source, drain, and the layers of the channel are assumed to be abrupt. The channel layers are lightly doped in comparison with the source and drain regions, and the doping concentration in the channel layer(s) is assumed to be uniform.

The simulation scheme used to investigate the characteristics of the layer doped DG MOSFET is identical to that has been used previously for the modeling of DG MOSFETs in the nanometer regime [30-32]. This scheme involves a self-consistent solution of a 2D transport equation (in our investigation, the Non Equilibrium Green's Function (NEGF) equation, as it incorporates all the quantum effects in the nanometer regime) and the Poisson equation with floating boundary conditions to obtain the current density and the potential profile in the device [33, 34]. To reduce the computational burden involved with the finite difference method without sacrificing accuracy, the uncoupled mode space method [35] is employed. The extremely small channel length of the device is comparable with the mean free path of the electrons, and hence the effect of scattering is not very significant at these dimensions. This fact justifies the use of ballistic transport that has been assumed in the simulations [36].

III. EFFECT OF LAYER DOPING THE DG

MOSFET CHANNEL

To study the effect of p/n-layer doping on DG MOSFETs, devices with uniformly p/n-doped gate layers (gate-layer doped devices) or p/n-doped mid layer (mid-layer doped devices) illustrated in Fig. 1 are simulated. Simulated structures have different doping concentrations and widths for their channel layers, but all other device parameters including the channel length, total channel width etc., are kept constant for easy comparison. To compare the characteristics of a gate-layer doped device with that of a mid-layer doped device, the mid-layer thickness of mid-layer doped devices are taken to be twice the gate-layer thickness of the gate-layer doped

devices, as there are two doped gate-layers of equal thickness in the latter devices.

Fig. 2(a) compares the gate characteristics of DG MOSFET having p-doped layer with that of an intrinsic channel DG MOSFET and a DG MOSFET with fully p-doped channel for different layer thickness under a drain bias of 600 mV and a layer-doping concentration NA=3×1019 cm-3. It is obvious that the drain currents of mid-layer and gate-layer devices lie between that of the undoped device at the top and that of the fully doped device at the bottom. The major effect of the p-doping is to increase the threshold voltage as the layer thickness increases. The marked decrease of the leakage current is evident in the subthreshold region of Fig. 2(a). It is clear that the drain currents are almost same for mid-layer doped devices and gate-layer doped devices if the doped mid-layer width is twice the doped gate-layer width, that is, for devices having equal doped layer width. However, for mid-layer devices of comparatively smaller doped layer width, the drain current is slightly less than that for

(a)

(b)

Fig. 2. Gate characteristics of a layer-doped DG MOSFET with (a) p-layer doping and (b) n-layer doping for different doped layer thickness.


the corresponding gate-layer devices. For larger layer widths, the current is larger for mid-layer devices. This odd behavior could be explained by analyzing the lateral potential profiles of the two device structures as depicted in Fig. 3(a). This potential profile is taken in the channel midway between the source and drain regions, along a plane normal to the transport direction. From Fig. 3(a), it is clear that the potential at the channel centre of a p-doped mid-layer device is lifted up in comparison with a similarly doped gate-layer device of identical layer width. More importantly, this lifting up of potential is more pronounced in devices of smaller layer width when compared with that of larger layer width devices. Near the gate contacts, however, the potential lowers down almost identically for mid-layer devices of all layer widths. The increase in the electron density near the gate contacts brought about by the lowering of potential of the mid-layer device is offset by its decrease at the centre

due to the lifting up of potential there. This happens so because the electron density of DG MOSFETs of these extremely small dimensions is not limited to regions close to the gate oxide layers, but is more or less uniform throughout the channel, unlike in the case of bulk MOSFETs. Thus, for mid-layer doped devices of small layer width, the overall electron density and hence current density is slightly lowered as a result of the decrease in the electron density at the centre of the channel brought about by the relatively larger potential rise. But, for mid-layer devices of larger layer width, the relatively small decrease in the electron density at the centre is completely offset by the larger increase near the oxide layers resulting in an overall increase in electron density and hence, current density.

The decrease in leakage current of the p-doped LDDG MOSFET in comparison with an intrinsic channel device, and the reduction in leakage current with an increase in the width of the layers as obvious from the subthreshold regions of Fig. 2(a) could be explained by the analysis of the potential along the channel in the transport direction as shown in Fig. 3(b), which is the potential barrier seen by an electron in the source for different layer widths having the same doping concentration. It is clear from Fig. 3(b) that as the width of the p-doped layer is increased, not only the height of the barrier, but also the extension of the barrier in the channel along the transport direction where it is greater than the potential level of the source increases. This increase in the height as well as width of the potential barrier with p-doping exponentially reduces band-to-band tunneling from channel to the drain (BTBT), and accounts for the sharp decrease in the leakage current when the transistor is off. But, this increase in the height of the potential barrier also reduces the on-current as evident from the saturation regions of Fig. 2(a).

Fig. 2(b) compares the gate characteristics of a DG MOSFET having an n-doped layer for different layer thickness with that of an intrinsic channel DG MOSFET and a DG MOSFET with fully n-doped channel under a drain bias of 600 mV, for a constant layer doping concentration of 8×1018 cm-3. The drain currents of mid-layer and gate-layer devices are larger than that of the undoped device, but less than that of the fully doped device. The major effect of the n-doping is to decrease the threshold voltage as the layer thickness increases.

(a)

(b)

Fig. 3. Potential profile of a layer-doped DG MOSFET (a) in the vertical direction midway between the source and drain and (b) along the transport direction midway between the upper and lower gates, for different channel thickness of n/p-doped layers.


The marked increase of the leakage current is evident in the subthreshold region of Fig. 2(b).

The increase in both leakage current and on-current with an increase in the layer width of the n-doped gate-layer and mid-layer devices could be explained by the reduction in the height as well as width of the potential barrier when the layer thickness is increased, as shown in Fig. 3(a).

Fig. 4(a) compares the drain current of a DG MOSFET having a p-doped layer for different doping levels of the mid/gate layers with that of an intrinsic channel DG MOSFET under a drain bias of 600 mV, for a constant layer thickness. In gate-layer devices, the thickness of each doped layer is 1.2 nm, while for mid-layer devices the thickness of the doped mid-layer is 2.4 nm, so as to keep the total width of the doped region in both devices the same. From Fig. 4(a) it is evident that the drain current decreases with increase in doping concentration, as with the increase in layer width discussed before. But, for devices with same layer

thickness, the difference in drain currents of gate-layer and mid-layer devices does not vary as the doping concentration changes. This could be explained by the potential profile shown in Fig. 5(a) for mid-layer and gate-layer devices of total doped layer thickness 2.4 nm having different doping concentrations. The lateral potential of mid-layer devices gets lifted up at the centre of the channel, but the corresponding lifting up of potential in gate-layer device near the oxide layers exactly matches this effect. As the electron density in DG MOSFET is uniformly distributed across the width of the channel, this lifting up of potential identically lowers the electron density and hence current density in both gate-layer and mid-layer devices. Thus the difference in drain currents for mid-layer and gate-layer devices remains a constant for a given layer width at all doping concentrations.

(a)

(b)

Fig. 4. Gate characteristics of a layer-doped DG MOSFET with (a) p-layer doping and (b) n-layer doping for different doping concentrations of layers.

(a)

(b)

Fig. 5. Potential profile of a layer-doped DG MOSFET (a) in the vertical direction midway between the source and drain and (b) along the transport direction midway between the upper and lower gates, for different doping concentrations of n/p-doped layers.


Fig. 4(b) compares the drain current of a DG MOSFET having an n-doped layer for different doping levels of the mid/gate layers with that of an intrinsic channel DG MOSFET under a drain bias of 600 mV, for a constant layer thickness. An increase in the doping concentration of the mid/gate layer increases the drain current. This increase of drain current with an increase in layer doping is obvious in Fig. 5(a) where the potential of the n-doped mid-layer device lowers down at the centre in comparison with that of the n-doped gate-layer device for different doping concentrations, while the potential of the n-doped gate-layer device near the gate oxide region lowers down in comparison with that of the mid-layer device. This lowering of the potentials at different regions of the channel accounts for the almost same currents observed in mid-layer and gate-layer devices of the same doping level. However, in both mid-layer and gate-layer devices, the effect of n-doping is to lower the potential throughout the channel in comparison with that of the intrinsic channel, accounting for the increase in drain current with layer doping. This lowering is most pronounced in fully doped devices, giving the largest drain current.

The reduction in the leakage current and on-current with the increase in the doping level of the p-doped layers observed in Fig. 4(a) could be explained by the increase in the height as well as width of the potential barrier when the p-doping level is increased, as shown in Fig. 5(b). In a similar way, the increase of these device parameters with an increase in n-doping concentration could be explained by the reduction in the height and width of the potential barrier shown in Fig. 5(b) for n-doped devices.

Fig. 6 shows the variation of the threshold voltage Vt of the mid-layer and gate-layer devices for different doping levels and layer widths. The threshold voltages of the p-doped devices, from its undoped device value of 0.153 V, exhibit a linear increase at low doping levels and sharper increase at higher doping levels for devices with thicker doped layers, including fully doped channel device, whereas a linear increase of the threshold voltage for thinner doped layer devices. This is because, for devices with thick doped layers, at low doping levels, the body is fully depleted and the potential at the centre of the silicon film is not fixed. Thus, the potential inside the silicon film moves as a whole along with the applied gate

voltage in the subthreshold region [37]. As the doping level further increases to a certain level, the centre potential of the silicon film remains unchanged even under large gate voltages. In that case, the depletion width becomes shorter than half of the silicon film thickness, i.e. the device becomes partially depleted. The threshold voltage shift under this condition is no longer a linear function of the doping level. For thin layer devices, the doping level of the very thin layer does not have much influence in fixing the potential at the centre of the thicker intrinsic silicon film, and the potential inside the silicon film moves as a whole along with the applied gate voltage in the subthreshold region, even when the thin layer is not fully depleted, giving a linear response of the threshold voltage with doping level.

The reduction in the threshold voltage of the n-doped devices as exhibited in Fig. 6 has been previously reported for fully n-doped channel DG MOSFETs [23], but the reduction in threshold voltage for DG MOSFETs with counterdoped layer(s) is less pronounced and accompanied with less leakage current when compared with fully counterdoped devices. In n-doped devices, usually the threshold voltage refers to the voltage at which one can clearly observe non-zero drain current on a linear scale [23]. But, as some authors have pointed out [38], this constant-current (CC) method suffers from the ambiguity arising due to the arbitrary choice of the critical drain current Id0 (usually scaled by W/Lg), at which the value of Vt is measured. Therefore, the critical currents for devices of different doping levels and layer widths are uniquely defined as the drain current when the gate voltage is the threshold voltage obtained by the

Fig. 6. Variation of the threshold voltage with change in doping concentration of the layers of varying thickness of a layer-doped DG MOSFET.


linear extrapolation of the drain current to zero at maximum transconductance in the linear region of operation (low Vds) [39]. The threshold voltage at any high drain voltage is then calculated as the gate voltage corresponding to this critical drain current. The threshold voltages of the n-doped devices calculated in this manner exhibit a linear decrease with doping concentration and layer width, as the simulated devices are having relatively less doping concentration (1018 cm-3) when compared with p-doped devices (1019 cm-3).

Fig. 7 plots the ION-IOFF ratio as a function of doping level extracted from the drain current characteristics of Fig. 2 for different layer widths of the gate-layer and mid-layer devices. As is evident from the figure, the ION-IOFF ratio increases exponentially with the increase in p-doping concentration for gate-layer and mid-layer devices. The increase is more pronounced in devices with wider doped layers. However, the ratio is more or less the same for gate-layer and mid-layer devices with the same total layer width and doping concentration. The ION-IOFF ratio decreases exponentially for n-doped devices as the doping concentration increases, and the decrease is more pronounced for devices with larger layer widths.

Fig. 8 plots the transconductance gm of the device as a function of doping level extracted from the gate characteristics for different layer widths of the gate-layer and mid-layer devices. As is evident from the figure, gm

increases in a linear manner with the increase in n-doping concentration for gate-layer and mid-layer devices. The increase is more in devices with wider

doped layers for a given doping concentration, but gm remains the same for gate-layer and mid-layer devices with the same total layer width and doping concentration. gm decreases linearly for p-doped devices as the doping concentration or the layer width increases, and the effect is most significant for devices with fully doped channels where at a doping concentration of 4×1019 cm-3, gm falls to 1.1×103 S/m from its undoped channel value of 15.6×103 S/m.

A similar change in the value of drain conductance gd is observed when the gate-layer and mid-layer devices are n/p doped as shown in Fig. 9. Drain conductance of p-doped channel decreases while that of the n-doped channel increases with an increase in doping concentration or layer width of the devices. As in the case of transconductance, the effect is most significant for devices with fully doped channels.

Fig. 10 shows the variation of the subthreshold slope

Fig. 7. Variation of Ion-Ioff with change in doping concentration of the layers of varying thickness of a layer-doped DG MOSFET.

Fig. 8. Variation of transconductance gm with change in doping concentration of the layers of varying thickness of a layer-doped DG MOSFET.

Fig. 9. Variation of drain conductance gd with change in doping concentration of the layers of varying thickness of a layer-doped DG MOSFET.


for n/p doped gate-layer and mid-layer devices at different doping levels and layer widths. From the figure it is evident that the degradation of the subthreshold slope for a DG MOSFET with fully n-doped channel is very large when compared with an n-doped gate-layer or mid-layer devices of the same doping level. The degradation of subthreshold slope is identical for gate-layer and mid-layer devices, and at high doping concentrations, both devices show an exponential increase in the subthreshold slope. This severe degradation of the subthreshold slope at high doping levels is most pronounced in fully doped channels. The subthreshold value improves almost linearly for p-doped devices from its undoped channel value of 82.13 mV/decade as the doping level increases. This improvement is identical for gate-layer and mid-layer devices and is more pronounced for devices having wider doped channel layers. Thus, for a device with total doped layer width of 1.6 nm subthreshold slope is 71.5 mV/decade at a doping concentration of 5×1019 cm-3, whereas for a device with total doped layer width of 3.2 nm subthreshold slope is as small as 67.7 mV/decade at the same doping concentration.

IV. CONCLUSIONS

This paper describes the effect of doping either some portion or whole of the channel of a symmetric DG MOSFET. Two different layer doped device structures,

viz., gate-layer devices where two narrow layers close to the oxide layers are n/p doped, and mid-layer devices where a layer of the channel at the centre is n/p doped while the layers nearer to the gate are left undoped, are simulated in addition to the ‘conventional’ intrinsic channel DG MOSFETs and fully doped DG MOSFETs. An increase in threshold voltage is observed if those layers are p-doped, with an accompanying decrease in leakage current when compared with an intrinsic channel device. But p-doping also reduces the on-current. However the decrease in on-current is less for a layer doped device than that for a full body doped device. Thus a p-layer doped device provides good threshold voltage control, something lacking in intrinsic channel DG MOSFETs, along with greater on-current than that is observed in full body doped devices.

Counterdoping of the layer with donor atoms can decrease the threshold voltage as in full body n-doped DG MOSFETs, but the degradation of the subthreshold swing and increase of leakage current are less in layer doped DG MOSFETs. Because of the further decrease in the threshold voltage, which is a problem to be addressed in device downscaling, and due to the increase in leakage current and degradation of the subthreshold voltage, counterdoping of the channel is not advisable to set the threshold voltage of the transistors in a chip, despite the increase of drain current, transconductance and drain conductance. However, these degrading effects of n-doped gate-layer or mid-layer devices are less pronounced when compared with full body doped devices. Thus, n/p doping a narrow layer rather than doping the entire channel is a better option to tune the threshold voltage while maintaining larger drive current and less leakage current.

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Saji Joseph received his M.Sc. degree in Physics from the Mahatma Gandhi University, India. He is currently pursuing the PhD degree in nanoelectronics at the Research & Postgraduate Department of Physics, St. Thomas College, Palai, India. He

was lecturer in Physics in Newman College, Mahatma Gandhi University from 1996 to 1997. In 1997 he joined the Faculty of Physics of Pavanatma College, Mahatma Gandhi University and presently is an Associate Professor there. His research interests include the investigation of alternate device geometries for the downscaling of MOSFETs.


George James T. was born in Kerala, India, in 1967. He received the M.Sc. degree in Physics in 1990 and M.Phil. degree in Condensed Matter Physics in 1991 from the Pondicherry University, Pondicherry, India. He is currently pursuing the PhD degree in

the Research & Postgraduate Department of Physics, St.Thomas College, Palai, India. He is an Associate Professor in Pavanatma College, Mahatma Gandhi University, India. His research interests include Quantum transport, Mosfet modeling and simulation.

Vincent Mathew was born in Kerala, India in 1968. He obtained B.Sc and M.Sc in Physics from the Mahatma Gandhi University, Kerala, India in 1988 and 1990 respectively. He received PhD in Electronics from the University of Delhi in 1998. He later

joined the Research & Postgraduate Department of Physics, St. Thomas College Palai, Kerela as a Lecturer and is presently involved in teaching and research in the field of Quantum Electronics, Surface plasmons, and Modeling of carrier transport through nanodevices.

Threshold Voltage Control through Layer Doping of Double Gate … · 2010-10-04 · Index...

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