Three-phase soft-switched pwm inverter for motor drive application

Three-phase soft-switched PWM inverter for motordrive application

J. Shukla and B.G. Fernandes

Abstract: A novel soft-switched inverter topology in which three mutually coupled inductors at atime are involved in the resonance process is proposed. By the introduction of magnetic couplingbetween three resonant inductors, the zero-voltage instants for the inverter can be generated by oneauxiliary switch. Also, the resonant energy can be recycled, and the maximum voltage stress on theauxiliary circuit diode components is confined to the DC-link clamp voltage level. The DC link canbe clamped to 1.1–1.3 times the DC-source value. This is unlike the soft-switched inverter in whichtwo mutually coupled inductors are at a time are involved in a resonance process [14], wherein theclamping diode experiences voltage stress of the order of 11 per unit when clamping the DC-linkvoltage at 1.1 per unit. The proposed inverter also provides pulse-width modulated operation. Ananalysis of this novel quasi-resonant DC-link inverter topology is presented to reveal its soft-switching characteristics. Simulation and laboratory experiments are performed to validate theanalysis.

1 Introduction

Quasi-resonant inverters offer several advantages comparedwith resonant DC-link inverters [1–3] with regard toresonant link design and control, device rating requirementsand use of pulse width modulation (PWM). Over the years,extensive research work has been carried out in the field ofquasi-resonant DC-Link (QRDCL) PWM inverters [4–17].The QRDCL inverter schemes generate zero-voltage (ZV)instants in the DC link at controllable instants that can besynchronised with any PWM transition command, thusensuring a ZV switching condition of inverter devices. As aresult, these inverters can be operated at high switchingfrequencies with high efficiency.

Among the different types of QRDCL inverter schemereported in the literature, the category of inverters in whichan inductor is connected between the DC link and the DCsource are particularly suited for high-frequency and high-power applications [10–17]. This is owing to the fact thatthese inverters do not have a high-frequency resonantswitch in the main power path of the inverter. However,higher DC-link voltage stress [11], a high auxiliary switchingdevice count [13] and the requirement of a separate low-voltage DC source to clamp the DC link [15–17] are themain limitations of these schemes.

One of the QRDCL inverter topology falling into thiscategory is the passively clamped QRDCL (PCQRDCL)inverter reported in [14]. This topology (shown in Fig. 1a)can be considered to be a state-of-the-art QRDCL schemesatisfying most of the essential requirements, such as lowclamp factor, simple resonance control, guaranteed zero-link voltage condition, PWM capability, use of only oneauxiliary switch and recycling of resonant energy. It wasshown that, by the introduction of magnetic coupling

E-mail: [email protected], [email protected]

The authors are with the Electrical Engineering Department, Indian Institute ofTechnology – Bombay, Powai, Mumbai-400076, India

r The Institution of Engineering and Technology 2007

doi:10.1049/iet-epa:20050539

Paper first received 31st August 2005 and in final revised form 25th May 2006

IET Electr. Power Appl., Vol. 1, No. 1, January 2007

between two resonant inductors, the zero-voltage instantscan be generated by only one auxiliary switch. Also, the DClink can be clamped at 1.1–1.3 per unit, and resonant energycan be recycled. The only drawback of this scheme was thehigh reverse voltage requirement of the clamp diode. Thevoltage-blocking capability of this diode is of the order of 11per unit for a clamping factor of 1.1 per unit. This problemcan be solved by use of a separate, low-voltage DC source.However, realisation of this low-voltage DC source is itself aproblem. In the case of a battery-operated inverter, the clampdiode can be connected to a separate low-voltage batterygroup. In the absence of a battery source, the realisation, of aseparate, low-voltage DC source becomes difficult.

Another possible solution could be to use a DC–DCregulator or a simple R-C parallel circuit to maintain lowvoltage (refer to Fig. 1b). The use of a DC–DC regulatorincreases the component count and control complexity.Also, if the DC–DC regulator is not capable of feeding theprocesses resonant energy back to the DC source, then thisenergy is dissipated in resistor. This reduces overallefficiency of the inverter. An optimum strategy in whichDC–DC regulator maintains a separate low voltage forclamping purposes and also feeds back the clamp energy tothe DC source has yet not been reported in the literature.

Hence, the objective of this paper is to design a QRDCLinverter circuit using one auxiliary switch, in which themaximum voltage stress in all semiconductor diodes isconfined to the DC-link clamp voltage level ðVcÞ. Also, theresonant energy associated with the clamping action isrecovered without the use of an extra switching circuit.Such a QRDCL inverter scheme is shown in Fig. 2, inwhich three mutually coupled inductors are used to achievethe above features. Only one auxiliary switch is used togenerate zero-voltage instants for the inverter switchingdevices.

2 Principle of operation

Through the introduction of magnetic coupling betweenthree resonant inductors (L1, L2 and L3), as shown inFig. 2, the zero-voltage instants for the inverter can be

93

i1

i2

i3

VC

IO

IM

S’cS’b

Sa Sb Sc

S’a

Vs+ +

L1

L3D3

C

L2

S2

D2

i2

VC

IO

+

i3

i1

IM

S’cS’b

Sa Sb Sc

S’a

Vs+ +

CS2

D2

L2

D3

L1

S

a b

Fig. 1 Invertersa Passively clamped QRDCL inverter with mutually coupled inductors proposed in [14]b Quasi-resonant inverter using separate low-voltage DC source for clamping purpose [14]

generated by one auxiliary switch. Also, the current in theauxiliary inductor L2 can now reverse during the resonantcycle. Thus switch S2 can be turned off under the ZVcondition. Clamping is provided by a large filter capacitorCF, which acts as a low-voltage DC source whose averagecurrent in steady state is zero. The entire resonant energyassociated with the clamping circuit is recycled. This can beeasily observed from the waveform of current iCF flowingthrough CF, as shown in Fig. 4. At steady state, the areaenclosed by its discharging current (area A1) is equal to thearea enclosed by its charging current (area A2). The voltageacross CF ðvCF Þ attains a value equal to ðK � 1ÞVs, where Kis the clamping factor and lies in the range of 1.1–1.3. ThisDC voltage across CF is analogous to a separate low-voltage DC source, as seen in a few QRDCL schemesreported in the literature [14–17]. Assuming that the inverteris feeding an inductive load (which can be represented by aconstant current source), the steady-state DC voltage across

Fig. 2 Proposed quasi-resonant DC-link inverter using threecoupled inductors

i1

VC RCR

i2Vs

+

i3

CF

VC F

+

D1

S2D2

L2

L1

D Io

+

D3

L3

Fig. 3 Simplified equivalent circuit of proposed QRDCL inverter

94

CF depends on the values of L1, L2, L3 and CR and thecoupling coefficients of mutually coupled inductors k12, k23and k13.

Fig. 4 Resonant link waveforms


3 Analysis and modes of operation

Operation of the proposed QRDCL inverter can beexplained by reference to Figs. 2–5. The various modes ofcircuit operation are described as follows.

3.1 Mode 0 ðt0 � t � t1Þ: pseudo steady-state mode (S2, D1, D2 and D3 off)During this mode, the inverter is said to be in pseudosteady-state mode. The resonant circuit formed by L1 andCR oscillates. The voltage vCR across capacitor CR alternatesbetween Vc¼ KVs and ð2� KÞVs. Also, the inductor currenti1 oscillates around the inverter input current (representedby a constant current source Io), and the magnitude of thisripple is ðVs� VcÞ=o1 L1, where o1 ¼ 1=

ffiffiffiffiffiffiffiffiffiffiffiL1 CRp

. The DC-link voltage vCR settles to Vs owing to the finite resistance ofthe resonant components. This mode of operation ends attime t1, when S2 is turned on under the ZV condition toreduce the DC-link voltage vCR to zero. If we neglect theresistance of the circuit, the state equations of this mode aregiven by

iL1t � t0ð Þ ¼ Vs� Vcð Þ=R01ð Þ sin o1 t � t0ð Þð Þ þ Io ð1Þ

vCR t � t0ð Þ ¼ Vs� Vs� Vcð Þ cos o1 t � t0ð Þð Þ ð2Þwhere R01 ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiL1=CR

pand o1 ¼ 1=

ffiffiffiffiffiffiffiffiffiffiffiL1 CRp

. Initial condi-tions for this mode are vCRðt0Þ ¼ Vc and iL1

ðt0Þ ¼ Io.

3.2 Mode 1 ðt1 � t � t2Þ: link voltagereduces sinusoidally (S2 on; D1, D2 andD3 off)With S2 on, the resonance between L1, L2 and CR causes CRto discharge. Current flowing through L1 decreasessinusoidally, and that flowing through L2 increasessinusoidally. When voltage across CRðvCRÞ becomes equalto the sum of vCF and the voltage induced in L3, D3 turnson, and this mode of operation ends. The equations forlink voltage and currents during this mode can be derived

Fig. 5 Equivalent circuits during various modes of operation


as follows:

vCR t � t1ð Þ ¼ VsL1 þ L2 þ 2M12

� �

� L2 þM12ð Þ þ L1 þM12ð Þ coso t � t1ð Þ½ �ð3Þ

i1 t � t1ð Þ ¼ Io þVs

o L1 þ L2 þ 2M12ð Þ

� �

� o t � t1ð Þ � L1 þM12ð Þ L2 þM12ð ÞL1 � L2 �M2

12

sino t � t1ð Þ� �

ð4Þ

i2 t � t1ð Þ ¼ Vso L1 þ L2 þ 2M12ð Þ

� �

� o t � t1ð Þ þ L1 þM12ð Þ2

L2 � L2 �M212

sino t � t1ð Þ" #

ð5Þ

where, o ¼ 1=ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiL12 � CRp

, L12 ¼ ðL1 � L2 �M212Þ=ðL1þ

L2 þM12Þ and M12 ¼ k12ffiffiffiffiffiffiffiffiffiffiffiffiffiL1 � L2

p. Initial conditions for

this mode are vCRðt1Þ ¼ Vs, i1ðt1Þ ¼ Io, and i2ðt1Þ ¼ 0. Theduration of this mode is given as

t2 � t1ð Þ ¼ 1

ocos�1

�AB

� �� ð6Þ

where

A ¼ Vcþ M23 þM13ð Þ � L2 þM12ð Þð ÞVsL1 þ L2 þ 2M12

B ¼

VsðM23ðL1 þM212Þ �M13ðL1 þM12ÞðL2 þM12Þ

�ðL1 þM12ÞðL1L2 �M212ÞÞ

ðL1 þ L2 þ 2M12ÞðL1L2 �M212Þ

95

3.3 Mode 2 ðt2 � t � t3Þ: link voltagecontinues to decrease sinusoidally (S2 andD3 on; D1 and D2 off)A resonant circuit consisting of mutually coupled inductorsL1, L2, L3 and CR is formed. Capacitor CR continues todischarge. This mode of operation ends when CR dischargesto zero. The equations governing this mode are

L1di1dtþM12

di2dt�M13

di3dtþ 1

CR

Z t

0

ði1ðtÞ

þi3ðtÞ � i2ðtÞ � IoÞdt ¼ Vs ð7Þ

L2di2dtþM21

di1dt�M23

di3dt� 1

CR

Z t

0

ði1ðtÞ þ i3ðtÞ

�i2ðtÞ � IoÞdt ¼ 0 ð8Þ

L3di3dt�M31

di1dt�M32

di2dtþ 1

CR

Z t

0

ði1ðtÞ

þi3ðtÞ � i2ðtÞ � IoÞdt ¼ vCF ð9Þwhere M13 ¼ k13

ffiffiffiffiffiffiffiffiffiffiffiffiffiL1 � L3

p, M23 ¼ k23

ffiffiffiffiffiffiffiffiffiffiffiffiffiL2 � L3

p, M12 ¼ M21,

M23 ¼ M32, and M13 ¼ M31. Initial conditions for this modeare i1 ¼ i1ðt2Þ, i2 ¼ i2ðt2Þ, i3 ¼ 0 and vCR ¼ vCRðt2Þ. It wasfound that this mode of operation occurs for a negligiblesmall interval of time. From Fig. 4, it can be observed thatthe duration of this mode is very small compared with thetime taken by the DC-link voltage to reduce to zero fromsource voltage value (which itself is small). Thus the changein currents i1, i2 and i3 during this mode is negligibly smalland can be neglected. Also, as the area enclosed by currentiCF during this mode is negligible, the contribution of thismode towards steady-state DC-voltage build-up across CF

is neglected. A situation in which three mutually coupledinductors are involved in a resonance process with CRoccurs twice during the entire circuit operation. One suchsituation occurs during this mode, and another occursduring mode 4 of operation (discussed later). During mode4 of operation, such a situation lasts for a longer durationand, hence, is not neglected.

3.4 Mode 3 t3 � t � t4ð Þ: zero link voltagecondition (S2 on and D2 off; inverterfreewheeling diodes on; D3 on; D1 off)During this interval, the freewheeling diodes in the inverterlegs represented by D start conducting. Link voltage isclamped at 0V, and the inverter devices can be turnedon/off under zero-voltage condition. A linearly increasingdischarge current iCF flows out of the positive electrode ofcapacitor CF. Current flowing through L1 increases linearly,and that flowing through L2 decreases linearly. Owing tomagnetic coupling between L1 and L2, current flowingthrough freewheeling diodes across the PWM inverterswitches decreases linearly. This mode of operation endswhen current flowing through the freewheeling diodesreduces to zero. The equation for link voltage and currentscan be derived as

vCR t � t3ð Þ ¼ 0 ð10Þ

i1 t � t3ð Þ ¼ i1 t2ð Þ

þt � t3ð Þ L2 M13 �M12 M23ð ÞvCF þ L2 L3 �M2

23

� �Vs

� D

ð11Þi2 t � t3ð Þ ¼ i2 t2ð Þ

þ t � t3ð Þ L1 M23 �M12M13ð ÞvCFþ M13M23 � L3M12ð ÞVs½ �D

ð12Þ

96

i3 t � t3ð Þ ¼ i3 t2ð Þ

þt � t3ð Þ L1 L2 �M2

12

� �vCF þ L2 M13 �M12M23ð ÞVs

� D

ð13Þwhere D ¼ L1 L2 L3 � L3 M2

12 � L2 M213 þ 2M12M13M23�

L1 M223. Initial conditions for this mode are i1 ¼ i1ðt2Þ,

i2 ¼ i2ðt2Þ, i3ðt2Þ ¼ 0 and vCR ¼ 0. It should be noted thatthe initial conditions for currents ði1; i2 and i3Þ are theirrespective values at the end of mode 1 (the effect of mode 2is neglected), and that of vCR is zero.

The duration of this mode is given as

TZero ¼ t4 � t3ð Þ ¼ i2 t2ð Þ þ Io � i1 t2ð Þ � i3 t2ð Þð Þ � DvCF � C þ Vs � E ð14Þ

where C ¼ L2 M13 �M12M23 þM13M12 � L1 M23 þ L1 L2�M2

12, and E ¼ L2 L3 �M223 þ L3M12 �M13M23 þ L2M13�

M12M23.The expression for the area enclosed by current iCF ð¼ i3Þ

during this mode is given as

iCF ;area;M3¼

ðt4 � t23Þ L1L2vCF �M212vCF þ L2M13Vs

��M12M23VsÞ

2Dð15Þ

3.5 Mode 4 t4 � t � t5ð Þ: capacitor CRcharges: stage 1 (S2 on then off; D2 off thenon; D3 on; D1 off)During this mode of operation, CR charges owing to theresonance caused between mutually coupled inductors L1,L2, L3 and CR. Capacitor CF continues to discharge. Thestate equations for this mode are the same as that ofmode 2, except for the initial conditions. If circuitparameters and initial conditions are used, the analyticalsolution of the mathematical equations governing this modebecomes difficult to solve manually. However, if thenumerical values of a few circuit parameters are known apriori, these equations can be solved with ease. Softwarepackages such as Mathematica can be used as an aid tosolve the equations. As an example, if numerical value ofcircuit parameters such as Vs¼ 600, Io ¼ 50, L1 ¼ 281 mH,L2 ¼ 29 mH, L3 ¼ 43:8 mH, k12 ¼ 0:9, k13 ¼ 0:6, k23 ¼ 0:5,CR ¼ 22 nF are used, with symbolic notations for vCF ,i1ðt4Þ, i2ðt4Þ, i3ðt4Þ, the state equations and the expressionfor area enclosed by iCF are given in Appendix 9.

Note that, when the above equations are solved, thecapacitor voltage vCF and initial conditions for currents atthe start of this mode ði1ðt4Þ; i2ðt4Þ; i3ðt4ÞÞ are kept assymbolic notations. This helps to solve the circuit from theprevious mode to the next mode of operation, and to provethe concept of steady-state DC-voltage build-up across CF,on which the entire circuit operation is based (discussed inthe following Section). If (29) is plotted with respect to time,there will be two zero-crossings or solutions (see Fig. 4).This implies that i2 reverses its direction, making the anti-parallel diode of switch S2 ðD2Þ conduct for a short interval.When D2 is conducting, S2 is turned off under zero-voltageand zero-current switching conditions. This mode ofoperation ends when D2 turns off.

3.6 Mode 5 t5 � t � t6ð Þ: capacitor CRcharges: stage 2 (S2, D1 and D2 off; D3 on)During this mode of operation, a resonant circuit consistingof L1, L3 and CR is formed. Voltage across CR continues toincrease. This mode ends when the sinusoidally decreasingdischarge current iCF decreases to zero. At this instant,


D3 turns off. The equations governing this mode are given as

L1di1dt�M13

di3dtþ 1

CR

Z t

0

i1ðtÞ þ i3ðtÞ � Ioð Þdt ¼ Vs ð16Þ

L3di3dt�M13

di1dtþ 1

CR

Z t

0

i1ðtÞ þ i3ðtÞ � Ioð Þdt ¼ vCF ð17Þ

The state equations during this mode are derived based onthe same arguments made in the previous mode of operation.The initial conditions during this mode are: vCR ¼ vCRðt5Þ,i1 ¼ i1ðt5Þ, i2 ¼ i2ðt5Þ and i3 ¼ i3ðt5Þ. The state equationsand the expression for area enclosed by iCF during this modeare given in Appendix 9.

3.7 Mode 6 t6 � t � t7ð Þ: capacitor CRcharges: stage 3 (S2, D1, D2 and D3 off)During this mode of operation, a resonance circuitconsisting of L1 and CR is formed. Voltage across CRcontinues to increase. Current flowing through L1 decreasessinusoidally. This mode ends when the voltage across CRreaches the clamp voltage level KVsð¼ Vsþ vCF Þ. The linkcurrent and voltage equations are

iL1t � t6ð Þ ¼ Io þ i1 t6ð Þ � Ioð Þ cos o1 t � t6ð Þð Þ

þ Vs� vCR t6ð ÞR01

sin o1 t � t6ð Þð Þ ð18Þ

vCR t � t6ð Þ ¼ i1 t6ð Þ � Ioð ÞR01 sin o1 t � t6ð Þð Þ� Vs� vCR t6ð Þð Þ cos o1 t � t6ð Þð Þ þ Vs ð19Þ

The duration of this mode is given as

t7 � t6ð Þ ¼ 1

o1tan�1

2abþffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2abð Þ2�4 b2 � c2ð Þ a2 � c2ð Þ

q2 b2 � c2ð Þ

0@

1Að20Þ

where a ¼ ðVs� vCRðt6ÞÞ, b ¼ ði1ðt6Þ � IoÞR01 and c ¼ vCF .


3.8 Mode 7 t7 � t � t8ð Þ: clamping action(S2, D2 and D3 off; D1 on)During this mode of operation, the DC-link voltage vCR isclamped at Vsþ vCF ð¼ KVsÞ. Current flowing throughL1ð¼ i1Þ is fed to CF by diode D1. This current decreaseslinearly. This mode of operation ends when i1 becomesequal to inverter load current Io. After this mode ofoperation, the DC link returns to mode 0 of operation. Thelink current and voltage equations are

iL1t � t7ð Þ ¼ Vs� Vcð Þ

L1t � t7ð Þ þ iL1

t7ð Þ ð21Þ

vCR t � t7ð Þ ¼ Vsþ vCF ð22ÞThe duration of this mode is given as

t8 � t7ð Þ ¼ Io � i1 t7ð Þð ÞL1

Vs� Vsþ vCFð Þð Þ ð23Þ

The expression for the area enclosed by current iCF duringthis mode is given as

iCF ;area;M7¼ 0:5 t8 � t7ð Þ i1 t7ð Þ � Ioð Þ ð24Þ

4 Link design and control scheme

The design of QRDCL topology with three coupledinductors shown in Fig. 2 involves the selection ofparameters L1, L2, L3, CR, M12, M23 and M13 to the satisfythe desired link waveform specifications such as dv=dt,di=dt, value of K, peak currents in L1, L2, L3 and TZero. Thedesign process for the proposed QRDCL circuit topology isiterative in nature, wherein a simulation study or calcula-tions based on (1)–(24) are required to adjust the linkparameters and to verify that the design specifications aremet. The following design guidelines are recommended forthe design of the topology.

Initially, suitable values for L1 and CR are chosen.Inductance L1 consists of the sum of DC-source inductanceand externally connected inductance between the DCsource and the DC link. It prevents a significant rise in

Fig. 6 Plot of vCF against iCF ;area;average, TZero and zero-voltage turn-off time available for S2

97

source current above load current value Io when theDC-link voltage reduces below Vs. Hence, L1 in the rangeof 100–500mH is selected. Capacitance CR consists of straycapacitance across the PWM inverter DC-busbar terminalsand externally connected resonant capacitor. Generally, CRin the range of 10–100mH is selected.

Inductances L2 and L3 and coupling coefficients k12, k23and k13 are chosen in the following range: L2 ¼ 0:1 L1,L3 ¼ 1:5 L2, k12¼maximum possible (usually k12 in therange of 0.85–0.95 can be obtained), k13 ¼ 0:6k12 andk23¼minimum possible (usually k23 in the range of 0.4–0.5can be obtained). Practical considerations limit the mini-mum value of k23 that can be obtained. Once all circuitparameter values are chosen based on the above-mentionedguidelines, the circuit equations for various modes ofoperation are executed to check whether essentially requiredspecifications are met (such as the steady-state DC-voltagebuild-up across CF, which decides the clamping factor K ofthe inverter DC-link voltage). Capacitor CF is chosen suchthat constant voltage with negligible ripple is maintainedacross it. As the average value of the charging anddischarging current flowing through CF is negligibly small(of the order of 0.25–0.5A), an empirical value in the range

a b

c d

Fig. 7 Simulation resultsa M12 is increased from 81.5mH to 85.5mH in steps of 2mHb M13 is increased from 66.56mH to 74.56mH in steps of 4mHc M23 is increased from 17.81mH to 21.81mH in steps of 2mHd CR is increased from 22nF to 28nF in steps of 3nF

98

of 500–5000 times the value of CR is sufficient to givesatisfactory performance. Thus, under steady-state condi-tions, when steady DC voltage builds up across CF, thefollowing condition must be satisfied:

iCF ;area;average ¼ iCF ;area;M7� ðiCF ;area;M3

þ iCF ;area;M4þ iCF ;area;M5

Þ ¼ 0 ð25Þ

where, iCF ;area;M7is the area enclosed by iCF during mode 7.

When the average area enclosed by the current throughCF ð¼ iCF ;area;averageÞ is calculated, a suitable value for vCF �0:1Vs is assumed, and (15), (32), (36), (24) and (25) areevaluated. This process is repeated by either the increasing(if iCF ;area;average40) or decreasing (if iCF ;area:averageo0) of thevalue of vCF until the value of iCF ;area;average becomes zero.The value of vCF at which iCF ;area:average becomes zero is thevalue of the steady-state voltage across CF . The proposedcircuit with the parameters given in mode 4 is solved usingMATLAB, and the plot of vCF against iCF ;area;average isshown in Fig. 6. It can be observed that the steady-statevoltage attained across CF is 121V. Figure 6 also showsthe plot of the zero DC-link voltage period and zero-voltageturn-off period available for S2.


For the same circuit, the effect of change in variouscircuit parameters (M12, M13, M23, CR, L1, L2 and L3) wasstudied using a SABER simulator. The simulated wave-forms for each individual parameter change are shown inFigs. 7 and 8, respectively. In this study, each circuitparameter was given an incremental change (while otherparameters were kept constant), and the results wereplotted. These results are enumerated in Table 1 and canhelp in fine-tuning the circuit parameters until the requiredspecifications are met. For example, if the zero-voltage turn-off switching property for S2 is not satisfied during mode 4of operation, then M12 should be given an incrementalchange until this property is satisfied.

It is found that average current stress on additionalswitching devices such as S2, D1 and D3 are negligibly small.From the simulation study on the proposed circuit with theparameters given in mode 4, the average values of currentflowing through S2, D1 and D3 are found to be 0.46A, 0.3Aand 0.26A, respectively, and their peak values of currentsflowing are found to be 24 A, 2.5 A and 8 A, respectively(see Fig. 4). Thus S2, D1 and D3 are selected based on their

a b

c d

Fig. 8 Simulation resultsa L1 is increased from 281mH to 321mH in steps of 20mHb L2 is increased from 29mH to 49mH in steps of 10mHc L3 is increased from 43.8mH to 73.8mH in steps of 15mHd During regeneration by taking Io¼ � 50A


Table 1: Effect of parameter variation on circuit perfor-mance

Circuitparameter

Zero-voltagetime periodTzero

Clamp voltagelevel ¼ ðVs þ vCF

ÞAvailablezero-voltageturn-offperiod for S2

k12 m decreases negligiblechange

increases

k13 m negligiblechange

decreases increases

k23 m negligiblechange

increases negligiblechange

CR m increases decreases decreases

L1 m increases decreases decreases

L2 m decreases marginalincrease

marginalincrease

L3 m negligiblechange

increases negligiblechange

99

peak current rating and the maximum voltage they need toblock. The maximum voltage that S2 needs to block isduring mode 7 of operation and is given as

Vmax;blocking;S2 ¼ Vsþ vCF �M12 �di1dt

� �mode 7

ð26Þ

The value of M12 � ðdi1=dtÞ during mode 7 of operation isnegative and is of the order of 30–40V for the circuitparameters given in mode 4. It can be easily verified from

Fig. 4 that the value of ðdi1=dtÞmode 7 � �357143A s�1,which gives the product M12 � ðdi1=dtÞmode 7 ¼ �29V ( forM12 ¼ 81:24 mH). Thus the maximum voltage stress on S2

is marginally higher than DC-link clamp voltage levelVCð¼ Vsþ vCF Þ. This increased voltage stress on S2 beyond

CommandGenerator(Phase A)

PWM

CommandGenerator(Phase B)

PWM

CommandGenerator(Phase C)

PWM

Link

Detector

EdgeDetector

MonoShot

DFlipFlop

DFlipFlop

DFlipFlop

Q

Q

Q

To Phase ASwitches

To Phase BSwitches

To Phase CSwitches

Switch S2To Auxiliary

V

D

D

D

CLK

CLK

CLK

Q

Q

Q

Sa

Sb

Sc

Sd

Se

Sf

Fig. 9 Control circuit for synchronising inverter switching withzero DC-link voltage instants

100

the DC-link clamp voltage level can be considered negligiblysmall.

The maximum reverse voltage appearing across diode D3

also occurs during mode 7 of operation and is given as

Vmax;reverse;D3¼ Vs�M13 �

di1dt

� �mode 7

ð27Þ

Thus the maximum reverse voltage across D3 alwaysremains marginally less than the DC-link clamp voltagelevel. It can be observed from Fig. 4 that the maximumreverse voltage across diode D1 occurs during mode 3 and isequal to the DC-link clamp voltage VCð¼ Vsþ vCF Þ.

The block diagram of the control circuit for soft-switchedPWM inverter control is shown in Fig. 9. Depending uponthe PWM inverter modulation strategy, the PWM com-mand generator generates the switching signals for theinverter devices. The change in the conducting state of anyinverter switch is first detected by the edge detector, whichgenerates a turn-on signal to the auxiliary switch S2. Thisinitiates the resonant cycle. The pulse width of the signalapplied to the gate of S2 is equal to sum of the time requiredfor the DC-link voltage to reach zero and TZero. Tosynchronise the change in the conducting state of theinverter devices with the zero link voltage instant, three

Fig. 10 Simulated plots of vCF and iCF during starting

Table 2: List of SABER templates used for simulating various circuit components and power dissipated in them for differentvalues of inverter switching frequencies

Circuit component SABERtemplate

Template properties/comments

Power dissipatedwith SPWM, 5kHz



L1 (281mH, air core) l r¼220mO 9.1W 9.81W 10.9W

L2 (29mH, air core) l r¼80mO 0.52W 1.86W 1.91W

L3 (43.8mH, air core) l r¼120mO 0.18W 0.45W 0.55W

Switch S2 irg4ph50u Inbuilt Saber TemplateAnalogy Inc.

4.5W 9W 10.5W

Diode D1 mur10150e Inbuilt Saber TemplateAnalogy Inc.

0.21W 0.33W 0.6W

Diode D3 mur10150e Inbuilt Saber TemplateAnalogy Inc.

0.84W 2.59W 4W

Inverter switches irg4ph40u Inbuilt Saber TemplateAnalogy Inc.

48W 52W 60W

Free-wheelingdiodes acrossinverter switches

dp Inbuilt Saber TemplateAnalogy inc.

5.2W 5.7W 6.2W

Total 68.55W 81.74W 94.66W

Load and source parameters are: RL¼19.68O, LL¼ 63.94O, Vs¼600V, Power factor¼ 0.7, Output power¼3.6kW


D-type flip-flops are used. The switching signals generatedby the three-phase PWM command generator drive theD-input pins of the flip-flops, and the output pins ðQ and �QÞdrive the corresponding top and bottom switches of the

Fig. 11 Experimental resultsa DC-link voltage vCR (top trace, 200Vper division), S2 gate driverinput signal (middle trace, 10V per division) and current through L2

(bottom trace 16A per division)Time: 5ms per divisionb DC-link voltage (top trace 300V per division), current through L2

(middle trace, 10A per division), and current through L1 (bottomtrace, 10A per division)Time: 5ms per division

Table 3: Inverter efficiency for three different switchingfrequencies

SPWM carrierfrequency, kHz

Average switchingfrequency of S2, kHz

% efficiency

5 30 98.09

6 36 97.72

7 42 97.37


PWM inverter. When the link voltage reaches zero, thezero-voltage detector outputs a signal that is used to clockthe D-type flip-flops. Thus it synchronises the change in theconducting state of the inverter devices with the zero linkvoltage instants, so that the conducting state is changedonly at zero-voltage condition.

5 Simulation results

A simulation study of the proposed circuit with parametersgiven in the mode 4 was performed to verify the analysisand to predict the performance under various loadconditions. Simulation results for Io ¼ 50A are shown inFig. 4. It is observed that the fall time of the link voltage isabout 533ns. The zero link voltage condition, which isutilised for soft-switching of the inverter poles, is maintained

Fig. 12 Experimental resultsa Current through L2 (top trace, 10A per division), current through L1

(middle trace, 10A per division) and current through CF (bottomtrace, 10A per division)Time: 5ms per divisionb DC-link voltage (top trace, 300V per division), current through L1

(middle trace, 5A per division) and current through CF (bottom trace,5A per division)Time: 20ms per division

101

for about 686ns. The rise time for the DC-link voltage toreach clamp voltage level after a brief zero-voltage period is3.6ms.

The proposed circuit behaves identically when loadregenerates (Io in Fig. 3 reversed in direction). A simulationstudy was carried out during regeneration with Io ¼ �50A(see Fig. 8d). Figure 10 shows the waveforms of the currentthrough CF and its voltage during starting. It can beobserved that vCF settles at 100V, giving a clamp factor ofK¼ 1.16. The on-time of S2 is 1.5ms.

So that the theoretical efficiency of the inverter atdifference switching frequencies can be estimated, theproposed circuit was simulated using actual SABERtemplates for various components. The inverter wasassumed to be feeding an RL load at power factor of 0.7,

Fig. 13 Experimental resultsa DC-link voltage vCR (top trace, 250V per division), inverter line-to-line voltage (middle trace, 250V per division) and current through L1 ði1Þ(bottom trace, 8A per division)Time: 20ms per divisionb Waveforms at fundamental frequency of 50Hz: DC-link voltage vCR (top trace, 500V per division), inverter line-line voltage (middle trace, 500Vper division), and motor phase current (bottom trace, 16A per division)c Waveforms at fundamental frequency of 60Hz: inverter line–line voltage (top trace, 300V per division) and motor phase current (bottom trace,10A per division)Time: 5ms per division

102

Table 4: List of motor parameters

Motor parameter Value

Rated voltage 400V

Rated line-current 7.8A

Stator connection type Star connected 3F 4 pole

Frequency 50Hz

Rs 1.1O

Rr 0.9O

Xsl 1.8O

xrl 1.8O

XM 68O


fundamental frequency of 50Hz and modulation index of 1.The per-phase load parameters, DC-source value andSABER templates used for the simulation study are givenin Table 2. As L1, L2 and L3 were chosen to be air coreinductors, a linear inductor template with finite resistancewas used for simulation. If actual SABER templates areused, the average power dissipated in each circuitcomponent can be determined from the simulation results.These results are given in Table 2.

Once the total power dissipation in the entire circuit hasbeen found, the efficiency can be calculated. The efficiencyof the inverter for three different switching frequencies isgiven in Table 3. It should be noted that the calculatedefficiencies of the proposed soft-switched inverter, as listedin Table 3, are based on simulation results.

6 Experimental results

So that the simulated results could be validated, alaboratory prototype was built and tested under variousload conditions. The circuit parameters used for theexperimental study are given in the mode 4 description ofcircuit operation. Other circuit parameters are: Vs¼ 300V,CF ¼ 5 mF, and the on-time of S2¼ 2.5ms. Figures 11a–12bshow the recorded waveforms under no-load condition.Figure 11a shows vCR , the gate signal of S2, and the currentthrough L2, and Fig. 11b shows vCR and currents throughL2 and L1. The clamp factor K achieved was 1.3. Figure 12ashows the currents through L1, L2 and L3, respectively, andFig. 12b shows vCR , L1 current and current through CF. Itcan be observed from Fig. 11a, that the fall time ofthe link voltage is approximately 800ns. The zero linkvoltage condition, which is utilised for soft-switching ofinverter poles, is maintained approximately for 700ns.The DC-link voltage rises is three distinct steps to reachclamp voltage level after a brief zero-voltage period. Thetime taken for the DC-link voltage to reach clamp voltagelevel after a brief zero-voltage period is approximately5.5ms.

It can be observed that there is fairly good match ofsimulated waveforms (Fig. 4) and those obtained from theprototype. In the experimental set-up there are strayinductances and capacitances that cause deviation fromthe simulation results. To demonstrate the PWM capability,a three-phase sine-triangle PWM command generator wasimplemented to control the six inverter switches. The outputof the soft-switched inverter is directly connected to three-phase induction motor whose parameters are given inTable 4. The sine-triangle PWM (SPWM) technique is usedcontrol the output voltage of the inverter. The frequency ofthe carrier wave is maintained at 6kHz. The measuredwaveforms are shown in Figs. 13a–c. Figure 13a shows thelink voltage vCR , inverter line–line voltage and currentthrough L1. Figure 13a clearly shows that the change inline–line voltage is synchronised with the zero-voltageinstants of the DC link. The load current is sinusoidal,and the performance of the link is found to be satisfactory.

7 Conclusions

In this paper, a new circuit topology for a QRDCL soft-switching PWM inverter is proposed. It is a simple soft-switching topology that is easy to implement and control.The proposed circuit uses one additional switch to createzero-voltage instants in the DC link. The maximum voltagestress on auxiliary circuit diodes is confined to the DC-linkclamp voltage level. Also, the resonant energy associated


with clamping is recycled. The proposed inverter config-uration is a solution to the problem of maintaining aseparate low-voltage DC source using a low-power DC-to-DC converter for clamping the DC link. It is shown that theextra resonant energy can be recycled, while the voltagestress on the clamping diode is maintained equal to the DC-link clamp voltage level. The introduction of magneticcoupling between three resonant inductors can minimise thedevice count. Various modes of operation and link wave-forms were analysed to reveal the soft-switching character-istics. Simulation and experimental studies were carried outto verify the proposed concept.

8 References

1 Divan, D.M.: ‘The resonant dc link inverter – a new concept in staticpower conversion’. IEEE-IAS Annual Conf. Rec., 1986, pp. 648–656

2 Divan, D.M., and Skibinski, G.: ‘Zero switching loss inverters for highpower applications’. IEEE-IAS Annual Conf. Rec., 1987, pp. 627–634

3 Merterns, A., and Divan, D.M.: ‘A high frequency resonant dc linkinverter using IGBTs’. IPEC Tokyo, Japan, 1990, pp. 152–160

4 He, J., andMohan, N.: ‘Parallel resonant dc link circuit – a novel zeroswitching loss topology with minimum voltage stresses’, IEEE Trans.Power Electron., 1991, 6, pp. 687–694

5 He, J., Mohan, N., and Wold, B.: ‘Zero voltage switching PWMinverter for high frequency DC-AC power conversion’, IEEE Trans.Ind. Appl.., 1993, 29, pp. 959–968

6 Jung, and Cho, G.: ‘Novel type soft switching PWM converter using anew parallel resonant DC link’. IEEE-IAS Conf., 1991, pp. 241–247

7 Malesani, L., Tenti, P., Tomasin, P., and Toigo, V.: ‘High efficiencyquasiresonant dc link three-phase power inverter for full-range PWM’,IEEE Trans. Ind. Appl., 1995, 31, pp. 141–148

8 Choi, J.W., and Sul, S.K.: ‘Resonant link bidirectional powerconversion – Part-I: Resonant circuit’, IEEE Trans. Power Electron.,1995, 10, pp. 479–484

9 Wang, K., Jiang, Y., Dudovsky, S., Hau, G., Boroyevich, D., and Lee,F.C.: ‘Novel dc-rail soft switching three-phase voltage source inverter’,IEEE Trans Ind. Appl., 1997, 23, pp. 509–516

10 Divan, D.M., Malesani, L., Tenti, P., and Toigo, V.: ‘Asynchronisedresonant dc link converter for soft switched PWM’, IEEE Trans. Ind.Appl., 1993, 29, pp. 940–948

11 Lai, J.S., and Bose, B.K.: ‘High frequency quasi-resonant DC voltagenotching inverter for AC motor drives’. Proc. IEEE Conf., 1990,pp. 1202–1207

12 Vassilios, G., and Ziogas, P.D.: ‘An optimum modulation strategy fora novel notch commutated three phase PWM inverter’, IEEE Trans.Ind. Appl., 1994, 30, pp. 52–61

13 Hui, S.Y.R., Gogani, S., and Zhang, J.: ‘Analysis of a quasi-resonantcircuit for soft-switched inverters’, IEEE Trans. Power Electron., 1996,11, pp. 106–114

14 Chen, S., and Lipo, T.A.: ‘A novel soft switched PWM inverter forACmotor drives’, IEEE Trans. Power Electron., 1996, 11, pp. 653–659

15 Jafar, J.J., and Fernandes, B.G.: ‘A new quasi-resonant DC-linkPWM inverter using single switch for soft switching’, IEEE Trans.Power Electron., 2002, 17, p. 1010

16 Jafar, J.J., and Fernandes, B.G.: ‘A quasi-resonant DC-link PWMinverter for induction motor drive’. In IEEE-IAS Annual Conf. Rec.,1999, pp. 1997–2002

17 Jafar, J.J., and Fernandes, B.G.: ‘A novel quasi-resonant DC-linkPWM inverter for induction motor drive’. In IEEE-PESC Conf. Rec.,1999, pp. 482–487

9 Appendix

9.1 State equations during mode 4 of circuitoperations

i1ðt � t4Þ ¼ 23:2556þ 0:534888i1ðt4Þ þ 0:465112i2ðt4Þþ 1:08022i3ðt4Þ þ 0:0078125ðt � t4Þ2

þ cos½373683ðt � t4Þ�ð�11:363þ 0:22726i1ðt4Þ� 0:22726i2ðt4Þ � 1:21087i3ðt4ÞÞ þ cos½3:72354� 106ðt � t4Þ�ð�11:8926þ0:237852i1ðt4Þ� 0:237852i2ðt4Þ þ 0:130654ðt4ÞÞ þ sin½373683ðt � t4Þ�� ð3:54682 � 0:106768 vCF Þ þ sin½3:72354� 106ðt � t4Þ�� ð2:63439 þ 0:00224885 vCF Þ þ 41561:1ðt � t4Þ vCF ð28Þ

103

i2ðt � t4Þ ¼ �26:7444þ 0:534888i1ðt4Þ þ 0:465112i2ðt4Þþ 1:08022i3ðt4Þ þ cos½373683ðt � t4Þ�ð�6:68997þ 0:133799i1ðt4Þ � 0:133799i2ðt4Þ � 0:712902i3ðt4ÞÞþ cos½3:72354� 106ðt � t4Þ�ð33:4344� 0:668688i1ðt4Þþ 0:668688i2ðt4Þ � 0:367315i3ðt4ÞÞ þ sin½373683ðt � t4Þ�� ð2:08819�0:0628597 vCF Þ þ sin½3:72354� 106ðt � t4Þ�� ð�7:40622�0:00632232 vCF Þ þ 41561:1ðt � t4Þ vCF

ð29Þ

i3ðt � t4Þ ¼ cos½373683ðt � t4Þ�ð8:50709� 0:170142i1ðt4Þþ 0:170142i2ðt4Þ þ 0:90654i3ðt4ÞÞ þ cos½3:72354� 106ðt � t4Þ�ð�8:50709þ 0:170142i1ðt4Þ � 0:170142i2ðt4Þþ 0:0934603i3ðt4ÞÞ þ sin½373683ðt � t4Þ�ð�2:65539þ 0:0799336 vCF Þ þ sin½3:72354� 106ðt � t4Þ�� ð1:88445þ 0:00160866 vCF Þ ð30Þ

vCRðt � t4Þ ¼ �45:4545� 106ð6:96892� 10�9

� ð459:557� 13:8338 vCF Þ � 2:09814� 10�9

� ð1526:41þ 1:30302 vCF ÞÞ þ 45:4545� 106

� ð�2:09814� 10�9ð6890:76� 137:815ði1ðt4Þ� i2ðt4ÞÞ � 75:703i3ðt4ÞÞ sin½3:72354� 106ðt � t4Þ�� 2:09814� 10�9 cos½3:72354� 106ðt � t4Þ�� ð1526:41þ 1:30302 vCF Þ þ 6:96892� 10�9

� ð2:54897� 10�7i1ðt4Þðt � t4Þ þ 4:77932

� 10�8i2 � ðt4Þðt � t4Þ þ 373683ðt � t4Þ3

þ 459:557 cos½373683ðt � t4Þ� þ 1472:29

� sin½373683ðt � t4Þ� � 29:4457i1ðt4Þ sin½373683ðt � t4Þ�þ 29:4457i2ðt4Þ sin½373683ðt � t4Þ� þ 156:891i3ðt4Þ�sin½373683ðt�t4Þ��13:8338 cos½373683ðt�t4Þ�vCF ÞÞ ð31ÞThe expression for the area enclosed by current iCF ð¼ i3Þduring mode 4 is given as

iCF ;area;M4 ¼ �4:56936� 10�8ð50� i1ðt4Þ þ i2ðt4Þ� 0:549308i3ðt4ÞÞ sin½3:72354� 106ðt � t4Þ�� 4:55311� 10�7ð15:6069� 0:469806 vCF Þþ 4:56936� 10�8ð11:0758þ 0:00945482 vCF Þ� ð1� cos½3:72354� 106ðt � t4ÞÞ� þ 4:55311� 10�7

� ðcos½373683ðt � t4Þ�ð15:6069� 0:469806 vCF Þþ sin½373683ðt � t4Þ�ð50� i1ðt4Þ þ i2ðt4Þþ 5:32814i3ðt4ÞÞÞ ð32Þ

104

9.2 State equations during mode 5 of circuitoperations

i1ðt � t5Þ ¼ 12:0485þ 0:759029i1ðt5Þ � 0:240971i3ðt5Þþ 1:31032� 106ðt � t5Þ � 0:045118 vCRðt � t5Þ� 0:000976563ðt � t5Þ2 � 2183:84ðt � t5Þ vCF

þ cos½1:62534� 106ðt � t5Þ�ð0:240971i1ðt5Þþ 0:240971i3ðt5Þ � 12:0485Þ þ sin½1:62534� 106ðt � t5Þ�ð1:24596� 0:00861631 vCRðt5Þþ 0:0065397 vCF Þ ð33Þ

i3ðt � t5Þ ¼ 37:9515� 0:759029i1ðt5Þ þ 0:240971i3ðt5Þ� 1:31032� 106ðt � t5Þ þ 0:045118 vCRðt � t5Þþ 0:000976563ðt � t5Þ2 þ 2183:84ðt � t5Þ vCF

þ cos½1:62354� 106ðt � t5Þ�ð0:759029i1ðt5Þþ 0:759029i3ðt5Þ � 37:9515Þ þ sin½1:62534�106ðt � t5Þ� � ð3:92462� 0:0271404 vCRðt5Þþ 0:0205993 vCF Þ ð34Þ

vCRðt � t5Þ ¼ vCRðt5Þ þ 0:0136554ð10589:3� 73:2297 vCRðt5Þ þ 55:5806 vCF Þ þ 45:4545

� 106ð�0:00016276ðt � t5Þð4:36557� 10�11

þ ðt � t5Þ2Þ � 3:00418� 10�10ð102400� 2048i1ðt5Þ� 2048i3ðt5ÞÞ sin½1:62543� 106ðt � t5Þ�� 3:00418� 10�10 cos½1:62534� 106ðt � t5Þ�� ð10589:3� 73:2297 vCRðt5Þ þ 55:5806 vCF ÞÞ ð35Þ

The expression for the area enclosed by current iCF ð¼ i3Þduring mode 4 is given as

iCF ;area;M5 ¼ �3:00418� 10�10ð77724:6� 1554:49i1ðt5Þ� 1554:49i3ðt5ÞÞ sin½1:62534� 106�ðt � t5Þ� þ 3:00418

� 10�10ð8037:62� 55:5834 vCRðt5Þ þ 42:1837 vCF Þ� ð1� cos½1:62534� 106ðt � t5Þ�Þþ 0:0000813802ðt � t5Þð466347� 9326:95i1ðt5Þþ 2961:05i3ðt5Þ � 8:05061� 109ðt � t5Þþ 277:205 vCR � ðt � t5Þ þ 2ðt � t5Þ2 þ 1:34175

� 107ðt � t5Þ vCF Þ ð36Þ


Three-phase soft-switched pwm inverter for motor drive application

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