The Xilinx Spartan 3 FPGA

EGRE 631

2/2/09

Basic types of FPGA’s• One time programmable• Reprogrammable (non-volatile)

– Retains program when powered down

• SRAM-based reprogramable– Must be reprogrammed each time powered up– This is usually accomplished by using a small

serial PROM.– The Nexys 2 board contains a Xilinx Spartan 3E

FPGA

Spartan-3E ArchitectureFundamental Elements

• Configurable Logic Blocks (CLBs)– Consists of RAM based look up table to implement logic

and storage elements that can be used as flip-flops or latches.

• Input Output Blocks (IOBs)– Controls the flow of data between IO pins and internal

logic. Supports many different signal standards. (Tri-state, bidirectional, LVTTL, etc.

• Block RAM (BRAM)• 18 bit Multiplier Blocks• Digital Clock Manager (DCM)

CLB’s

Spartan 3 Configurable Logic Blocks (CLB’s)

• CLBs contain Ram based lookup tables to implement logic and storage elements that can be used as flip-flops or latches.

• CLBs can be programmed to perform a wide variety of logic functions as well as store data.

Clock signal fromoutside world

Clocktree

Flip-flops

Special clockpin and pad

Spartan 3E IO Blocks (IOB’s)

• IOB’s control flow of data between IO pins and the internal logic.

• Each IOB supports bidirectional data flow, 3-state operation, and numerous different signal standards. (We will typically use LVTTL). See data sheet.

• Very low cost, high-performance logic solution forhigh-volume, consumer-oriented applications• Multi-voltage, multi-standard SelectIO™ interface pins- Up to 376 I/O pins or 156 differential signal pairs- LVCMOS, LVTTL, HSTL, and SSTL single-endedsignal standards- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

I/O block

I/O block continued

CLB’s – four slices per CLB

Top slice of CLB