The "Ultimate" CMOS Device:A 2003 Perspective

(Implications For Front-End Characterization And Metrology)Howard R. Huff and Peter M. Zeitzoff

International SEMATECH2706 Montopolis Drive

Austin, TX 78741

Abstract. The evolution of planar, conventional CMOS to non-classical CMOS devices as described inthe International Technology Roadmap for Semiconductors (ITRS) is discussed. The benefits of strainedsilicon configurations to enhance the channel mobility, silicon-on-insulator (SOI) to enhance thereduction of residual parasitics and non-planar transistor device structures to improve control of the short-channel effects are discussed. The combination of the above enhancements, in conjunction with thecurrent state-of-the art global efforts in high-k gate dielectrics, metal electrodes and elevatedsource/drain, offers a plethora of opportunities requiring careful assessment of the optimal solution foreach organization's portfolio of products and projected market position. Several of these possiblesolutions for the "ultimate" CMOS device are discussed from today's perspective, with attention to thecharacterization and metrology for assessing these alternate device structures.

INTRODUCTION

The pervasiveness of the microelectronicsrevolution can be traced to Patrick Haggerty andGordon Moore. Moore's remarkedly prescientassessment of memory component growth in1965, initially based on bipolar and then MOSmemory density, observed that a semilog graphof the number of memory bits in an integratedcircuit (1C) versus the date of initial availabilitywas a straight line, representing almost adoubling per year [1,2]. The technology wasbased on a cell design feature in which thenumber of transistors per memory cell wasreduced from 6 for a static random accessmemory (SRAM) to 1.5 for a dynamic randomaccess memory (DRAM), based on BobDennard's one transistor/one capacitor (IT/1C)DRAM cell in 1968 [3] and the reduction (i.e.,scaling) in the design rule. The scalingmethodology, introduced by Dennard et al. in1974 [4] (i.e., reduction in design rules withoutcompromising the current-voltagecharacteristics), established the paradigm bywhich enhanced scaling has progressed andfacilitated the explosive growth and applicationsof the metal-oxide semiconductor field-effecttransistor (MOSFET) 1C. The original scalingmethodology was based on constant electric fieldscaling principles and was generalized in 1984 to

allow the voltage to be scaled less rapidly thanthe dimensions by increasing the electric field(with its own scaling factor) [5]. Major scalingchanges were implemented in the reductions ofthe gate dielectric thickness, physical gate lengthand extension junction depth, as discussed byDennard and colleagues via initially constantelectric-field scaling and, subsequently, constantvoltage scaling [6].

The concurrent concept of a learning curve,(i.e., the concomitant reduction in the cost offabrication with the increased volume ofproduction) and the concept of market elasticitywas enunciated by Pat Haggerty in the 1960's[7-9]. The number of transistors per chip wassubsequently modified by Moore in 1975 todouble about every two years around the mid-later 1970s [10]. The technology continued to bebased on a reduction in the design rule while thedesign, per se, was no longer achieved by areduction in transistors per memory cell. Rather,the design benefits were now derived fromimprovements in circuit layout. These analyseswere enshrined as Moore's law and became theproductivity criterion by which the 1C industrygrew at a 16% compound annual growth rate(CAGR) during the 30 years from the 1960's-1980's.

The phenomenal growth of the 1C industry,achieved by staying on the "productivity learning

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curve," continues to be the gauge by which theindustry is measured [11]. Indeed, Moore's lawcontinues to be the metric by which 1Cperformance is measured in the InternationalTechnology Roadmap for Semiconductors(ITRS) [11]. More than just monitoringproductivity, whether by staying on theproductivity curve or increasing manufacturingeffectiveness, however, is required. Rather,modeling productivity—the identification of newproductivity measures—is now required [12].

Significant front-end-of-the-line scalingcontributions have occurred in reduction of thegate dielectric thickness, physical gate length andextension junction depth [13] (see Figure 1) [14].These scaling advances have resulted in lowerpower dissipation per function, increased speed(intrinsic transistor gate delay) and increasedtransistor and function density [15-17]. Thepotential solutions and approaches for scalinghave been addressed by both material andprocess advances. These include arenas such ashigh-k gate dielectrics [18-23] andcharacterization of the interfaces involving thehigh-k gate dielectric as well as the metal gateelectrodes. In particular, interactions of thehigh-k with either the silicon [24] or the poly-silicon gate electrode [25], including interactionsof the high-k material with both the siliconsubstrate and the polysilicon gate electrode [26]and charge instabilities associated with the highgate dielectric and/or its method of fabrication

[27] have also been considered. Finally, the roleof poly SiGe gate electrodes [28] and dual workfunction metal gate electrodes with differingwork functions [29] or a single, tunable workfunction metal for CMOS optimization [30,31]to reduce the poly depletion effect [32] andboron penetration in PMOSFETs [32] with metalgate electrodes as well as avoiding reactionsbetween the polysilicon and the high-k gatedielectric [24,25] are state-of-the art issues.

During the last few years, however,alternative non-classical device structuralconfigurations have received extensiveassessment to maintain Moore's law [10,33].MOS transistor scaling of the physical gatelength (Lg) to the sub-20 nm regime has beenobserved to exhibit short channel effects (SCE)[32,34,35]. In conjunction with alternativeCMOS device structures (i.e., vertical gateapproaches such as the FinFET [36,37] and othermultiple gate configurations [38]), theopportunity for mainstream utilization of SOIhas significantly broadened [39-45]. We shallfocus on these alternative device structures in thedrive to the "ultimate" CMOS deviceconfiguration [46,47], noting the importance ofcharacterization and metrology in thesealternative device structures.

poly

fits

Si

LJ

Figure 1. Simplified cross-section of a high-k gate dielectric stack with accompanying physicalgate length (Lg) and junction structures. Modified version of drawing in [14].

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TRANSISTOR SCALINGISSUES

The increased difficulty in meeting therequired device metrics over the next 15 yearscertainly appears daunting [11]. These deviceparameters include the maximum saturated draincurrent Idsat9 off-current, Ioff, intrinsic transistorgate delay (CV77), switching energy (CV2) andtheir dependence upon Lg, supply voltage (VDD)and oxide equivalent thickness (EOT). Althoughthe challenges are substantial, they appearsoluble with currently understood physicalprinciples [15-17,32]. Similarly, theexponentially increasing limits to scaling such asincreased subthreshold leakage, increased gatedielectric leakage, increased transistor parametervariability and interconnect density andperformance appear to be comprehended [32].Accordingly, silicon MOSFETs may beexpected to scale in an essentially predictablemanner from the present state-of-the-art 90 nmtechnology generation (MPU Lg of 45 nm) to the22 nm technology generation (MPU Lg of 9 nm)[34,35,37], with band-to-band tunnelingconsidered as the limitor at about an Lg of 5 nm.Recent advances towards the extreme scalinglimit for Lg have been described for anelectrically variable shallow junction MOSFET[48] and ultra-thin Si channel MOSFETs [49].

Nevertheless, substantial issues that must beassessed involve control of SCE, impact ofquantum effects in the bulk silicon (andpolysilicon, an especially intricate topic.Additional critical issues include dopantstochastic variations (number and spatial locationin channel) and other device/process fluctuationphenomena [50,51], usefulness for enhancedmobility (beyond the universal mobility curve),impact of high substrate doping, control of seriessource/drain resistance and related contactissues. We shall focus on two members of thenon-classical CMOS device family in addressingthe above issues. These are band-engineeredtransistors, resulting in improved transport andmobility of the relevant charge carriers, andmulti-gate SOI structures, including the verticalFinFET device.

Band Engineered Transistors

The maximum attainable Idsat f°r siliconMOSFET's has been identified to be limited bythe thermal injection of carriers from the source

into the channel [52] with Ge suggested as amore efficient injecting material than Si.

Once the carriers enter the channel, it isadvantageous to enhance their mobility beyondthe classical, universal limit [32,53]. Severaltechniques to enhance the electron carriermobility in the channel include the incorporationof an epitaxial strained silicon film (due to thebiaxial in-plane tensile strain arising as a resultof the lattice mismatch between the Si and theunderlying fixed composition, relaxed Si(i_x)Gexdeposited on a compositionally varied Si(i_y)Gey(where y < x) [54-62]) or slightly differentstrained configurations for p-channel devices[63] as well as strained Ge channels [64,65].Additional methods of introducing strain in thechannel include a tensile (localized) film abovethe channel [66,67]. The role of the source/drainsilicide, inducing a tensile strain in the channel,enhancing both the electron and hole mobility[68] and that of shallow trench isolation (STI)induced stresses [69] have also been noted.

The de-convolution of the mobility[70,71] is still riddled with numerous un-resolved issues. The detailed analysis fromcapacitance-voltage (CV) curves to determinethe effective surface mobility ortransconductance has re-emerged as a criticalissue and is a state-of-the-art issue [72,73]. It iswell accepted, however, that at low electric field,scattering is dominated by unscreened (noinversion layer free carriers) ionized dopantscattering centers in silicon. At high electricfield, furthermore, surface acoustic phonons andsurface microroughness are critical contributors.The latter contribution is generally representedby the product of H x L, where H is the height ofthe surface undulation and L is the undulationcorrelation length [74]. Recently, it has beenpostulated that remote scattering by high-k gatedielectric optical phonons, coupling with thesilicon channel, degrades the surface mobility[75]. Interestingly, the presence of an interfacialoxide modulates the optical phonon coupling tothe silicon channel, at the expense of increasingthe EOT of the dielectric stack.

Additional sources of mobility degradationhave been deduced by detailed experiments,although a theoretical basis for these sourcescontinues under development. These includeinterfacial and high-k gate dielectric bulk traps[27], crystalline inclusions in amorphous high-kgate dielectrics [76], N, Al and other elemental,interface scatterers as well as remote scatteringdue to the gate electrode [77]. Band engineeredMOSFETS such as the surface strained silicon

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Figure 2. Surface channel strained silicon band-engineered MOSFET structures for NMOS (left) [57] andPMOS (right) [58], courtesy of Judy Hoyt. Reproduced with the permission of the IEEE.

MOSFET structure have received significantattention (see Figure 2) [57,58] for increasing thecarrier mobility and Idsat- The electron mobilityenhancement (relative to the unstrained case) of1.6 to 1.8 has been reported for a Ge atomiccontent of about 20% (see Figure 3) [78,79],even up to effective surface electric fieldsbeyond 1 MV/cm [80]. Comparable n-channelIdsat enhancements have been reported for long-channel devices [81] whereas the enhancementdegrades to less than 50% in the case of short-channel devices [32]. The hole mobilityenhancement can apparently be as large as 2.5,requiring a Ge content of ~ 35 atomic % [78,82]as seen in Figure 3, which may not be sosurprising considering the increased holemobility of germanium as compared to silicon[83]. Figure 3 schematically illustrates theincreased lattice constant of the strained siliconon a relaxed or strained epitaxial Si(i_x)Gex, thelatter materials straining the subsequentlydeposited silicon (channel layer) in a biaxially

tensile manner [78]. This has the effect ofsplitting the silicon conduction band's six-folddegenerate electron A orbitals, lowering theenergy of the out-of-plane A2 orbitals, relative tothe A4 in plane orbitals by about 200 meV [60](as well as lowering their effective mass) and,thereby, increasing their occupancy. The tensilestrain, therefore, effectively increases theelectron mobility. More importantly, however,the inter-valley scattering is significantlyreduced, also enhancing the electron mobility.Assessment of the residual strain in such filmsafter 1C fabrication is most important.

The hole mobility is more complicated dueto the degeneracy of the light- and heavy-holebands at k=0 as well as the split-of band at k=0.Here also, the tensile strain splits the siliconvalence-band degeneracy, lowering the light-holeenergy band relative to the heavy-hole band byabout 77 meV as well as lowering the effectivemass of both the light-hole and heavy-holebands [56].

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Simodified band structure of Si under biaxialtensile strain ==> enhanced mobility

Strained Si on SiGe

need relaxed Sh_xGex with 0.15<x<0.35

Figure 3. Electron [79] and hole enhancement [82] factors (left) and schematic illustration of tensile inducedstrained silicon layer, courtesy of Patricia Mooney [84] (IBM Corporation).

More importantly, however, here also there isreduced intervalley scattering, therebyeffectively increasing the hole mobility. For thehole situation, these observations are observedfor both biaxially tension and compressivestresses [80].

By engineering the controlled growth rate ofthe compositionally varied epitaxial Si(i_y)Geyand, thereby, minimizing dislocation nucleationsuch that the threading dislocations are

5 2< 5 x 10 /cm , each sub-component layer of thestack is relaxed to an intermediate latticeconstant, reducing the misfit dislocation array ateach interface. Nevertheless, the underlyingmisfit dislocation array can affect the localepitaxial growth rate of the subsequentlydeposited strained silicon layer. Accordingly,chemical-mechanical planarization (CMP) isperformed to reduce any residual crosshatchsurface microroughness [84-86], which couldalso affect subsequent photolithographyprocesses. The controlled introduction of misfit

dislocation arrays results in a high qualityrelaxed SiGe substrate for the epitaxialdeposition of the strained silicon layer (typically15-20 nm). An Idsat of about 550 |iA/jim hasrecently been reported for Lg of 100 nm [87].

A variety of additional strained siliconstructures can also be fabricated. These includethe deposition of strained silicon on a fixedcomposition epitaxial Si(i_x)Gex layer on SOI aswell as the deposition of strained silicon directlyon SOI. In these SOI cases, both partiallydepleted (PD) and fully depleted (FD) structurescan be fabricated [88].

Difficult integration issues andmanufacturability, compatibility with silicon-on-insulator (SOI) and cost are mitigating issueswhich will be discussed below.

I l l

Ultra-Thin SOI/Multi-Gate SOI and(Vertical-Gate) FinFET

The spectrum of innovative deviceconfigurations includes alternative verticaltransistor structural configurations where thecurrent flow is either within the surface of thesilicon as in the FinFET, dependent on thecrystal direction utilized [36,37] or where thecurrent flow is perpendicular to the siliconsurface [38], often in conjunction with an ultra-thin, FD SOI substrate as well as the semi-ballistic transistor [89]. One configuration positsa double gate CMOS device with an undoped,(or lightly doped) ultra-thin FD SOI substrate[90]. The utilization of a double-gateconfiguration for dynamic Vt operation hasalready been discussed for DRAM applications[91]. The benefits of an assy metrical, self-aligned double gate CMOS device compared to asymmetrical double gate structure has also beentheoretically modeled [92]. Other configurationsfor the ultimate CMOS silicon and end-of-the-roadmap devices have also recently beendiscussed [46,47].

FD single and double-gate transistor structure[17,94], with several of the relative benefits anddisadvantages summarized in Table 2.

In that regard, one might consider multiplegate structures [95-97]. The concurrentutilization of multiple gate structures may alsoalleviate, to some extent, the difficulties in thecharacterization and metrology (P/T analysis) ofthe silicon thickness for fully depleted (FD)applications. That is, it appears that the FDthickness for single-gate MOSFETs is requiredto be as small as one-third of Lg, to control SCE[98], requiring severe precision to tolerance(P/T) ratios, as generically discussed in [99] (forLg). The multi-gate structures generally allow arelaxation of this thickness (1/3 Lg) requirement.It is also anticipated that various multi-gateconfigurations will mitigate the SCE [17,94,97].One such embodiment is the FinFET,schematically illustrated in Figure 6 [36,37]. Thefabrication of the fin connecting the source anddrain appears to have the advantage of relativelyconventional processing, largely compatible withcurrent techniques. Nevertheless, significantissues must be addressed such as the surface

Planar Bulk Partially DepletedSOI

Fully DepletedSOI

Figure 4. Schematic illustrations of transistor cross-sections for planar bulk, partially depleted (PD) and fullydepleted (FD) SOI, courtesy of M. Bohr [93] and Intel Corporation. The planar bulk and PD SOIstructures still require shallow extension junctions and halo implants to control SCE but are notillustrated herein for convenience. Reproduced by permission of The Electrochemical Society, Inc.

Planar, bulk polished and epitaxial wafers aswell as PD and even FD SOI silicon materials,present SCE scaling issues. Short channel effects(SCE) become especially significant as Lphysapproaches the 20 nm and, especially, the sub-10nm regime. Figure 4 schematically illustratesthese various material configurations [93] whileTable 1 summarizes several of their advantagesand disadvantages [15,17,43,93]. Figure 5schematically illustrates an ultra-thin silicon film

roughness of the edge of the fin which willdegrade the effective mobility of the chargecarriers in the inversion layer and methodologiesfor appropriate annealing to restore the mobilityis required.

The multi-gate structures generally allow arelaxation of the thickness (1/3 Lg) requirement.For example, Figure 7 illustrates the siliconthickness requirement for a single, conventional

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Transistor Type

Planar Bulk

Partially Depleted SOI

Fully Depleted SOI

Advantages

Wafer cost / availability

Lower junction capacitanceBoating body performancemprovement by device and circuitdesign;elimination of "body effect" inplanar bulk20-25% reduced process time andmproved manufacturing "ease"compared to planar bulk25-35% improvement in deviceperformance compared to planar bulkReduction in chip power by 1 .7-3.0xcompared to planar bulkLower soft-error rate compared toplanar bulkRecovery of Moore's law growthprojections

Lower junction capacitance

Operational beyond 300°C

Threshold voltage and leakagecurrent less sensitive than planarbulk

Improved swing leading to lower off-current

No floating body and history effects

Less dependence on device andcircuit design

Multiple-gate structures alleviatesneed for ultra-thin SOI

Lower soft-error rate compared toplanar bulkRecovery of Moore's law growthprojections

Disadvantages

SCE scaling difficultHigh doping effects and statisticalvariationParasitic junction capacitance

SCE scaling difficult

Floating body and history effects

Wafer cost / availability

High doping effects and statisticalvariation

SCE scaling difficultHigh source / drain seriesresistanceSensitivity to silicon thickness(ultra-thin SOI) to ensureacceptable DIBLSource / drain contact requiresthickened silicon, compared toultra-thin body, to decrease seriesresistanceWafer cost / availability

Table 1. Brief comparison of the advantages and disadvantages of various transistor types [15,17,43,93].

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Ultra-thin film, single-gate SOI

1Ultra-thinsiliconfilm

Double-gate

Ultra-thinsiliconfilm

Figure 5. Schematic illustrations of transistor cross-sections for fully depleted (FD) SOI with single- anddouble-gate structures (based on [17,94]).

Fully DepletedSOI Transistor

Single Gate

Double Gate

Advantages

Lower junctioncapacitanceReduced channel dopingfor metal gate electrode,fully depleted

Enhanced scalabilityNear ideal subthresholdslope, SLower junctioncapacitanceReduced channel dopingfor metal gate electrode,fully depletedAbout 2x drive currentfor symmetric gateAssymetric gatecapability for dynamic Vt

operation

Disadvantages

SCE scaling difficult

Sensitivity to siliconthickness

Wafer cost / availability

Complex process

Wafer cost / availability

About 2x gate capacitance

Advanced devicestructure, difficult tofabricate at present

Table 2. Brief comparison of the advantages and disadvantages of ultra-thin silicon film, fully depleted single-and double-gate SOI transistors [17,94].

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Figure 6. FinFET structure, after T-J. King and C. Hu [36,37].

planar CMOS structure in comparison to a tri-gate structure [97]. In the former case, an Lg of20 nm would require a silicon FD thickness of~7 nm, necessitating a significant P/Trequirement. On the other hand, the tri-gatestructure theoretically relaxes the critical siliconbody thickness to approximately Lg, inasmuch asthe inversion layer is being formed via threesurfaces. In a similar manner, even a double gatestructure offers a P/T relief as the silicon body

thickness is increased to about 2/3 of Lg,although the tri-gate structure offers further P/Trelief, see Figure 8 [97] (note in this case thebody thickness for the double-gate case isrepresented by the symbol Wsi). Other relatedconfigurations such as the omega (Q) gate havealso been discussed [100]. Measurement of thefin dimensions is a significant characterizationissue for such advanced device structures.

115

si

140 4

m J

9 i

fri-giiii

ctitit

ft t|| I

IS 40

PS¥ ^ Piyil^^^plirliiii

Figure 7. Tri-gate relaxes T$ j requirement of single-gate, courtesy of R. Chau [97] and Intel Corporation.

Figure 8. Tri-gate relaxes W$ j requirement of double-gate, courtesy of R. Chau [97] and Intel Corporation.

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In a more far-reaching sense, one mayconsider the fin of the FinFET as a quantum wireMOSFET [101], in conjunction with the front-end fabrication approaches briefly noted earliersuch as high-k gate dielectric, metal gate, lowresistance source and drain in conjunction with aFD SOI substrate material (strained Si may alsobe utilized). Furthermore, there appears theopportunity for multiple fins, with multiple gatesas appropriate, increasing the total source todrain current.

The relative immaturity of SOI materialscompared to bulk and expitaxial silicon,however, will result in significant challenges forthe understanding of SOI specific defects andtheir impact on device performance and yield ina production environment [102-105]. Forexample, gettering methodologies will be asignificant issue for SOI [106,107]. The reducedquality previously seen with the BOX layer onSIMOX, compared to a conventionally formedSiO2 layer, has suggested an enhanced transportof Fe through the SIMOX BOX layer [108]. Asimilar phenomenon has also been observed forCu and Ni in SIMOX wafers [109]. Metrologymethods for many of the SOI defect categoriesrequire destructive chemical etching thatdecorate but do not uniquely distinguish varioustypes of crystal defects [11]. These variousdefects may not all have the same origin, size orimpact on device performance and yield and,therefore, may exhibit different effects ondegrading or killing device characteristics. Non-destructive and fast-turn around methods areneeded for measurement of the electricalproperties and structural defects in SOImaterials. The role of the background interstitialoxygen [110] and carbon [111] in the starting CZmaterial are also issues that will need to becomprehended. Clearly, this is an area that willrequire significant further research, especiallywith the various forms of BOX being explored.

Metrology for SOI wafers is also asignificant challenge. One critical example is theassessment of SOI material properties with anedge exclusion of 2 mm per the ITRS [11]. Theparticle metrology readiness grades for generalpolished and epitaxial wafer characteristics arenot applicable for SOI wafers. Interferenceeffects arising from multiple reflections from theSi and BOX layers fundamentally alter theresponse of optical metrology tools compared topolished and epitaxial wafers, generallydegrading the measurement capability. Forinstance, the current particle size capability forSOI wafers is 120-150 nm as compared to 90 nm

for the 90 nm technology generation in aproduction fab, although 65 nm particles can beroutinely measured on current tools. Theanticipated shift from capacitive to opticalmeasurement of wafer site flatness beyond the90 nm technology generation appears to havebeen resolved for site flatness measurements[11]. Finally, the characterization and metrologyissues for the various strained siliconconfigurations (spatially varying Si:Gecomposition content, threading dislocations andassociated defects as well as unique surfaceroughness issues) will require significantattention [37,84-86].

PROGNOSIS

The drive to service a broad variety ofleading-edge 1C applications such as micro-processors (MPU), servers, smart power, and RFsignal processors [14] has concurrently beenaccomplished utilizing a plethora of SOIfabrication methodologies [43,88] which, inconjunction with high-k gate dielectrics, metalelectrodes, elevated source-drain, strained siliconlayers and eventually, perhaps, FinFETstructures will drive us to the ultimate CMOSdevice structure. The applicability of SOImaterials for these leading-edge 1C applicationsappears warranted in the recovery of the growthexpectations anticipated with Moore's law andthe ITRS, especially with 3-D deviceconfigurations [112-115], resulting in a largenumber of unique device configurations. Asnoted earlier, the assessment of productivitygains, whether by staying on the productivitycurve or increasing manufacturing effectiveness,may have to be expanded. Rather, modelingproductivity—the identification of newproductivity measures—will be required [12].

Finally, it may be appropriate to briefly notethat several alternative novel device structuresbeyond CMOS have been described [11]. In anycase, it seems that these alternatives will need tobe capable of integration with Si-CMOS formaximum leverage, operate at room-temperaturewith the capability of system-on-chip (SOC)applications, including gigabytes of memorystorage and portable (to ensure the opportunityfor a mass market). One such example is amolecular single-electron latching switchbetween gold nano wires, which has beendescribed in conjunction with an SOI MOSFETintegrated system [116]. Significantopportunities for silicon-based ICs will continuefor at least the next 100 years [117], including

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combinatorial configurations with alternativenovel devices beyond CMOS.

SUMMARYPlanar MOSFET device scaling has taken

the 1C industry from the realm of physical gatelengths of, for example, 7.5 jum for the 4KDRAM to about 45 nm for the high-performanceMPU for the 90 nm technology generation.Scaling has been the driver in meeting theprojected overall chip performance, density andpower requirements. Different end-userapplications such as a high-performance MPU ora low standby power device will, of courserequire different metrics. Front-end material andprocess solutions will include high-k gatedielectrics, metal gate electrodes, elevatedsource/drain, spike annealing and, eventually,novel source/drain annealing and dopingprocedures as well as strained silicon and,probably, SOI. The ensurance of continuedscaling to the 22 nm technology generation(Lg = 9 nm) or so appears soluble withincurrently understood physical principles[15-17,32]. Effective non-planar solutions mustrectify significant process issues for verticaltransistors in conjunction with multi-gate and FDSOI, in some combinatorial mix. The ultimateCMOS MOSFET with Lg < 10 nm may be alightly doped channel (strained silicon orgermanium), ultra-thin body SOI FinFET (withmultiple fins and, perhaps, multiple gates), inconjunction with the high-k gate dielectric,multi-gate metal electrodes (approximately mid-gap work function), elevated source and drain,etc. Beyond that regime, however, an emphasison alternative novel device structuralconfigurations appears essential [11,116,118].

In reality, however, each 1C manufacturerwill utilize that portion of the potentialmanufacturing process tools and devicestructures available to ensure their optimalparticipation in the particular markets they serve.Perhaps our 1C industry has been best describedby Gordon Moore who has recently noted"...and you are once again reminded that this isno longer just an industry, but an economic andcultural phenomenon, a crucial force at the heartof the modern world" [119]. Indeed, Moore hasnoted that "no exponential is forever: but"forever" can be delayed" [120], which couldaccount for the 1C community's drive tomaintain the pace of Moore's law.

ACKNOWLEDGEMENTS

The authors appreciate discussions and theutilization of a number of figures for both themanuscript (and the oral presentation) fromM. Bohr, D. Buchanan, D. Chapman, R. Chau,J. Chung, R. Cleavelin, J-P Colinge, M. Currie,P. Gargini, E. Gusev, J. Hergenrother, J. Hoyt,C.Hu, J. Hutchby, T-J. King, K. Likharev,G. Lucovsky, V. Misra, T. Mizuno, S. Monfray,P. Mooney, Y. Nishi, C. Osburn, G. Parsons,D. Schlom, T. Skotnicki, B. Wallace, G. Wilk,R. Wise and F-L Yang. The assistance of boththe FEP Division and Fab personnel atInternational SEMATECH and our colleagues atthe FEP-RC, IMEC, ASM and AMAT is alsoappreciated.

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