Status of Global Trigger Global Muon Trigger Sept 2001 Vienna CMS-group presented by A.Taurok.
The Trigger Prototype Board Status
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Transcript of The Trigger Prototype Board Status
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The Trigger Prototype Board Status
Marco Grassi
INFN - Pisa
On behalf of trigger group
D. NicolòF. Morsani S. Galeotti M. Grassi
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Hardware: board Type 1•VME 6U•A-to-D Conversion
– FADC with differential inputs bandwidth limited
•Trigger– LXe calorimeter– timing counters
•No use for the tracking chambers
•I/O– 16 PMT signals– 2 LVDS transmitters– 4 in control signals
FADC FPGA
ControlFPGA
PMT16
16 x 10
4
48
48
VME
SyncClockSyncTriggerStart
4
LVDS Trans 48
LVDS TransType 2
boards
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Hardware: board Type 2
•VME 9U•Matched with the Type 1 boards
•I/O– 10 LVDS receivers– 2 LVDS
transmitters– 4 in control signals– 3 out signals
FPGA
ControlFPGA
Type 110 x 48
4
48
48
SyncClockSyncTriggerStart
4 VME
LVDS Trans
LVDS Trans
48
LVDS Rec
18
18
10 x 18
to next Type 2
TriggerSyncStart 3
Out3
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Type2
Hardware: system structure
LXe inner face(312 PMT)
Type2
. . . 20 boards
20 x 48
Type1Type1
Type116
4 Type2
2 boards
. . . 10 boards
10 x 48
Type1Type1
Type116
4
LXe lateral faces(208 PMT)
(120x2 PMT)(40x2 PMT)
Type2
1 board
. . . 12 or 6 boards
12 x 48
Type1Type1
Type116
4
Timing counters(160 PMT)
or(80 PMT) Type2
Type2
2 or 1
boards
4 x 48
1 board
4 x 48
2 x 48
2 VME 6U
1 VME 9U
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Present status• Prototype board: Type0
– Modified Type1 :• Check of the connectivity with the Type2• Study the FADC coupling• Verify the chosen algorithms
• Selected components (all delivered)• Main FPGA XCV812E-8-FG900 and XCV18V04 config. ROM• Interface and control CPLD XC95288XL-FG256• ADC AD9218 (dual 10 bits 100 MHz)• Clock distribution CY7B993V (DLL multi-phase clock buffer)• LVDS serializer DS90CR483 / 484 (48 bits - 100 MHz - 5.1 Gbits/s)• LVDS connectors 3M Mini-D-Ribbon • Analog input by 3M coaxial connectors• Control and debug signals in LVDS standard
• FPGA design completed– FPGA design and simulation completed (runs at 100 MHz)– VHDL parameterization is ready
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Prototype board : Type 0•VME 6U•A-to-D Conversion•Trigger•I/O
– 16 PMT signals– 2 LVDS transmitters– 4 in/2 out control signals
•Complete system test
LVDS Rec
SyncTriggerStart
FADC FPGA
ControlCPLD
PMT16
16 x 10
4
48
48
VME
SyncClockSyncTriggerStart
4
48
LVDS Trans
3Out
2 boards16
16
4
Type0
Type0
TriggerStart
4
Analog receivers
Spare in/out
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The Analog input stage
• BW limitation
• Unipolar or bipolar inputs
• Variable gain
• Pedestal adjust
AD8138
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•Board Design completed – Implementation by means of
CADENCE– Schematic simulation completed– Components footprints checked
– Board routing ready• 10 layers
4 GND Power
6 signals• DC/DC converters• A32 mode• Block transfer
•Board production– PCB producer contacted: ready
for a production offer
– Delivery: end of July
– Test: September
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DRS Chip
• Prototype received Nov. 02• Tests Dec. 02 – April 03• Digital part works perfectly• Analog parts requires redesign• DLL and VME board built by Siena
• Prototype received Nov. 02• Tests Dec. 02 – April 03• Digital part works perfectly• Analog parts requires redesign• DLL and VME board built by Siena
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Test results
fsamp [GHz]
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00
fsamp [GHz]
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
1.500 1.700 1.900 2.100 2.300 2.500 2.700 2.900 3.100 3.300 3.500
fsamp [GHz]
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
0.000 10.000 20.000 30.000 40.000 50.000 60.000 70.000
fsamp[GHz] vs. Vcontrol[V]
fsamp[GHz] vs. Vdd[V]
fsamp[GHz] vs. T[deg. C]
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Running Domino WaveRunning Domino Wave
Denable
Dtap
Jitter after 32 turns: ~1ns32 Domino cycles @ 320ns
SR_CLKSR_RESET
SRIN
SROUT
#768
Readout Shift RegisterReadout Shift Register
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DLL Design
R. Paoletti, N. Turini, INFN
In
PhaseComparator
Ext. quartzclock
DLLVspeed
• DLL works with jitter of 200 ps RMS
• Siena (N. Turini, R. Paoletti, MAGIC) designs VME board
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DRS Readout
Input pulse Digitized output pulse
5ns risetime 8ns risetime
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Problems in analog part
PHI
PHI
Bus
Csamp
source
draingate Capacitances:
Gate-Bulk: 10.6 fFSource-Bulk: 13.5 fFDrain-Bulk: 2.4 fF
Bus capacitance too high (110pF)
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DRS Redesign
• Reduce bus-bulk capacitance by 6x• Reduce bus-bus capacitance• Use current-mode readout
write
read
C
. . .
RI
Vout
G. Varner, Univ. of Hawaii:STRAW2 chip
Vin
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Plans
• UMC 0.25m technology• Next Submission Oct. 20th • Production time ~9 weeks• VME board design in parallel (Siena)• Rectangle 5 x 5 mm2
• Reduce minimum sampling speed to 500 MHz (for DC)
• Daisy chain mode for N x 1024 bins• Dual-channel for deadtimeless
operation• 4 chn. Q mode + 4 chn. I mode• Production run spring 2004
• UMC 0.25m technology• Next Submission Oct. 20th • Production time ~9 weeks• VME board design in parallel (Siena)• Rectangle 5 x 5 mm2
• Reduce minimum sampling speed to 500 MHz (for DC)
• Daisy chain mode for N x 1024 bins• Dual-channel for deadtimeless
operation• 4 chn. Q mode + 4 chn. I mode• Production run spring 2004
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DRS options
Input
Dom
ino W
ave
Daisy-chain mode
Input
Readout
Dual-channel mode
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DRS (DAQ)
2002 2003 2004 2005
Test MilestoneAssemblyDesign Manufactoring
2nd Prototype
Tests1st Prototype
Boards & Chip Test
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DAQ System
PMT ActiveSplitter
~7m to trigger (~20m)
area
monitor
~2m
DRSBoard
(16chn)
DC Pre-Amp DRSBoard
(16chn)
~7m
SIS3100
10 VME crates
800 + 160
1920
opticalfiber (~20m)
Trigger
GigabitEthernet
Front-End PCs
On-line farm
Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)
Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)
storage
Fitted data:10 Hz waveform data -> 1.2 MB/sec90 Hz ADC / TDC data -> 0.9 MB/sec
Raw data:2880 channels100 Hz50% / 10% / 10% occupancy2kB / waveform -> 5 x 25 MB/sec.
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Waveform analysis
• Zero suppression in FPGA• Single hit
– ADC/TDC derived in FPGA
• Multiple hit– Waveform compressed in
FPGA (2x12 bit -> 3 Byte)– Waveform fitted /
compressed in PC cluster
• Store ADC/TDC only for “calibration” events
• Store (lossless) compressed waveforms for MEG candidates
• Zero suppression in FPGA• Single hit
– ADC/TDC derived in FPGA
• Multiple hit– Waveform compressed in
FPGA (2x12 bit -> 3 Byte)– Waveform fitted /
compressed in PC cluster
• Store ADC/TDC only for “calibration” events
• Store (lossless) compressed waveforms for MEG candidates
OriginalWaveform
Difference Of Samples
Threshold in DOS
Region for pedestal
evaluationintegration area
ADC1/TDC1
ADC2/TDC2
T
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ROOT for online analysis• ROOT becomes more stable and is now widely
used• “Online extensions” are underway (life display of
histos and N-tuples)• Propose to use ROOT for online monitoring and
single event display, CARROT for Web display• For offline analysis, keep possibility to use ROOT
or PAW
• ROOT becomes more stable and is now widely used
• “Online extensions” are underway (life display of histos and N-tuples)
• Propose to use ROOT for online monitoring and single event display, CARROT for Web display
• For offline analysis, keep possibility to use ROOT or PAW
FE Analyzer
*.mid
ROOTGUI
offlineanalysisROOT
*.root
offlineanalysisHBOOK
*.rz PAW
ROOT
online offline