The PowerPC Models in Bluespec - csg.csail.mit.edu
Transcript of The PowerPC Models in Bluespec - csg.csail.mit.edu
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IBM T. J. Watson Research Center
© 2007 IBM Corporation
The PowerPC Models in Bluespec
Jessica Tseng, K Ekanadham, Pratap PattnaikT J Watson Res. Lab., IBM, Yorktown Heights, NY
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IBM T. J. Watson Research Center
© 2007 IBM Corporation2 The First Bluespec Workshop, MIT 08/13/2007
PowerPC Architecture Spans Wide Range of Markets
embedded systems
automotives
cell broadband engineservers
super computers (BG/L)
powerarchitecture
journey to mars
game consoles
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IBM T. J. Watson Research Center
© 2007 IBM Corporation3 The First Bluespec Workshop, MIT 08/13/2007
Flexible Support Structures For Software
Multi-Threading
VirtualizationSupport
SophisticatedCache
Protocols
Large PageSizes
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IBM T. J. Watson Research Center
© 2007 IBM Corporation4 The First Bluespec Workshop, MIT 08/13/2007
Our Research Goal and Vision
Goal:
– Promote Power architecture as building block for a wide range of systems and find innovative ways to extend Power architecture with accelerator for specific applications.
Vision:
– Create an ecosystem to foster Power architecture and eseof its use for system research by the community.
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IBM T. J. Watson Research Center
© 2007 IBM Corporation5 The First Bluespec Workshop, MIT 08/13/2007
Bluespec PowerPC Processor Model
Since Bluespec advertises itself as a high-level synthesis solution that can reduce the design and modeling times, it is ideal for rapid design changes and experimentations.
– Collaborate with MIT to create a public PowerPC ISA compatible core from the public available documents (Book I, II, and III) using Bluespec.
– Further synthesize the Bluespec generated verilog code onto FPGAsfor real-time evaluation and simulation.
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IBM T. J. Watson Research Center
© 2007 IBM Corporation6 The First Bluespec Workshop, MIT 08/13/2007
The Basic PowerPC Processor ModelSimple in-order pipeline, with standard PowerPC ISA.
Support for multiple threads per core.
Support for address translation with variable page sizes.
Support for multiple cores with shared caches in a node.
Support for coherency and synchronization across nodes.
IU
XU FU
L1
L2interface
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IBM T. J. Watson Research Center
© 2007 IBM Corporation7 The First Bluespec Workshop, MIT 08/13/2007
Thank you!