The overview of Networking Technology & New Generation Processors Boxuan Gu Chi Chau CS-5212-5-2004.

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The overview of Networking The overview of Networking Technology Technology & & New Generation Processors New Generation Processors Boxuan Gu Boxuan Gu Chi Chau Chi Chau CS-521 CS-521 2-5-2004 2-5-2004

Transcript of The overview of Networking Technology & New Generation Processors Boxuan Gu Chi Chau CS-5212-5-2004.

The overview of Networking The overview of Networking Technology Technology

& & New Generation ProcessorsNew Generation Processors

Boxuan GuBoxuan GuChi ChauChi ChauCS-521CS-521

2-5-20042-5-2004

Part 1Part 1Networking TechnologyNetworking Technology

The lecture consists of The lecture consists of two partstwo parts

Network ArchitectureNetwork Architecture Ethernet technologyEthernet technology

Network Architecure-Network Architecure-OSI OSI reference modelreference model

OSIOSI The OSI model provides a conceptual The OSI model provides a conceptual

framework for communication between framework for communication between computers, but the model itself is not a computers, but the model itself is not a method of communication. Actual method of communication. Actual communication is made possible by using communication is made possible by using communication protocols. communication protocols.

In the context of data networking, In the context of data networking, a a protocolprotocol is a formal set of rules and is a formal set of rules and conventions that governs how computers conventions that governs how computers exchange information over a network exchange information over a network medium. A protocol implements the medium. A protocol implements the functions of one or more of the OSI layers.functions of one or more of the OSI layers.

OSI-InteractionOSI-Interaction

OSI-OSI-EncapsulationEncapsulation

TCP/IPTCP/IP

TCP/IPTCP/IP-IP-IP The Internet Protocol (IP) is a The Internet Protocol (IP) is a

network-layer (Layer 3) protocol network-layer (Layer 3) protocol that contains addressing that contains addressing information and some control information and some control information that enables packets information that enables packets to be routed. to be routed.

IP has two primary responsibilities: IP has two primary responsibilities: 1.1. providing connectionlessproviding connectionless2.2. best-effort delivery of datagrams best-effort delivery of datagrams

IP Packet FormatIP Packet Format

IP address formatIP address format

IP address…

TCP/IP-TCP/IP-TCPTCPTransmission Control ProtocolTransmission Control Protocol

•The TCP provides reliable transmission of data in an IP environment. TCP corresponds to the transport layer (Layer 4) of the OSI reference model. Among the services TCP provides are stream data transfer, reliability, efficient flow control, full-duplex operation, and multiplexing.

•TCP offers reliability by providing connection-oriented, end-to-end reliable packet delivery through an internetwork.

TCP/IP-UDPTCP/IP-UDPUser Datagram ProtocolUser Datagram Protocol

The User Datagram Protocol (UDP) is The User Datagram Protocol (UDP) is a connectionless transport-layer a connectionless transport-layer protocol (Layer 4) that belongs to the protocol (Layer 4) that belongs to the Internet protocol family. Internet protocol family.

UDP is basically an interface between UDP is basically an interface between IP and upper-layer processes. UDP IP and upper-layer processes. UDP protocol ports distinguish multiple protocol ports distinguish multiple applications running on a single device applications running on a single device from one another. from one another.

UDP-UDP-packet headerpacket header

IPV6IPV6

Disadvantage of IP v4:Disadvantage of IP v4:

1.1. 32 bits address is limited32 bits address is limited

2.2. Routing is not efficientRouting is not efficient

3.3. Bad support for mobile deviceBad support for mobile device

4.4. Security needs growSecurity needs grow

4bits version

8bits traffic class

20 bits flow label

16 bits payload length

8 bits next header

8 bits hop limit

128 bits source address

128 bits destination address

IPv6 Packet Header FormatIPv6 Packet Header Format

IPV6 IPV6 Version Number:Version Number: The version is a 4-bit The version is a 4-bit

field as in IPv4. The field contains the field as in IPv4. The field contains the number 6 for IPv6, instead of the number 6 for IPv6, instead of the number 4 for IPv4.number 4 for IPv4.

Traffic Class:Traffic Class: The Traffic Class field is The Traffic Class field is an 8-bit field similar to the type of an 8-bit field similar to the type of service (ToS) field in IPv4. The Traffic service (ToS) field in IPv4. The Traffic Class field tags the packet with a traffic Class field tags the packet with a traffic class that can be used in Differentiated class that can be used in Differentiated Services. The functionalities are the Services. The functionalities are the same in IPv4 and IPv6.same in IPv4 and IPv6.

IPv6IPv6 Flow Label:Flow Label: The Flow Label field can The Flow Label field can

be used to tag packets of a specific be used to tag packets of a specific flow to differentiate the packets at the flow to differentiate the packets at the network layer. Hence, the Flow Label network layer. Hence, the Flow Label field enables identification of a flow field enables identification of a flow and per-flow processing by the routers and per-flow processing by the routers in the path.in the path.

Payload Length:Payload Length: Similar to the Total Similar to the Total Length field in IPv4, the Payload Length field in IPv4, the Payload Length field indicates the total length Length field indicates the total length of the data portion of the packet.of the data portion of the packet.

IPV6IPV6 Next Header:Next Header: Similar to the Protocol field in Similar to the Protocol field in

the IPv4 packet header, the value of the Next the IPv4 packet header, the value of the Next Header field in IPv6 determines the type of Header field in IPv6 determines the type of information following the basic IPv6 header. information following the basic IPv6 header.

Hop Limit:Hop Limit: Similar to the Time to Live field Similar to the Time to Live field in the IPv4 packet header, the value of the in the IPv4 packet header, the value of the Hop Limit field specifies the maximum Hop Limit field specifies the maximum number of routers (hops) that an IPv6 packet number of routers (hops) that an IPv6 packet can pass through before the packet is can pass through before the packet is considered invalid. considered invalid.

IPV6IPV6 Source Address:Source Address: The IPv6 source address The IPv6 source address

field is similar to the Source Address field in field is similar to the Source Address field in the IPv4 packet header, except that the field the IPv4 packet header, except that the field contains a 128-bit source address for IPv6 contains a 128-bit source address for IPv6 instead of a 32-bit source address for IPv4.instead of a 32-bit source address for IPv4.

Destination Address:Destination Address: The IPv6 destination The IPv6 destination address field is similar to the Destination address field is similar to the Destination Address field in the IPv4 packet header, Address field in the IPv4 packet header, except that the field contains a 128-bit except that the field contains a 128-bit destination address for IPv6 instead of a 32-bit destination address for IPv6 instead of a 32-bit destination address for IPv4.destination address for IPv4.

IPv6-extension headerIPv6-extension header

IPv6-extension headerIPv6-extension header1.1. Hop-by-Hop Options header.Hop-by-Hop Options header.

2.2. Destination Options header.Destination Options header.

3.3. Routing header.Routing header.

4.4. Fragment header.Fragment header.

5.5. Authentication header and Authentication header and Encapsulating Security Payload Encapsulating Security Payload headerheader

6.6. Upper-Layer header.Upper-Layer header.

IPv6-Addressing IPv6-Addressing schemescheme

IPv6 uses 16-bit hexadecimal number IPv6 uses 16-bit hexadecimal number fields separated by colons (:) to represent fields separated by colons (:) to represent the 128-bit addressing format making the the 128-bit addressing format making the address.address.

2031:0000:130F:0000:0000:09C0:876A:132031:0000:130F:0000:0000:09C0:876A:130B. 0B.

IPv6-Addressing schemeIPv6-Addressing scheme

IPv6 addresses consist of a prefix and a IPv6 addresses consist of a prefix and a local partlocal part

(like in IPv4)(like in IPv4) - Example:- Example: 3FFE:400:280:0:0:0:0:1/483FFE:400:280:0:0:0:0:1/48 here the first 48 bits a fixed (prefix) and here the first 48 bits a fixed (prefix) and

the other 80the other 80 bits will be assigned in the local subnetbits will be assigned in the local subnet

IPv6-Addressing schemeIPv6-Addressing scheme

In IPv6, there 3 types of addresses:In IPv6, there 3 types of addresses:

1. Unicast

2. Multicast

3. Anycast (new in IPv6)

IPv6-Addressing IPv6-Addressing schemescheme-unicast-unicast

IPv6-Addressing schemeIPv6-Addressing scheme-Multicast-Multicast

IPv6-Addressing IPv6-Addressing schemescheme-Anycast-Anycast

Packets sent to an anycast address Packets sent to an anycast address or list of addresses are delivered to or list of addresses are delivered to the nearest interface identified by the nearest interface identified by that address. Anycast is a that address. Anycast is a communication between a single communication between a single sender and a list of addresses, sender and a list of addresses,

Part 2: Ethernet

EthernetEthernet

EthernetEthernetMAC Data Frame FormatMAC Data Frame Format

Ethernet-10gigabit Ethernet-10gigabit EthernetEthernet

10 Gigabit Ethernet is Ethernet. 10 10 Gigabit Ethernet is Ethernet. 10 Gigabit Ethernet uses the IEEE Gigabit Ethernet uses the IEEE 802.3 Ethernet media access control 802.3 Ethernet media access control (MAC) protocol, the IEEE 802.3 (MAC) protocol, the IEEE 802.3 Ethernet frame format, and the IEEE Ethernet frame format, and the IEEE 802.3 frame size. 10 Gigabit 802.3 frame size. 10 Gigabit Ethernet is full duplex.Ethernet is full duplex.

Ethernet-10gigabit Ethernet-10gigabit EthernetEthernet

Technology and StandardTechnology and Standard The IEEE 802.3ae 10 Gigabit Ethernet The IEEE 802.3ae 10 Gigabit Ethernet Task Force was chartered with Task Force was chartered with developing the 10 Gigabit Ethernet developing the 10 Gigabit Ethernet Standard. Standard.

This group is a subcommittee of the This group is a subcommittee of the larger 802.3 Ethernet Working Group. larger 802.3 Ethernet Working Group. In contrast to previous Ethernet In contrast to previous Ethernet standards, 10 Gigabit Ethernet targets standards, 10 Gigabit Ethernet targets three application spaces: the LANs, three application spaces: the LANs, MANs, and WANs. MANs, and WANs.

Cont.Cont. Gigabit Ethernet is no longer a shared Gigabit Ethernet is no longer a shared

domain, half-duplex technology. domain, half-duplex technology. Because there are no packet collisions in a Because there are no packet collisions in a

full-duplex link, the link distances are full-duplex link, the link distances are determined by optics and not by the determined by optics and not by the diameter of an Ethernet collision domain. diameter of an Ethernet collision domain.

10 Gigabit Ethernet will also be a full-10 Gigabit Ethernet will also be a full-duplex, switched technology, maintaining duplex, switched technology, maintaining compatibility with the 802.3 Ethernet MAC compatibility with the 802.3 Ethernet MAC protocol and the Ethernet frame format.protocol and the Ethernet frame format.

Cont.

10 gigabit ethernet 10 gigabit ethernet Layer 1: Physical Layer Devices Layer 1: Physical Layer Devices

Contained within the PHY are several Contained within the PHY are several sublayers that perform these sublayers that perform these functions, including the physical functions, including the physical coding sublayer (PCS) and the optical coding sublayer (PCS) and the optical transceiver or physical media transceiver or physical media dependent (PMD) sublayer for fiber dependent (PMD) sublayer for fiber media. The PCS is made up of coding media. The PCS is made up of coding (for example, 8b/10b) and serializer or (for example, 8b/10b) and serializer or multiplexing functions. multiplexing functions.

Cont.Cont.

10g Ethernet define two kinds of PHY:10g Ethernet define two kinds of PHY: the LAN PHY the LAN PHY the WAN PHYthe WAN PHY

WAN PHYWAN PHY

SONET Friendly SONET Friendly Enables use of Enables use of

SONET SONET infrastructure for infrastructure for Layer 1 transport: Layer 1 transport:

SONET ADMs, SONET ADMs, DWDM DWDM Transponders, Transponders, optical optical regeneratorsregenerators

Not SONET Not SONET Compliant Compliant

Connects to Connects to SONET access SONET access devices but not devices but not directly to SONET directly to SONET infrastructure infrastructure

Cont.Cont.

SONET Friendly SONET Friendly Requires some Requires some

SONET features: SONET features: OC-192 link speed OC-192 link speed SONET framing SONET framing MinimalPath/MinimalPath/

Section/Line Section/Line overheard overheard processing processing

Not SONET Not SONET CompliantCompliant

Avoids most costly Avoids most costly aspects of SONET: aspects of SONET:

No TDM support No TDM support Concatenated OC-192c Concatenated OC-192c

only only Does not require Does not require

meeting SONET grid meeting SONET grid laser specifications, laser specifications, jitter requirements, jitter requirements, stratum clocking stratum clocking

Minimal operations, Minimal operations, administration, administration, maintenance, and maintenance, and provisioning (OAM&P) provisioning (OAM&P)

LAN PHYLAN PHY

10 Gigabit defines a LAN PHY that, 10 Gigabit defines a LAN PHY that, with simple encoding, will transmit with simple encoding, will transmit Ethernet packets on dark fiber and Ethernet packets on dark fiber and dark wavelengths.dark wavelengths.

The LAN PHY is intended to support The LAN PHY is intended to support the existing Ethernet applications at the existing Ethernet applications at ten times the bandwidth with the ten times the bandwidth with the most cost-effective solution.most cost-effective solution.

Cont.Cont.

Cont.Cont. Both the LAN and WAN PHY will Both the LAN and WAN PHY will

support each physical medium-support each physical medium-dependend (PMD) sublayer and, dependend (PMD) sublayer and, therefore, support the same therefore, support the same distances. These PHYs are distances. These PHYs are distinguished solely by the PCS. distinguished solely by the PCS.

The WAN PHY differs from the LAN The WAN PHY differs from the LAN PHY by the inclusion of a simplified PHY by the inclusion of a simplified SONET framer.SONET framer.

Cont.Cont.10 Gigabit Ethernet Link Distance and Media Goals

At least 65 meters over multimode fiber

At least 300 meters over installed multimode fiber

At least 2 km over single-mode fiber

At least 10 km over single-mode fiber

At least 40 km over single-mode fiber

Application of 10GEApplication of 10GE

10 Gigabit in the LAN

Cont.Cont.10 Gigabit Ethernet Metropolitan Network

Part 2Part 2AMD & IntelAMD & Intel

Latest Desktop & Server Latest Desktop & Server ProcessorsProcessors

AMDAMD Desktop: AMD Desktop: AMD

Athlon 64 FX, AMD Athlon 64 FX, AMD Athlon 64Athlon 64

Server: AMD Server: AMD OpteronOpteron

IntelIntel Desktop: Intel Desktop: Intel

Pentium 4 w/ HT, Pentium 4 w/ HT, Intel Pentium 4 Intel Pentium 4 Extreme EditionExtreme Edition

Server: Intel Server: Intel Itanium 2, XeonItanium 2, Xeon

Desktop Processor Desktop Processor PricingPricing

AMD Athlon 64 FX-AMD Athlon 64 FX-51 $73351 $733

AMD Athlon 64 AMD Athlon 64 3400+ $4173400+ $417

AMD Athlon 64 AMD Athlon 64 3200+ $2783200+ $278

AMD Athlon 64 AMD Athlon 64 3000+ $2183000+ $218

Intel Pentium 4 Intel Pentium 4 Extreme Edition Extreme Edition 3.4Ghz $9993.4Ghz $999

Intel Pentium 4 Intel Pentium 4 3.4Ghz w/ HT $4243.4Ghz w/ HT $424

Intel Pentium 4 3.2 Intel Pentium 4 3.2 Ghz (Prescott) w/ Ghz (Prescott) w/ HT $417HT $417

Processor TimelineProcessor Timeline

DateDate IntelIntel AMDAMD

2/2/20042/2/2004 P4 3.4Ghz, P4 3.2E Ghz, P4 EE P4 3.4Ghz, P4 3.2E Ghz, P4 EE 3.4Ghz3.4Ghz

1/6/20041/6/2004 Athlon 64 3400+Athlon 64 3400+

9/24/2009/24/20033

P4 EE 3.2 GhzP4 EE 3.2 Ghz Athlon 64 FX-51, Athlon 64 FX-51, 3200+3200+

6/23/2006/23/20044

P4 3.2 GhzP4 3.2 Ghz

5/13/2005/13/20033

Athlon XP 3200+Athlon XP 3200+

4/14/2004/14/20033

P4 3.0 Ghz 800MhzP4 3.0 Ghz 800Mhz

2/10/2002/10/20033

Athlon XP 3000+Athlon XP 3000+

11/14/2011/14/200202

P4 HT 3.06GhzP4 HT 3.06Ghz

Traditional Intel Traditional Intel roadmaproadmap

Intel historically would move to a Intel historically would move to a smaller process, double the cache, smaller process, double the cache, increase clock speedsincrease clock speeds

It was true until first generation of It was true until first generation of Pentium 4 and when AMD was still Pentium 4 and when AMD was still strugglingstruggling

It is not the case for PrescottIt is not the case for Prescott

Intel Pentium 4 Intel Pentium 4 (Prescott)(Prescott)

Intel launched Pentium 4 Prescott on Intel launched Pentium 4 Prescott on February 2February 2ndnd

Not P5 just 3Not P5 just 3rdrd generation of P4 generation of P4 Intel CEO Paul Otinelli discuss about Intel CEO Paul Otinelli discuss about

64-bit extension on Prescott64-bit extension on Prescott With enough cooler Prescott can With enough cooler Prescott can

overclock to 5Ghzoverclock to 5Ghz

P4 PrescottP4 Prescott

New ChangesNew Changes Prescott use 90 nm process instead of 130 Prescott use 90 nm process instead of 130

nm processnm process Double the L2 cache to 1 MBDouble the L2 cache to 1 MB Expand L1 data cache to 16 KB to improve Expand L1 data cache to 16 KB to improve

AGUs (address generation units)AGUs (address generation units) Add 13 new instructions aka SSE3Add 13 new instructions aka SSE3 Extend pipeline from 20 to 31 stagesExtend pipeline from 20 to 31 stages Process and die size dropProcess and die size drop Increasing scheduler queue size Increasing scheduler queue size Add a dedicated integer multiplierAdd a dedicated integer multiplier A new shifter/rotator logic block is replace A new shifter/rotator logic block is replace

in ALUsin ALUs

SSE3SSE3 After great success with the P4 SSE2 After great success with the P4 SSE2

instruction set (144 instructions) , SSE3 instruction set (144 instructions) , SSE3 added 13 more to make programmer’s life added 13 more to make programmer’s life easiereasier

fisttp: fp to int conversion fisttp: fp to int conversion addsubps, addsubpd, movsldup, movshdup, addsubps, addsubpd, movsldup, movshdup,

movddup: complex arithmetic movddup: complex arithmetic lddqu: video encoding lddqu: video encoding haddps, hsubps, haddpd, hsubpd: graphics haddps, hsubps, haddpd, hsubpd: graphics

(SIMD FP / AOS) (SIMD FP / AOS) monitor, mwait: thread synchronization monitor, mwait: thread synchronization

31 Pipeline Stages31 Pipeline Stages

Hyper-Threading Hyper-Threading TechnologyTechnology

Could increase performance up to 40%Could increase performance up to 40% HT enables multi-threaded software to HT enables multi-threaded software to

execute threads in parallel. It split execute threads in parallel. It split instructions into multiple streams so that instructions into multiple streams so that multiple processors could work on it.multiple processors could work on it.

The problem is not many software is The problem is not many software is taking advantage of HT. HT is big in taking advantage of HT. HT is big in graphic arena ex: Adobe taking big graphic arena ex: Adobe taking big advantage of HTadvantage of HT

Prescott ProblemsPrescott Problems

90 nm process not yet mature unlike 130 90 nm process not yet mature unlike 130 nmnm

90 nm process has heat and power problem90 nm process has heat and power problem Hold back 3.4E GhzHold back 3.4E Ghz Intent to produce limited edition Intent to produce limited edition SSE3 will be useful down the road, but SSE3 will be useful down the road, but

today’s software is not ready for ittoday’s software is not ready for it 31 stages pipeline would slow perfermance 31 stages pipeline would slow perfermance

with wrong predictionwith wrong prediction

Should you get Prescott?Should you get Prescott?

The real strength of Prescott is in its The real strength of Prescott is in its Hyper-Threading performanceHyper-Threading performance

Great for multitaskingGreat for multitasking Some applications Prescott beat Some applications Prescott beat

Extreme Edition in multitaskingExtreme Edition in multitasking

Pentium 4 Extreme Pentium 4 Extreme EditionEdition

Intel top of the line desktop Intel top of the line desktop processorprocessor

““Xeon” processor with P4 Extreme Xeon” processor with P4 Extreme Edition labelEdition label

It is more like “Emergency Edition” It is more like “Emergency Edition” rather than “Extreme Edition” to rather than “Extreme Edition” to repose AMD 64repose AMD 64

Optional 2 MB L3 cacheOptional 2 MB L3 cache

Intel RoadmapIntel Roadmap

AMD 64AMD 64 AMD 64 building a bridge from the 32 to AMD 64 building a bridge from the 32 to

64-bit world64-bit world Provide great performance without parallelProvide great performance without parallel Simultaneous 32 and 64 bit computingSimultaneous 32 and 64 bit computing More physical address 1 TB not limited to More physical address 1 TB not limited to

4GB4GB Applications can use up to 4GB instead of Applications can use up to 4GB instead of

2GB2GB Worry-Free on memoryWorry-Free on memory A lot less swapping to virtual memoryA lot less swapping to virtual memory A single architecture designed fit allA single architecture designed fit all

AMD Athlon 64 & 64 FXAMD Athlon 64 & 64 FX

Athlon 64 is 754-pin Athlon 64 FX is 940-pin

New ChangesNew Changes 1 MB L2 cache1 MB L2 cache Integrated memory controllerIntegrated memory controller HyperTransport channelHyperTransport channel Less power need Less power need New AMD CoreNew AMD Core Double the registersDouble the registers Integrated DDR Memory ControllerIntegrated DDR Memory Controller Enlarge Look-Aside Buffer (TLB)Enlarge Look-Aside Buffer (TLB) Extend pipeline from 10 to 12 stagesExtend pipeline from 10 to 12 stages

AMD 64 Processor AMD 64 Processor ArchitectureArchitecture

Integrated Memory Integrated Memory ControllerController

Provide sufficient low-latency memory bandwidth Provide sufficient low-latency memory bandwidth to processor coreto processor core

With integrated memory controller it changed With integrated memory controller it changed the way processors access main memorythe way processors access main memory

It greatly increase bandwidth and reduce It greatly increase bandwidth and reduce latencies thus speed up processlatencies thus speed up process

Run memory controller at processor speeds Run memory controller at processor speeds rather than FSB speedsrather than FSB speeds

Boosts performance for many applications with Boosts performance for many applications with intensive memory useintensive memory use

Available memory bandwidth up to 6.4GB/s with Available memory bandwidth up to 6.4GB/s with Opteron and FX and 3.2GB/s with AMD 64Opteron and FX and 3.2GB/s with AMD 64

AMD 64 CoreAMD 64 Core

Enables simultaneous 32 and 64 bit Enables simultaneous 32 and 64 bit computingcomputing

There are 3 main categories in AMD 64 There are 3 main categories in AMD 64 CoreCore

1. 32-bit applications under a 32-bit OS1. 32-bit applications under a 32-bit OS 2. 32-bit applications under a 64-bit OS2. 32-bit applications under a 64-bit OS 3. 64-bit applications under a 64-bit OS3. 64-bit applications under a 64-bit OS Great for migrationGreat for migration

HyperTransportHyperTransport

Increase overall system performance by Increase overall system performance by reducing I/O bottlenecks, increasing reducing I/O bottlenecks, increasing system bandwidth and reducing system system bandwidth and reducing system latencylatency

High-speed I/O communicationHigh-speed I/O communication Up to 6.4GB/s bandwidth per link, Up to 6.4GB/s bandwidth per link,

improve interconnection with system improve interconnection with system componentscomponents

Up to 3 HyperTransport link (only on Up to 3 HyperTransport link (only on Opteron)Opteron)

SSE/SSE2 RegistersSSE/SSE2 Registers

Double the number of registersDouble the number of registers Double SSE registers to improve Double SSE registers to improve

floating point calculationsfloating point calculations

Enlarge Look-Aside Enlarge Look-Aside Buffer (TLB)Buffer (TLB)

With enlarge look-aside buffer it reduce With enlarge look-aside buffer it reduce transmitting between system memory and transmitting between system memory and physical addressphysical address

PipelinePipeline

Extended the pipeline to 12 states Extended the pipeline to 12 states from 10 to increase the clock speedsfrom 10 to increase the clock speeds

Rework the predictionsRework the predictions

ProblemsProblems

AMD partner with Nvidia, but AMD partner with Nvidia, but NForce 3 chipset is not mature NForce 3 chipset is not mature

With nForce 3 low AGP performance With nForce 3 low AGP performance bug w/ HyperTransport channel bug w/ HyperTransport channel interfaceinterface

It comes up VIA is a better chipset It comes up VIA is a better chipset for AMD 64for AMD 64

AMD 64 FX-51AMD 64 FX-51

““Opteron” processor with FX labelOpteron” processor with FX label Slight change on the DDR400 support Slight change on the DDR400 support

(reduce validation)(reduce validation) Major difference from Athlon 64 is Major difference from Athlon 64 is

128-bit memory controller vs 64-bit 128-bit memory controller vs 64-bit Works with dual-channel Registered Works with dual-channel Registered

memorymemory Athlon 64 works with single-channel Athlon 64 works with single-channel

unbuffered DDR memoryunbuffered DDR memory

Final Word of FX-51Final Word of FX-51

Athlon 64 3400+ bring the death of Athlon 64 3400+ bring the death of the FX-51the FX-51

According to benchmarks from According to benchmarks from different areas Athlon 64 3400+ different areas Athlon 64 3400+ come very closely behind FX-51come very closely behind FX-51

But the price is half of FX-51But the price is half of FX-51 Or you can wait until FX-53 to come Or you can wait until FX-53 to come

outout

Watch Out!Watch Out!

AMD is talking about new Socket-AMD is talking about new Socket-939 around late this year939 around late this year

AMD Roadmap 754AMD Roadmap 754

AMD Roadmap 940AMD Roadmap 940

AMD Roadmap 939AMD Roadmap 939

Benchmarks - OpenGLBenchmarks - OpenGL

Benchmarks - Benchmarks -

Benchmarks - Benchmarks -

Benchmarks – Business Benchmarks – Business AppApp

Result SummaryResult Summary

AMD is good comes to AMD is good comes to business/gaming/2D work with business/gaming/2D work with perspective to price/performance perspective to price/performance ratioratio

Intel offers the best in encoding and Intel offers the best in encoding and 3D performance as well as 3D performance as well as multitaskingmultitasking

ConclusionConclusion

It is very hard to compare new processorsIt is very hard to compare new processors With AMD 64 lack of true 64-bit With AMD 64 lack of true 64-bit

applicationsapplications With Intel Prescott lack of SS3 enhance With Intel Prescott lack of SS3 enhance

applications and “out-to-day” video driver applications and “out-to-day” video driver and DirectXand DirectX

Hardware open the future door but not Hardware open the future door but not until software catch up, we won’t be able until software catch up, we won’t be able to truly experience the great to truly experience the great enhancement enhancement

SourcesSources

Intel Corp - Intel Corp - www.intel.comwww.intel.com AMD Corp – AMD Corp – www.amd.comwww.amd.com Toms’s Hardware – Toms’s Hardware –

www.tomshardware.comwww.tomshardware.com AnandTech – AnandTech – www.anandtech.comwww.anandtech.com ExtremeTech – ExtremeTech – www.extremetech.comwww.extremetech.com Tech Report – Tech Report – www.techreport.comwww.techreport.com Xbit Lab – Xbit Lab – www.xbitlabs.comwww.xbitlabs.com Opteronics – Opteronics – www.opteronics.comwww.opteronics.com