The MOSFETThe MOSFET

IntroductionIntroduction

Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs

Assets: High integration density and relatively simple manufacturing process

Consequently, it is possible to realize 107-8

transistors on an integrated circuit (IC) economically.

The MOS TransistorThe MOS Transistor

n+n+

p-substrate

Field-Oxide(SiO2)

p+ stopper

Polysilicon

Gate Oxide

DrainSource

Gate

Heavily doped n-type source and drain regions are implanted (diffused) into a lightly doped p-type substrate (body)

A thin layer (approx. 50 A0) of silicon dioxide (SiO2) is grownover the region between source and drain and is called thin orgate oxide

• Gate oxide is covered by a conductive material, often polycrystallinesilicon (polysilicon) and forms the gate of the transistor

• MOS transistors are insulated from each other by thick oxide(SiO2) and reverse biased p-n+ diode

• Adding p+ field implant (channel stop implant) makes sure aparasitic MOS transistor is not formed

MOS Transistor as a switch

Vin > VT : a conducting channel is formed between source anddrain and current flows

Vin <VT : the channel does not form and switch is said to beOpen

Vin >VT : current is a function of gate voltage

NMOS, PMOS, and CMOS TechnologyNMOS, PMOS, and CMOS Technology

In an NMOS transistor, current is carried by electrons (fromsource, through an n-type channel to the drainDifferent than diode where both holes and electrons contributeto the total currentTherefore, MOS transistor is also known as unipolar device

Another MOS device can be formed by having p+ source anddrain and n-substrate (PMOS)Current is carried by holes through a p-type channel

A technology that uses NMOS (PMOS) transistors only iscalled NMOS (PMOS) technologyIn NMOS or PMOS technologies, substrate is common and isconnected to +ve voltage, GND (NMOS) or VDD (PMOS)

In a complementary MOS (CMOS) technology, both PMOSand NMOS transistors are usedNMOS and PMOS devices are fabricated in isolated regionfrom each other (i.e., no common substrate for all devices)

MOS transistor is a 4 terminal device, if 4th terminal is notshown it is assumed to be connected to appropriate voltage

What is an MOS Transistor?What is an MOS Transistor?

VGS ≥ VT

RonS D

A Switch!

|VGS|

An MOS Transistor

When the voltage applied to the gate is larger than VT, a conducting channel is formed between the drain and source. In the presence of a voltage difference between D & S, electrical current flows between them. When the gate voltage is lower than the threshold, no channel exists, and the switch is considered open.

Very few parasitic effects, high integration density, relatively simple manufacturing process

Threshold Voltage: ConceptThreshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

DepletionRegion

n-channel

Initially: VGS=0, both pn-junctions have a 0V bias, and are considered off => extremely high resistance between drain and source.

Then: VGS>0, channel is formedIf now the gate voltage (VGS) is increased, gate and substrate form plates of a capacitor with oxide as dielectric

+ve gate voltage causes +ve charge on gate and -ve chargeon the substrate side. In substrate it occurs in two steps (i) depletion of mobileholes, (ii) accumulation of -ve charge (inversion)

At certain Vgs, potential at the interface reaches a criticalvalue, where surface inverts to n-type (start of strong inversion)

Further Vgs increase does not increase the depletion widthbut increases electrons in the inversion layer

Threshold Voltage

where

where

VT is +ve for NMOS and -ve for PMOS devices

]22[0 FSBFTT VVV Φ−−Φ−+= +γ

OX

Asi

CNqε

γ2

=

The Threshold Voltage The Threshold Voltage –– Body EffectBody Effect

- 2 . 5 - 2 - 1 . 5 - 1 - 0 . 5 00 . 4

0 . 4 5

0 . 5

0 . 5 5

0 . 6

0 . 6 5

0 . 7

0 . 7 5

0 . 8

0 . 8 5

0 . 9

VB S

(V )

VT (V

)

VT is the VGS value where strong inversion occurs.Note that VBS should never exceed 0.6V, otherwise the source-body becomes forward biased, which deteriorates the transistor’s operation

( )FSBFTT VVV Φ−+Φ−+= 220 γ

Function in manufacturing process (oxide thickness, fermi voltage, ion implants)

Transistor in LinearTransistor in Linear

n+n+

p-substrate

DS

G

B

VGS

xL

V(x) +–

VDS

ID

With VGS>VT, and a small VDS is applied, a current ID flows from the drain to source.Using simple analysis, a first order expression of ID is obtained.

When VGS >VT

Let at any point along the channel, the voltage is V(x) andgate to channel voltage at that point is VGS -V(x)

If the Vgs -V(x) >VT for all x, the induced channel charge perunit area at x (Cox is the capacitance per unit area of the gate oxide – εox/tox)

Current is given by

The electron velocity is given by

Therefore,

Integrating the equation over the length L yields

or

])([)( TgsOXi VxVVCxQ −−−=

WxQxI iD )()(υ−=

dxdVxE nnn µµυ =−= )(

dVVVVWCdxI TgsOXnD )( −−= µ

]2

)[('2

dsdsTgsnD

VVVVL

WKI −−=

]2

)[(2

dsdsTgsnD

VVVVKI −−=

For small VDS values, the MOS acts as a resistor

Transistor in SaturationTransistor in Saturation

n +n +

S

G

V G S

D

V D S > V G S - V T

V G S - V T+-

Pinch-offWith VGS>VT, and a larger VDS applied, the channel thickness gradually is reduced from sourceto drain until pinch-off occurs (channel depth depends on the voltage from G to channel). This occurs when pinch-off condition meets the drain region,

and current remains constant TDSGS VVV ≤−

( )22 TGSn

D VVL

WkI −=

K’n is known as the process trans-conductance parameter andequals

If the VGS is further increased, then at some x, Vgs - V(x) <VTand that point the channel disappears and transistor is said tobe pinched-off

Close to drain no channel exists, the pinched-off condition inthe vicinity of drain is VGS - VDS ≤ VT

Under these conditions, transistor is in the saturation regionIf a complete channel exists between source and drain, thentransistors is said to be in triode or linear region

Replacing Vds by Vgs -VT in the current equation we get,MOS current-voltage relationship in saturation region

ox

oxnOXnn

tCK εµµ =='

2)(2'

Tgsn

D VVL

WKI −=

This equation is not entirely correct, the position of pinch-offpoint and hence the effective channel length is a function ofVds, a more accurate equation is given as

where is an empirical constant parameter called channellength modulation factor

]1[)(2' 2

dsTgsn

D VVVL

WKI λ+−=

0.0 1.0 2.0 3.0 4.0 5.0VDS (V)

1

2

I D(m

A)

0.0 1.0 2.0 3.0VGS (V)

0.010

0.020

÷√I D

VT

SubthresholdCurrent

Triode Saturation

VGS = 5V

VGS = 3V

VGS = 4V

VGS = 2VVGS = 1V

(a) ID as a function of V DS (b) √ID as a function of V GS(for VDS = 5V).

Squ

are

Dep

ende

nce

VDS = VGS-VT

CurrentCurrent--Voltage RelationsVoltage RelationsA good A good olol’ transistor’ transistor

QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D(A

)VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

A model for manual analysisA model for manual analysis

The Transistor as a Switch (for hand analysis)The Transistor as a Switch (for hand analysis)

VGS ≥ VT

RonS D

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

Ron varies with time, nonlinear and depends on operating point of the MOS.

∫∫ −=

−== =

2

1

2

1)()(1)(1))((

12122...1

t

t D

DSt

tononttteq dt

tItV

ttdttR

tttRaverageR

))()((21

21 tRtRR ononeq +≈

VDD

VDS (VDD VDD/2)

ID

The Transistor as a SwitchThe Transistor as a Switch

0.5 1 1.5 2 2.50

1

2

3

4

5

6

7x 10

5

VDD

(V)

Req

(Ohm

)

• Resistance is inversely proportional to W/L ratio of the device. Doubling the transistor width cuts the resistance by half

• For VDD >> the resistance becomes virtually independent of VDD. Only a minor improvement is the resistance can be seen when rising VDD (attributed to the channel length modulation) – refer to the I-V equations in linear and saturation

• Once VDD approaches VT, the resistance dramatically increases.

Dynamic BehaviorDynamic Behavior

DS

G

B

CGDCGS

CSB CDBCGB

Dynamic BehaviorDynamic BehaviorMOS transistor is a unipolar (majority carrier) device, therefore,its dynamic response is determined by time to (dis)charge various capacitances

MOS capacitancesGate oxide capacitance (Cg): COX = per unit area,for a transistor of width, W and length, L, the Cg=Cox.W.L

From current equation it is apparent that Cox shouldbe high or gate oxide thickness should be small

Gate capacitance consists of several components

Source and drain diffusions extend below the thin oxide (lateraldiffusion) giving rise to overlap capacitance

The Gate CapacitanceThe Gate Capacitance

tox

n+ n+

Cross section

L

Gate oxide

xd xd

L d

Polysilicon gate

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W

❍ Source and drain diffusions extend below the thin oxide (lateral diffusion) giving rise to overlap capacitance❍ Xd is constant for a technology and this capacitance is linear and has a fixed value CgsO = CgdO = CoxXdW =

CoW

Average Gate CapacitanceAverage Gate Capacitance

Most important regions in digital design: saturation and cut-off

Gate to channel capacitance consists of Cgs, Cgd, and Cgb components. All these components are nonlinear and their value depends on operation region of the device.

Gate CapacitanceGate Capacitance

S D

G

CGC

S D

G

CGCS D

G

CGC

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

No channel exists, CGC appears between gate and body

Inversion layer is formed acting as conductor between source and drain. Cgb=0 (body electrode is shielded by channel). CGC divided evenly between source and drain

Channel is pinched off. Cgd~0 & Cgb~0

Gate CapacitanceGate Capacitance

WLCox

WLCox2

2WLCox3

CGC

CGCS

VDS /(VGS-VT)

CGCD

0 1

CGC

CGCS = CGCDCGC B

WLCox

WLCox2

VGS

Capacitance as a function of VGS(with VDS = 0)

Capacitance as a function of the degree of saturation

Diffusion CapacitanceDiffusion Capacitance