The High Voltage/High Power FET (HiVP)
description
Transcript of The High Voltage/High Power FET (HiVP)
The High Voltage/High Power The High Voltage/High Power FET (HiVP)FET (HiVP)
Amin K. Ezzeddine & Ho C. HuangAmin K. Ezzeddine & Ho C. Huang
Amcom Communications, Inc.Amcom Communications, Inc.
Clarksburg, Maryland, USAClarksburg, Maryland, USA
Presentation OutlinePresentation Outline
Why high voltage device?Why high voltage device?
Traditional high voltage approachesTraditional high voltage approaches
New New HiHigh gh VVoltage/ High oltage/ High PPower (ower (HiVPHiVP) ) configurationconfiguration
Implementation of a 14V & 28V GaAs Implementation of a 14V & 28V GaAs MMIC HiVPMMIC HiVP
ConclusionConclusion
Why High Voltage Device?Why High Voltage Device?
Some applications need high voltage:Some applications need high voltage:– Phase arraysPhase arrays– Satellite transmittersSatellite transmitters– No DC-to-DC converterNo DC-to-DC converter
Low breakdown voltage in semiconductors Low breakdown voltage in semiconductors materials such as: GaAs, AlGaAs, InP.materials such as: GaAs, AlGaAs, InP.
High powerHigh power
FET High Voltage ConfigurationsFET High Voltage Configurations
Traditional high voltage device Traditional high voltage device configurations:configurations:– DC series/ RF parallelDC series/ RF parallel– DC series/ multi-stageDC series/ multi-stage
New New HiHigh gh VVoltage/high oltage/high PPower device ower device ((HiVPHiVP))
DC Series/RF Parallel ConfigurationDC Series/RF Parallel Configuration
INPUT MATCHING
OUTPUT MATCHING
INPUT MATCHING
INPUT MATCHING
INPUT MATCHING
OUTPUT MATCHING
OUTPUT MATCHING
OUTPUT MATCHING
Pow
er D
ivid
er
Pow
er C
ombi
ner
Vgg
Vds
2Vds
3Vds
Vdd = 4Vds
RF IN RF OUT
Choke
Bypass
DC-Series/Cascaded-Stages DC-Series/Cascaded-Stages ConfigurationConfiguration
RF outOUTPUT MATCHING
INPUT MATCING
Vds
2Vds
INTERSTAGEMATCHING
Vgs
RF in
Choke
Choke
Bypass
New New HiHigh gh VVoltage/ High oltage/ High PPower (ower (HiVPHiVP))
Equivalent performance to a single device:Equivalent performance to a single device:- Efficiency- Efficiency- Power- Power
Higher gainHigher gain
High voltage biasHigh voltage bias
Scaled I-V characteristicsScaled I-V characteristics
Power combiner Power combiner
4-Cell 4-Cell HiHigh gh VVoltage/ High oltage/ High PPower (ower (HiVPHiVP))
OUTPUT MATCHING
INPUT MATCHING
Vgs
Vd3=3Vds
Vdd = 4Vds
RF IN
RF OUT
Vd2=2Vds
Vd1=Vds
FET1 (W/4)
FET2 (W/4)
FET3 (W/4)
FET4 (W/4)
C1
C2
C3
R4
R3
R2
R1
Vg4=3Vds+ Vgs
Vg3=2Vds+ Vgs
Vg2=Vds+ Vgs
Vg1=Vgs
I-V Characteristics of a 4-Cell (4 x 3mm) I-V Characteristics of a 4-Cell (4 x 3mm) HiVP DeviceHiVP Device
AM030MH4-BI (002)
0
0.2
0.4
0.6
0.8
0 10 20 30 40
Vdd (V)
Cu
rre
nt
(A)
-3V
-2.5V
-2V
-1.5V
-1V
-0.5V
0V
4-Cells HiVP Voltage Waveforms4-Cells HiVP Voltage Waveforms
Vin
Vd3=3Vm
Vdd = 4Vm
Vd2=2Vm
Vd1=Vm
C1
C2
C3
R4
R3
R2
R1-1.5
-1
-0.5
0
0.5
1
1.5
0 1 2 3 4 5 6 7
-1.5
-1
-0.5
0
0.5
1
1.5
0 1 2 3 4 5 6 7
-1.5
-1
-0.5
0
0.5
1
1.5
0 1 2 3 4 5 6 7
-1.5
-1
-0.5
0
0.5
1
1.5
0 1 2 3 4 5 6 7
-1.5
-1
-0.5
0
0.5
1
1.5
0 1 2 3 4 5 6 7
Zopt
Impedance Optimization of Impedance Optimization of Common Gate FETCommon Gate FET
Z Z source, Nsource, N 1/g 1/gmm (C (Cgsgs+ C + C NN) / C) / CN N
ggmm is FET transconductance is FET transconductanceCCgsgs is FET gate-to-source capacitance is FET gate-to-source capacitance
ZZopt, N+1opt, N+1
DrainSource
CCN+1N+1
Gate
DrainSource
CCNN
ZZsource, Nsource, N ZZopt, N opt, N = Z source, N+1
Gate
(N+1)th
FETNth
FET
HiVP Configuration FeaturesHiVP Configuration FeaturesHigh voltage bias: VHigh voltage bias: Vdddd = V = Vdsds x N x N
Lower Current by 1/N factor compared to Lower Current by 1/N factor compared to regular FET with equivalent peripheryregular FET with equivalent periphery
Higher optimum output impedance by NHigher optimum output impedance by N22 factor factor
Higher input impedanceHigher input impedance
Higher gain by factor of NHigher gain by factor of N
Broadband matchingBroadband matching
Simple & compact configurationSimple & compact configuration
Concept applicable to LDMOS and MOSFET Concept applicable to LDMOS and MOSFET to achieve very high powerto achieve very high power
Power & IP3 for 14V Hybrid HiVP at 1GHzPower & IP3 for 14V Hybrid HiVP at 1GHz
0
5
10
15
20
25
30
35
40
0 5 10 15 20 25 30
Pin (dBm)
Po
ut
(dB
m)
& G
ain
(d
B)
0
5
10
15
20
25
30
35
40
Eff
icie
ncy
(%
)
Pout
Gain
Efficiency
0
10
20
30
40
50
0 5 10 15 20
Pin (dBm)
IP3
& P
ou
t (d
Bm
)
IP3
Pout P1dB =35dBmEfficiency = 25%IP3 = 45dBm
@ 1.0GHz
14V/2-Cells HiVP MMIC ( 2 x 2mm device)14V/2-Cells HiVP MMIC ( 2 x 2mm device)
-20
-10
0
10
20
30
0 2 4 6 8 10Frequency (GHz)
Ga
in &
Inp
ut/
Ou
tpu
t R
etu
rn L
os
s
(dB
)
Gain
S22
S11
Chip Layout
S-Parameters
P1dB =31dBmEfficiency = 35%IP3 = 46dBm
@ 3.5GHz
Pout & Efficiency of 2 x 2mm HiVP at 3.5GHz Pout & Efficiency of 2 x 2mm HiVP at 3.5GHz
10
15
20
25
30
35
0 5 10 15 20
Pin (dBm)
Po
ut
(dB
m)
& G
ain
(d
B)
0
10
20
30
40
50
Eff
icie
ncy
(%
)
Gain
Efficiency
Pout
IP3 & IP5 of 2 x 2mm HiVP at 3.5GHz IP3 & IP5 of 2 x 2mm HiVP at 3.5GHz
0
10
20
30
40
50
60
-5 0 5 10 15
Pin (dBm)
Po
ut
& IP
3 (
dB
m)
IP3
IP5
Pout
28V/4-Cells HiVP MMIC (4 x 1mm device28V/4-Cells HiVP MMIC (4 x 1mm device))
-15
-10
-5
0
5
10
15
20
25
0 1 2 3 4 5Frequency (GHz)
Ga
in &
Inp
ut/O
utp
ut R
etu
rn L
oss
(d
B)
Gain
S22
S11
Chip LayoutS-Parameters
P1dB =31dBmEfficiency = 32%IP3 = 45dBm
@ 1GHz
28V/4-Cells HiVP in Parallel (4 x 3mm device)28V/4-Cells HiVP in Parallel (4 x 3mm device)
Package Device4 x 3mm ChipP1dB =35dBm
Efficiency = 27%IP3 = 50dBm
@ 2.15GHz
Power & Efficiency of 4 x 3mm HiVP at 2.15GHz Power & Efficiency of 4 x 3mm HiVP at 2.15GHz
0
5
10
15
20
25
30
35
40
0 5 10 15 20 25
Pin (dBm)
Po
ut
(dB
m)
& G
ain
(d
B)
0
5
10
15
20
25
30
35
40
Eff
icie
ncy
(%
)
Pout
Gain
Efficiency
IP3 of a 4 x 3mm HiVP at 2.15GHz IP3 of a 4 x 3mm HiVP at 2.15GHz
0
10
20
30
40
50
60
0 5 10 15 20
Pin (dBm)
IP3
& P
ou
t (d
Bm
)
IP3
Pout
IP3 at 2.15GHz for 4 x 3mm HiVP versus 12 mm FETIP3 at 2.15GHz for 4 x 3mm HiVP versus 12 mm FET
35
40
45
50
55
15 20 25 30 35
Pout (dBm)
IP3
4 x 3mm HiVP
12mm FET
24V/4-Cell High Power pHemt HiVP 24V/4-Cell High Power pHemt HiVP (4 x24mm)(4 x24mm)
4 x 6mm Chip4 x 24mm Chip P1dB =43dBmEfficiency = 30%IP3 = 57dBm
@ 1.5GHz
Power & Efficiency of 4 x 24mm pHemt HiVP at 1.5GHzPower & Efficiency of 4 x 24mm pHemt HiVP at 1.5GHz
15
20
25
30
35
40
45
10 15 20 25 30Pin (dBm)
Po
ut (
dB
m)
& G
ain
(d
B)
0
10
20
30
40
50
60
Effi
cie
ncy
(%
)
Pout
Efficiency
Gain
IP3 of 4 x 24mm pHEMT HiVP at 1.5GHzIP3 of 4 x 24mm pHEMT HiVP at 1.5GHz
0
10
20
30
40
50
60
5 6 7 8 9 10 11 12 13 14 15Pin (dBm)
Pou
t &
IP3
(dB
m)
Pout
IP3
ConclusionConclusion
A simple DC series/RF series device (HiVP) for A simple DC series/RF series device (HiVP) for high voltage operation is presentedhigh voltage operation is presented
This simple new device behaves as an RF This simple new device behaves as an RF combinercombiner
New device has good linearity and broadband New device has good linearity and broadband performanceperformance
HiVP concept could be applied to GaN and HiVP concept could be applied to GaN and Silicon FETs to push the power to kW rangesSilicon FETs to push the power to kW ranges