The HCS12 Microcontroller Han-Way Huang Minnesota State...

The HCS12/MC9S12 Microcontroller

Chapter 6: Interrupts and Resets

The HCS12 Microcontroller

Han-Way Huang

Minnesota State University MankatoMinnesota State University, Mankato

September 2009

H. Huang Transparency No.6‐1Copyright © 2010 Delmar Cengage Learning


Fundamental Concepts of Interrupts

What is an interrupt?

A special event that requires the CPU to stop normal program execution andf i l t d t th tperform some service related to the event.

Examples of interrupts include I/O completion, timer time-out, illegal opcodes, arithmetic overflow, divide-by-0, etc.

F nctions of Interr ptsFunctions of Interrupts

Coordinating I/O activities and preventing CPU from being tied upProviding a graceful way to exit from errorsReminding the CPU to perform routine tasksReminding the CPU to perform routine tasks

Interrupt Maskability

Interrupts that can be ignored by the CPU are called maskable interruptsInterrupts that can be ignored by the CPU are called maskable interrupts. A maskable interrupt must be enabled before it can interrupt the CPU. An interrupt is enabled by setting an enable flag.Interrupts that can’t be ignored by the CPU are called non-maskable interrupts.



Interrupt priorityInterrupt priorityAllow multiple pending interrupt requestsResolve the order of service for multiple pending interrupts

I S iInterrupt Service

CPU executes a program called the interrupt service routine.A complete interrupt service cycle includesp p y

1. Saving the program counter value in the stack2. Saving the CPU status (including the CPU status register and some other

i t ) i th t kregisters) in the stack3. Identifying the cause of interrupt4. Resolving the starting address of the corresponding interrupt service routine5. Executing the interrupt service routineg p6. Restoring the CPU status and the program counter from the stack7. Restarting the interrupted program



Interrupt Vector

Starting address of the interrupt service routine

Interrupt Vector Tablep

A table where all interrupt vectors are stored.

Methods of Determining Interrupt VectorsMethods of Determining Interrupt Vectors

1. Predefined locations (Microchip PIC18, 8051 variants)2. Fetching the vector from a predefined memory location (HCS12, Atmel avr)3. Executing an interrupt acknowledge cycle to fetch a vector number in order to3. ecut g a te upt ac ow edge cyc e to etc a vecto numbe o de to

locate the interrupt vector (68000 and x86 families)

Steps of Interrupt Programming

Step 1. Initializing the interrupt vector tableStep 2. Writing the interrupt service routineStep 3. Enabling the interrupt



The Overhead of Interrupts

Saving and restoring of CPU status and other registers. (HCS12 needs to save all

CPU registers).

Execution time of instructions of the interrupt service routine.

The execution of the RTI instruction that will restore all the CPU registers.The execution of the RTI instruction that will restore all the CPU registers.



R tResets

The initial values of some CPU registers, flip-flops, and the control registers in I/O

interface chips must be established in order for the computer to function properly.

The reset mechanism establishes these initial conditions for the computer system.

There are at least two types of resets: power-on reset and manual reset.

The power-on reset establishes the initial values of registers and I/O control registers.

The manual reset without power-down allows the computer to get out of most error

conditions if hardware doesn’t failconditions if hardware doesn t fail.

A reset is non-maskable.



HCS12 ExceptionsCS cep o s

Maskable interrupts: including IRQ pin and all peripheral function interrupts.Nonmaskable interrupts: including XIRQ pin, SWI interrupt, and unimplemented opcodetraptrap.Resets: including the power-on reset, reset pin manual reset, the COP reset (computeroperate properly), and clock monitor reset.

Maskable InterruptsMaskable Interrupts

Different HCS12 members implement different number and types of peripheral functions,and hence may have different number of maskable interrupts.O f th k bl i t t b i d t th hi h t i it th k blOne of the maskable interrupts can be raised to the highest priority among the maskableinterrupt group and receive quicker service. This is achieved by programming theHPRIO register.



The priority and vector addresses of all HCS12 exceptions are listed in Table 6 1The priority and vector addresses of all HCS12 exceptions are listed in Table 6.1.

To raise a maskable interrupt source to the highest priority, write the low byte of the

vector address of this interrupt to the HPRIO register.

In Table 6.1, exceptions that have higher vector addresses are at higher priorities.

Not all the exceptions are available in all HCS12 members.

IRQ Pin Interrupt

The only external maskable interrupt for the HCS12.

IRQ interrupt can be edge-triggered or level-triggered.IRQ interrupt can be edge triggered or level triggered.

IRQ interrupt has a local enable mask in the IRQCR register.

The IRQ interrupt is configured by programming the IRQCR register.

Th f h IRQCR i h i Fi 6 2The contents of the IRQCR register are shown in Figure 6.2.



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Making IRQ Level-Sensitiveg Q

Pros:Multiple interrupt sources can be tied to this pin.

Cons:Need to make sure that the IRQ signal has become inactive before the IRQ service routine is complete if there is only one interrupt request pending.

Making IRQ Edge-SensitiveMaking IRQ Edge Sensitive

Pros:No need to control the duration of the IRQ pulse.

Cons:Cons:Not suitable for noisy environment because every falling edge caused by noise will be recognized as an interrupt.

When does the MCU recognize interrupt requests?When does the MCU recognize interrupt requests?

The MCU recognizes the interrupt request when it completes the execution of the current instruction unless the current instruction is a fuzzy logic instruction. For fuzzy logic i t ti th HCS12 i th i t t i di t l


instructions, the HCS12 recognizes the interrupt immediately.


Th St k O d E t f I t tThe Stack Order on Entry of an Interrupt

The HCS12 saves all CPU registers on an interrupt.The order of saving CPU registers is shown in Figure 6.3.

The RTI InstructionRTI is used to terminate interrupt service routines.RTI will restore CPU registers from the stack.The HCS12 will continue to execute the interrupted program unless there is anotherpending interrupt.



N k bl I t tNon-maskable Interrupts

XIRQ pin, SWI instruction, & unimplemented instruction opcode trap.

XIRQ Pin Interrupt

XIRQ interrupt is disabled during a system reset and upon entering the service routine of another XIRQ interrupt.

After minimal system initialization, software can clear the X bit of the CCR register to e ble the ( i the andcc #$BF i t ti ) XIRQ i te t S ft e t e et the Xenable the (using the andcc #$BF instruction) XIRQ interrupt. Software cannot reset the X bit once it has been set.

When a non-maskable interrupt is recognized, both the X and I bits are set after CPU registers are saved.g

The execution of an RTI instruction at the end of the XIRQ service routine will restore the X and I bits to the pre-interrupt request state.

Unimplemented Opcode Trapp p p

There are 202 unimplemented opcode on page 2 (16-bit opcode).

These unimplemented opcode share the same vector $FFF8:$FFF9.



S ft I t t I t ti (SWI)Software Interrupt Instruction (SWI)

Execution of the SWI instruction causes an interrupt without an interrupt request signal.

The SWI instruction is commonly used in the debug monitor to implement breakpoints d t t f t l f t th d b itand to transfer control from a user program to the debug monitor.

A breakpoint in a user program is a memory location where we want program execution to be stopped and information about instruction execution (in the form of register contents) to be displayed. ) p y

Interrupts in D-Bug12 EVB ModeOn-chip flash memory locations are not available for user to stored interrupt vectors.D-Bug12 monitor provides SRAM-based interrupt vector table.g p pThe SRAM-based table (in Table 6.3) starts at $3E00 and has 64 entries.The interrupt SCI0 has been used by the monitor and is not available to the user.Mnemonic names are defined for users to store their interrupt vectors in the table. Both the hcs12.inc and the vectors12.h (for C language) have the definitions for these entries.



Setting Up the Interrupt Vector

Assume that the label (or name) of the IRQ interrupt service routine is irqISR.

In assembly language,

For miniIDE (D-Bug12 monitor), the interrupt vector must be stored in SRAM

movw #irqISR,UserIRQ ; store the vector at the designated address

For CodeWarrior (the serial monitor or BDM debug adapter), the interrupt vector must bestored at the default address (for example, IRQ interrupt at $FFF2).

org $FFF2 ; set up interrupt vector for IRQ under CodeWarriordc.w irqISR ; “



In C langaugeg gCodeWarrior Template for Interrupt Service RoutineInterrupt void ISR_name (void)

… // statements to service the interrupt

There are two parts in setting up the interrupt service routine:1. Declare the interrupt service to be external2. Insert the name of interrupt service routine into the appropriate place of the

interrupt vector table

For example, IRQ interrupt vector can be setup as follows:



t l id i ISR( id) // IRQ i i d fi d t id thi filexternal void near irqISR(void); // IRQ pin is defined outside this file#pragma CODE_SEG_NEAR_SEG NON_BANKED // interrupt section for this module_interrupt void UnimplementedISR(void)

f ( ) // d thi b t t f i t tfor(;;); // do nothing, but return from interrupt

#pragma CODE_SEG DEFAULTt edef id (* e tI F )( id);typedef void (*near tIsrFunc)(void);const tIsrFunc _vect[] @0xFF80 = // interrupt vector table starts from this line// interrupt vector table

UnimplementedISR,……irqISR, // IRQ interrupt vector (at the address 0xFFF2)……

;The entry UnimplementedISR is provided as a catch-all handler for all unintended interrupts.



If the user is not concerned about unintended interrupts, the interrupt vector table canp pBe reduced to

const tIsrFunc _vect[] @0xFFF2 = // 0xFFF2 is the address to store IRQ interupt vectorirqISRq

;

Interrupt Handling in ImageCraft ICC12

The interrupt service routine for IRQ is defined as follows:#pragma interrupt_handler irqISRvoid irqISR (void)]

…The interrupt vector can be setup using the D-Bug12 monitor function SetUserVector.

asm(“ldd #_irqISR”); // push IRQ interrupt vector into stackasm(“pshd”); // “asm(“ldd #56”); // place IRQ vector number of IRQ in Dasm(“ldx $EEA4”); // place SetUserVector function indirect call address in Xasm(“jsr 0,X”); // jump to SetUserVector function



Interrupt Programming in EGNU IDEp g g1. Use the interrupt attribute of the GCC compiler. Add the following statements at

the beginning of the program: #define INTERRUPT __attribute__((interrupt))

2. Apply the interrupt attribute to the interrupt service routine.void INTERRUPT irqISR(void);

3. Include the header file vectors12.h to your program :y p g#include “c:\egnu\include\vectors12.h”

4. Store the name of the IRQ service routine at the designated address:UserIRQ = (unsigned short)&IRQISR;Q ( g ) Q ;

5. Write the actual IRQ service routine.



Example 6.1 The IRQ pin of the HCS12DP256 is connected to a 1-Hz digitalExample 6.1 The IRQ pin of the HCS12DP256 is connected to a 1 Hz digital waveform and port B is connected to eight LEDs. Write a program to configure port B foroutput and enable the IRQ interrupt and also write the service routine for the IRQ interrupt. The service routine for the IRQ interrupt simply increments a counter and outputs it to port B. The assembly language version is to be assembled miniIDE whereas the C languageport B. The assembly language version is to be assembled miniIDE whereas the C language version of the program is to be compiled by GNU C compiler.Solution:The assembly and C language versions of the program are in the following two pages.pages.



#include "c:\miniide\hcs12.inc"org $1000

count ds.b 1 ; reserve one byte for countorg $1500lds #$1500 ; set up the stack pointermovw #IRQISR,UserIRQ ; set up interrupt vector in SRAMclr countmovb #$FF,DDRB ; configure port B for outputbset DDRJ,$02 ; configure PJ1 pin for output (required in Dragon12)bclr PTJ,$02 ; enable LEDs to light (required in Dragon12)movb count,PTB ; display the count value on LEDsmovb #$C0,IRQCR ; enable IRQ pin interrupt, select edge-triggeringcli ; "

forever nopbra forever ; wait for IRQ pin interrupt

; ****************************************************************************; This is the IRQ service routine.; ****************************************************************************IRQISRinc count ; increment count

movb count,PTB ; and display count on LEDsrti


end


#include "c:\egnu\include\hcs12.h"#i l d " \ \i l d \ t 12 h"#include "c:\egnu\include\vectors12.h"#define INTERRUPT __attribute__((interrupt))void INTERRUPT IRQISR(void);unsigned char cnt;

void main(void)

UserIRQ = (unsigned short)&IRQISR;DDRB 0 FFDDRB = 0xFF;cnt = 0;DDRJ |= BIT1; // configure PJ1 pin for outputPTJ &= ~BIT1; // enable LEDs to lightIRQCR 0 C0; // enable IRQ interr pt on falling edgeIRQCR = 0xC0; // enable IRQ interrupt on falling edgeasm("cli"); // enable interrupt globallywhile(1); // wait for interrupt forever

void INTERRUPT IRQISR(void)void INTERRUPT IRQISR(void)

cnt++;PTB = cnt;



Clock and Reset Generation Block (CRG)Clock and Reset Generation Block (CRG)

CRG generates the clock signals required by the HCS12 instruction execution and all

peripheral operations.p p p

The clock signal has the form of square waveform.

Crystal oscillators are often used to generate clock signals.

The crystal oscillator output is a sinusoidal wave and must be converted to square waveThe crystal oscillator output is a sinusoidal wave and must be converted to square wave

before it can be used.

The HCS12 has internal circuit to do this square up operation.

The CRG block also has a PLL circuit that can multiply the frequency of the incoming

clock signal.

The block diagram is shown in Figure 6.4.

The CRG can also accept oscillator output (square waveform) directly.

The XCLKS signal must be tied low (for MC9S12DP256B) in order to use external

clock signal


clock signal.


Choice of Clock SourceChoice of Clock Source

The user can choose between using the external crystal or oscillator to produce the clocksignal.The external crystal is connected between the EXTAL and XTAL pins and needs anThe external crystal is connected between the EXTAL and XTAL pins and needs anon-chip oscillator circuitry to square it up.The external clock source provided by the oscillator is connected to the EXTAL pin andhave a 2.5V peak to peak magnitude for D family.The XCLKS signal must be grounded to select the external clock signalThe XCLKS signal must be grounded to select the external clock signal.The output from the OSC module in Figure 6.4 may bypass or go through the PLL circuit.The PLL circuit has the capability to multiply incoming signal frequency and stabilize its output signal frequency.Either the OSCCLK or the PLLCLK can be chosen as the SYSCLK which will beEither the OSCCLK or the PLLCLK can be chosen as the SYSCLK which will bedivided by 2 to derive the bus clock to control the instruction execution and peripheraloperation. The HCS12 clock generation circuit is shown in Figure 6.15.



Phase Locked Loop

The frequency of the PLLCLK is controlled by registers SYNR and REFDY using thefollowing equation:

(SYNR + 1)PLLCLK = 2 × OSCCLK × ------------------- (6.1)

(REFDV + 1)

reset:

0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0

0 0 0 0 0 0 0 0

Figure 6.8 The CRG synthesizer register (SYNR)

01234567

reset:

0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0

0 0 0 0 0 0 0 0

Figure 6 9 The CRG reference divider register (REFDV)

7 6 5 4 3 2 1 0

Figure 6.9 The CRG reference divider register (REFDV)

Selection of PLL for clock generation is controlled by the CRGSEL register.



PLL circuit is also controlled by the PLLCTL register.



Example 6.2 There is a system that derives its bus clock from the PLL circuit and an crystal oscillator of 8 MHz is selected. The desired bus clock is 24 MHz. Write an assembly routine and a C function to perform the configuration.Solution:

The SYSCLK frequency is 48 MHz and the frequency of OSCCLK is 8 MHz.

48 MHz = 2 × 8 MHz × [SYNR + 1] /[REFDV + 1]

One solution is to set SYNR and REFDV to 2 and 0, respectively.SetClk8 movb #02,SYNR

movb #0,REFDVmovb #$60,PLLCTL ; disable clock monitor, enable PLLbrclr CRGFLG,LOCK,* ; wait until PLL locks into the target frequency

$movb #$80,CLKSEL ; use PLL to generate system clockrts

void SetClk8(void)

// d l l kSYNR = 0x02; // use PLL and 8-MHz crystal to generate 24-MHz E clockREFDV= 0; // “PLLCTL= 0x60; // enable PLLwhile(!(CRGFLG & 0x08); // wait until PLL locks into the target frequencyCLKSEL | PLLSEL // l k d i d f PLL


CLKSEL |= PLLSEL; // clock derived from PLL


Clock MonitorClock Monitor

The clock monitor is based on an RC circuit.If no OSCCLK edges are detected within the RC time delay, the clock monitor mayreset the MCU if the CME bit in the PLLCTL register is set to 1.reset the MCU if the CME bit in the PLLCTL register is set to 1.The SCME bit of the PLLCTL register must be cleared to 0 for clock monitor to work.

Real Time InterruptReal Time Interrupt

- Main function is to generate periodic interrupt to the MCU.- The RTI interrupt is enabled by the CRGINT register (shown in Figure 6.11)- The interrupt interval of RTI is selected by the RTICTL register (shown in Figure 6.16).e te upt te va o s se ected by t e C eg ste (s ow gu e 6. 6).- The actual available interrupt periods for RTI are listed in Table 6.4.



Table 6.4 RTI interrupt period (in units of OSCCLK cycle)

RTR[3:0] RTR[6:4]000( ff)

001(210)

010(211)

011(212)

100(213)

101(214)

110(215)

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4×210

211

2×211

3×211

4×211

212

2×212

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4×212

213

2×213

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4×213

214

2×214

3×214

4×214

215

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4×215

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8×211

11

4×25×212

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7×212

8×212

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4×25×213

6×213

7×213

8×213

13

4×25×214

6×214

7×214

8×214

14

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6×215

7×215

8×215

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4×25×216

6×216

7×216

8×216

161000 (÷9)1001 (÷10)1010 (÷11)1011 (÷12)1100 (÷13)

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9×210

10×210

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12×210

13×210

9×211

10×211

11×211

12×211

13×211

9×212

10×212

11×212

12×212

13×212

9×213

10×213

11×213

12×213

13×213

9×214

10×214

11×214

12×214

13×214

9×215

10×215

11×215

12×215

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9×216

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12×216

13×216( )1101 (÷14)1110 (÷15)1111 (÷16)

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14×210

15×210

16×210

14×211

15×211

16×211

14×212

15×212

16×212

14×213

15×213

16×213

14×214

15×214

16×214

14×215

15×215

16×215

14×216

15×216

16×216



Example 6.5 Write a C program to use the RTI interrupt to time-multiplex four sevenp p g p psegment displays using the circuit shown in Figure 4.18 and shift the seven-segment display pattern as described in Example 5.9. Turn on one display at a time and light each display for about 1 ms then switch to the next display. Use display #0 to display #3. Use CodeWarrior and a demo board programmed with serial monitor to implement the circuit. p g pSolution:Arangememt

Place the segment patterns in one array segPat[].Place digit select values in the array digit[].g y g []Use the variable seq as index to the segment array that identifies the first digit of the current sequence.Use the variable ix as an index to the digits within one sequence (ix = 0..3).Use the variable count to specify the repetition count of a sequencep y p q



#include "c:\cwHCS12\include\hcs12.h"#include "c:\cwHCS12\include\SetClk.h"int seq; // start index to segPat[] of a sequence of digits (0 to 9)int ix; // index of digits of a sequence (0 to 3)int count; // repetition count of a sequencechar segPat[13] = 0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x67,0x3F,0x06,

0x5B,0x4F;char digit[4] = 0xFE,0xFD,0xFB,0xF7;

void main (void) seq = 0; // initialize the start index to segPat[] for the display sequenceix = 0; // initialize the index of a new sequence count = 400; // initialize the RTI interrupt count of a sequenceSetClk8(); // set E clock to 24 MHz from an 8-MHz crystal oscillatorRTICTL = 0x40; // RTI interrupt interval set to 2**10 OSCCLK cyclesDDRB = 0xFF; // configure Port B for outputDDRP = 0xFF; // configure Port P for outputCRGINT|= RTIE; // enable RTI interruptasm("CLI"); // enable interrupt globallywhile(1);



// RTI interrupt service routineinterrupt void rtiISR(void)

CRGFLG = 0x80; // clear RTIF bitPTB = segPat[seq+ix]; // send out digit segment patternPTP = digit[ix]; // turn on the displayix++; // increment the index to digits of a sequenceif (ix == 4) // make sure the index to digits of a sequence is from 0 to 3

ix = 0; // “count--;if(count == 0) // is time for the current sequence expired?

seq++; // change to a new sequence of digitscount = 400; // reset repetition count

if(seq == 10) // is this the last sequence?

seq = 0; // reset start index of a sequence

This project also contains the vectors.c file.



extern void near rtiISR(void);#pragma CODE_SEG __NEAR_SEG NON_BANKED#pragma CODE_SEG DEFAULT // Change code section to DEFAULT.

typedef void (*near tIsrFunc)(void);const tIsrFunc _vect[] @0xFFF0 =

rtiISR;;

Example 6.6 Modify the C program in Example 6.5 so that it can be compiled using the ICC12 C compiler and run in a demo board programmed with the D-Bug12 monitor. Solution:So u o :#include "c:\cwHCS12\include\hcs12.h"#include "c:\cwHCS12\include\SetClk.h"void rtiISR(void);int seq,ix,count;q, , ;char segPat[13] = 0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x67,0x3F,0x06,0x5B,0x4F;char digit[4] = 0xFE,0xFD,0xFB,0xF7;



void main (void) asm("ldd #_rtiISR"); // set up RTI interrupt vector by calling SetUserVectorasm("pshd"); // function using in-line assembly instructionsasm("ldd #56"); // “asm("ldx $EEA4"); // “asm("jsr 0,x"); // “seq = 0;ix = 0; count = 400;SetClk8();RTICTL = 0x40; // RTI interrupt interval set to 2**10 OSCCLK cyclesDDRB = 0xFF; // configure Port B for outputDDRP = 0xFF; // configure Port P for outputCRGINT |= RTIE; // enable RTI interruptasm("CLI"); // enable interrupt globallywhile(1);



#pragma interrupt_handler rtiISRvoid rtiISR(void)

CRGFLG = 0x80; // clear RTIF bitPTB = segPat[seq+ix]; // output the segment patternPTB segPat[seq ix]; // output the segment patternPTP = digit[ix]; // output digit select valueix++; // increment digit index within a sequenceif (ix == 4)

ix = 0;;count‐‐; // decrement repetition countif(count == 0) // if repetition count is 0, then change to the next sequence

seq++;count = 400;;

if(seq == 10) // Reach the last sequence?

seq = 0;



Computer Operating Properly (COP) CircuitComputer Operating Properly (COP) Circuit

Allow the user to determine whether the application software operates properly.The COP is a timer circuit that will time out if it is not rearmed within a presettime limittime limit.The COP will reset the MCU when it times out and the user would know if the softwareoperate properly.The application software would include an instruction sequence to prevent the COPfrom timing outfrom timing out.To prevent the COP from timing out, write $55 and then $AA into the ARMCOP register.The time out period of the COP is controlled by the COPCTL register. The contents of the COPCTL are shown in Figure 6.17.



Lower Power Mode

It is desirable to minimize power consumption when the MCU is not busy performinguseful operations.The execution of the WAI instruction places the HCS12 MCU in wait mode andreduces power consumption significantly.In wait mode, CPU clocks are stopped but clock signals for peripheral functions continue to run.The CPU leaves the wait mode when one of more of the following events occur:

(1) Maskable interrupts that are not disabled(2) Non-maskable interrupts(3) Resets

Reset is not the best way to get out of wait state because it will restart everything andtakes longer time to resume normal operation.



Stop ModeStop Mode

Stop mode is entered when the MCU executes the STOP instruction. When this instructionis executed, the MCU enters standby mode.The STOP instruction has no effect if the S flag of the CCR register is 1.The STOP instruction has no effect if the S flag of the CCR register is 1.In stop mode, all clock signals in the MCU are stopped. Asserting the RESET, IRQ, or XIRQ signal ends the standby mode.

ResetsResets

There are four sources of reset:

(a) Power-on (POR) and low-voltage detector (LVD) reset(a) owe o ( O ) a d ow vo tage detecto ( V ) eset(b) RESET pin(c) COP reset(d) Clock monitor reset



Power‐On ResetPower On ResetThe HCS12 has a circuit to assert reset when VDD supply to the MCU has reacheda certain level.The CRG module performs a quality check on the incoming clock signal as soon asa power‐on reset is triggered.a power on reset is triggered.The CRG module will release the reset signal only when the clock check is successful.

External ResetThe RESET pin allows the user to reset the MCU.pThe MCU can differentiate the external and internal reset signals.When the power supply drops to certain level, it may corrupt the EEPROM. It is desirableto have a circuit that can detect this situation and asserts a reset to the MCU.The Motorola MC34064 is a chip that can detect low voltage on power supply and p g p pp yreset the CPU.An external reset circuit incorporating an MC34064 is shown in Figure 6.18.



V V

IN

VDD

MC34064

VDD

4.7 ΚΩ

1 manual reset2µF

GND

RESETMC34064

34.7 ΚΩ

4.7 ΚΩ

To RESETof HCS12

Figure 6.18 A typical external reset circuit



HCS12 Operation Modes

The HCS12 can operate in eight different operation modes (shown in Table 6.5).The states of MODC, MODB, and MODA pins are latched to determine the MCUoperation modes.Expanded modes allow the user to access external memory where single chip modesdo not.In expanded modes, Port A and B become the time-multiplexed address and data port.

Table 6.5 HCS12 Mode Selection

BKGD MODB MODA Mode

0 0 0 Special single chip

Port A

general-purpose I/O

Port B

general-purpose I/O000111

011001

101010

p g pSpecial expanded narrow

Special peripheralSpecial expanded wide

Normal single chipNormal expanded narrow

Reserved (forced to peripheral)

g p pADDR[15:8]DATA[7:0]ADDR/DATAADDR/DATAGeneral-purpose I/OADDR[15:8]DATA[7:0]--

g p pADDR[7:0]ADDR/DATAADDR/DATAGeneral-purpose I/OADDR[7:0]--1

111

01

Reserved (forced to peripheral)Normal expanded wide ADDR/DATA ADDR/DATA


The HCS12 Microcontroller Han-Way Huang Minnesota State...

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