The five basic gates (AND, OR, INVERTER, NAND, NOR) arecmsc.ac.in/phy78.pdf · memory or storage...
Transcript of The five basic gates (AND, OR, INVERTER, NAND, NOR) arecmsc.ac.in/phy78.pdf · memory or storage...
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The five basic gates (AND, OR, INVERTER, NAND, NOR) are
classified as combinational logic circuits. A combinational logic circuit is
a circuit without feedback. The output of such a circuit depends only on
its external inputs and so have no memory and can operate as fast as the
devices of which they are made.
As sequential logic circuit is a logic circuit with feedback. Its
output depends on the external inputs as well as on the present state of
its outputs, which are feedback to the inputs and so have memory. For
example, in a flip flop (which has two stable states 1 or 0, i.e., output is al
or a0) if output is al then it will continue to be so until next input is
applied. Thus circuit retains the effects of applied input till the next input
is applied. This is called memory. Flip flop is a basic memory circuit.
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The basic memory element used in sequential logic systems is a
flip-flop. A flip-flop has two stable states-logic 0 and logic-1. A flip flop
output can stay in one of the two states after an input is applied and does
not change even after the removal of the input responsible for that output
state. Thus one FF can store only one bit– 0 or 1. We call flip flop as 1–bit
memory or storage device. Fli- flops are also known as bistable multi-
vibrator, multi-binary, toggle or latch.
A Set-Reset is the simplest sequential circuit. It can be
constructed in many ways. In fig. (1) it is formed using NAND gates while in
fig. (2) using NOR gates.
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Fig. (1) SR latch using NAND gates
CONDITION
R + S = 0 (or R= S=1) is avoided
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The circuit has two inputs, S and R, and two outputs Q and Q'.
Feedback connection to form the sequential circuit is shown in the figures; each
of the outputs is connected as one of the inputs to a gate which controls the
other output. Thus circuit's outputs depend on the present inputs and also on the
present outputs (which are the result of earlier inputs).
There are two possible ways in which Q and Q' can differ; Q = 0 and
.
Q' =1 (= ), Q or Q =1 and Q' = 0 (= ). Q
Thus Q' = , outputs are complementary to each other. Both cases are stable
one, i.e., the circuit will remain in one state and will not change as long as the
input conditions do not change
Q
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Fig. (2) SR latch using NAND gates.
Condition R= S=1 is avoided
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From fig. (1), we express the outputs as
QSQ = (1a)
=S+Q using De Morgan's theorem
and Q'= Q QR.=(1b)
= R + Q using De Morgan's theorem
Putting eq. 1(b) in eq. 1(a) we can get the characteristic equation for the
flip flop as
QRSQRSQSQ +=== )(using De Morgan's theorem.
From fig. (2), we express the
+==
+=
QRQQ
QSQ
'and(2)
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We note that outputs of the two figures have the same expressions. We
can trace another SR flip flop NOR gate circuit as shown in fig. (3). In
this case output are
+=
+=
QSQ
QRQ (3)
and
For these circuits, there combinations of inputs [but only two output states
either [Q = 0 ( = 1) or Q=1 ( = 0)].
We shall discuss these input conditions. In truth
table we shall use Qn and Qn+1, to denote the present and next output state of
the flip flop. That is, say for example, for S = R = 0 inputs, they denote
Qn = value of Q before S= R= 0 condition was imposed
Qn+1 = value of Q after S =R = 0 condition was imposed
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Fig. (3) Another SR flip-flop NOR circuit
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The subscript n and (n+1) are used because there will be in general
numerous times during which the control inputs (the signals applied to S and R
terminals are control inputs, often called data inputs) will change. With regard to
the output terminals, it is usually convenient to think of the Q terminal as the main
output even though both Q and Q' signals are available. When the Q output is HIGH
(logic 1), we say that the flip flop is SET (al is stored) and when the Q output is LOW
(logic 0), we say that the flip flop is RESET or CLEARED (a0 is stored).
We now discuss the four input conditions
(i) S =R = 0 : From eqs. (1), (2) and (3), we get
Q= Q and Q' = Q
Thus when both inputs go to logic 0, the output will remain in the state
it has before the change. That is,
Qn+1= Qn, and Q'n+l = Q'n
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(ii) S = 1, R = 0 Equations give
Q = 1 + Q = 1
Q' = 0 + Q =0
Hence these input conditions force Q to become al.
Any action which ensures that Q= 1 is SET action.
(iii) S = 0, R = 1 This is opposite to case (ii) and will give
Q = 0 and Q'=1
Any action which ensures that Q' = = 1 is RESET action =0Q
(iv) S = 1, R = 1, Not allowed (invalid).
These inputs give Q = 1 and Q' =1 (using eqs. 1, 2 or 3). Though the
situation is stable but another difficulty arises which leads to the situation in which
outputs can not be defined with certainty. It is a race condition
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