The FE-I4 Pixel Readout System-on-Chip for ATLAS Experiment Upgrades

Tomasz Hemperek on behalf of ATLAS Pixel Collaboration

ATLAS Detector

21/09/20102

Pixel Detector: 3 barrels 112 staves 1744 modules 80 million channels

IBL = New Insertable B-Layer at 33 mm

IBL

Beam pipe

Existing B-layer

Current Pixel Detector Module

21/09/20103

16-front-end chip (FE-I3) module with a module controller chip (MCC)

Planar n-on-n DOFZ silicon sensors, 250 μm thick

Designed for for 1 x 1015 1MeV neq fluence and 50 MRad

Front End ChipFE-I3 FE-I4

21/09/20104

Pixel Size [μm2] 50×400 50×250Pixel Array 18×160 80×336Chip Size [mm2] 7.6×10.8 20.2×19.0Active Fraction 74 % 89 %Output Data Rate [Mb/s] 40 160Transistor Count [M] - ~80

2mm

16.8

mm

8mm

2.8m

m

7.6mm

20.2mm

Double Hit Column Waiting (FE-I3)

21/09/20105

Inefficiencies

ToT

Vth

Lost LE

Time over Threshold ~Q

Vth

LE

1. Record2. Transfer3. Trigger4. Transmit

Motivation

21/09/20106

0%

20%

40%

60%

80%

100%

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 2 2.5 3 3.5 4 4.5 5

Hit probability per Double-Column

Inefficiency for FE-I3 at 3.7cm

Total Double Hit Wrong Bunch Crossing Busy Pixel

LHC

IBL SLH

C

New FE improvements

21/09/20107

New technology Smaller pixel size Bigger chip size and active area New digital architecture New analog pixel Reduce number of external components New powering schemes Decrease cost (per area) Better radiation hardness

FE-I4 Functional Overview

21/09/20108

Pads / RX /TX

Double Column

End Of Chip Logic

Data Output Block

Phase Lock Loop

Command Decoder

SEU-Hard Memory

DACs & Reference

Power

4 Pixel Region

Pixel Array

Analog Pixel

21/09/20109

150 µm

50 µm

Cc

Cf2Cf1

Preamp Amp2

feedbox feedbox

Inj0

Inj1

injectIn

Cinj1

Cinj2

+local

feedback tune

FDAC4 Bit

Vfb

+local

thresholdtune

TDAC5 Bit

Vfb2

+

-

HitOutNotKill

Vth

Two-stage architecture optimized for low power, low noise and fast rise time

Additional gain Cc/Cf2~ 6 More flexibility on choice of Cf1 Charge collection less

dependent on detector capacitor

Decoupled from preamplifier DC potential shift caused by leakage

Local DACs for tuning feedback current and global threshold

Charge injection circuitryPreamp

Am

p2

FDAC

TDAC

discri

FE-I4-P1 (Prototype)

21/09/201010

61x14 pixel array Silicon proven RadHARD up to 200MRad

(loaded ~400 fF)

<ENC> = ~65 e

Noise Measurements

Noise Measurements (Irradiation)

4 Pixel Region

21/09/201011

- Analog - Digital

0

5000

10000

15000

20000

25000

30000

1 2 3 4 5 6

central module - ϕ direction

Mean: 1.76

Cluster size projection

0

5000

10000

15000

20000

25000

30000

1 2 3 4 5 6

central module - Z direction

Mean: 1.87 4 analog pixels are connected to one digital region

Analog pixels can operate and be tested independently from digital part

Pixel organization

Digital Region (simplified)

21/09/201012

- Hit Processing- ToT Counter- ToT Memory- Latency Counter- Triggering/Readout

Receiving hit

Start ToT counter

Assign first free memoryand latency counter

Generate trailing edge

Store ToT value

Check for trigger when latency counter finished

Indicate ready to read status (release token)

Release memory after read

Read memory

Generate leading edge

Regional Buffer Overflow FE-I4 Inefficiency (3.7cm)

21/09/201013

FE-I4 Inefficiency

MemoriesSimulation

IBL 10xLHC

5 0.047% 2.19%

6 0.011% 0.65%

7 <0.01% 0.16%

0%

1%

2%

3%

4%

Hit probability per pixel

Total Double Hit Buffer OverflowLH

C

IBL

SLH

C

Mean ToT = 4

Column Readout

21/09/201014

TokenBus

End of Chip Logic

Two prioritized token scenario (column and periphery level)

One data bus End of column logic selects

column to read Chip control logic controls

trigger and read Data is always read in the

same order All buses including address

(thermal encoded) protected with hamming encoding

Pixel Array Layout

21/09/201015

Digital Region

AnalogPixel

50x250µm

Framing / Transmission

21/09/201016

Re-

Form

attin

g

Eve

nt B

uild

er

Asy

nchr

onou

s re

dund

ant F

IFO

(8

x32b

it)

8b10

b E

ncod

ing

Fram

ing

Ser

ializ

er

Readout Control

Dat

a S

witc

h

Hamming Encoded Pixel Data

Header

Service

TX

40MHz Clock Domain160MHz Clock Domain

Re-formatting: Data reduction about 25% and 8-bit word format

Ham

min

g D

ecod

er

DC/DC

Serial Power

21/09/201017

Powering

Shunt LDO

FE-I41.2V1.5V Shunt LDO

Shunt LDO

FE-I41.2V1.5V Shunt LDO

IinIout

2x DC/DC LDO

FE-I4 1.2V1.5V

3.3V

2x DC/DC LDO

FE-I4 1.2V1.5V

Saving cable material budget

Reduction of cable power losses

New Module Concept

21/09/201018

Sensor technology independent. Decision on sensors after prototyping with

FE-I4 Minimum amount of external components

FE-I4

Sensor

Flex

Design Flow

21/09/201019

Design in “big A small D” methodology Blocks designed and verified individually Full chip digital and mixed-signal verification Work synchronization with integrated Revision Control System Big chip = many difficulties with software and PDK!

Analog Block Design & Verification

Digital Block Design & Verification

Integration

Full Chip Verification

Verification

21/09/201020

Full chip verification based on Open Verification Methodology (OVM) with multiple physics based and random test

ANALOGARRAY

(digital part)

DIGITALARRAY

END OF COLUMN

END OF CHIP

COMMAND DECODER

REGISTER MEMORYPLL

PLL

DATA OUTPUT

- verilog model- Implementation (RTL/gate)

FE-I4

DETECTOR(PIX)

OUTPUT(RECEIVE)

MANUAL

SLOW COMMAND

(CMD)

Modeling Interfaces

Conclusion

21/09/201021

Project duration: ~3 years Design team: ~21 persons+

FE-I4A last official shipping date: This Thursday (23rd September 2010) Test setup readiness ramping-up, on time for IC back Tests: Wafer, single-chip, bump-bonded (planar, 3D, diamond), irradiation

Design teamBonn: D. Arutinov, M. Barbero, T. Hemperek, A. Kruth,

M. KaragounisCPPM: D. Fougeron, F. Gensolen, M. MenouniGenova: R. Beccherle, G. DarboLBNL: S. Dube, D. Elledge, J. Fleury (LAL),

M. Garcia-Sciveres, D. Gnani, F. Jensen, A. MekkaouiNIKHEF: V. Gromov, R. Kluit, J.D. Schipper, V. Zivkovic

Extra Slides

21/09/201022

Test Chips

21/09/201023

FE-I4-P1

LDORegulator

ChargePump

CurrentReference

DACs

Con

trol

Blo

ckC

apac

itanc

eM

easu

rem

ent

FE-I4-P161x14 Array

SEU test IC

4-LVDS Rx/Tx

ShuLDO+tristLVDS/LDO/10b-

DAC

turboPLL: PLL core + PRBS +

8b10b coder + LVDS driv

low power discri.

Clocking

21/09/201024

Phase Lock Loop (PLL) type 2

Voltage Controlled Oscillator (VCO) at 640 MHz (x16)

Lost of Lock Detection 2 Independent output

multiplexers Silicon Proven

LVDS TX LVDS RX

21/09/201025

Data Transmission

M3 M4

M5 M6

CMFBCMOSdriver

D

D

D

VofsVcm

Vbp

Vbn

5pF

5pF

100k 100k

TX

TX

M11 M12 M13 M14

M8

M9 M10

M4 M5 M6 M7

M1

M2 M3

RX RX

M14

M15 M16

M18M17

OUT

M20M19

M21 M22

Transition speed up to 330 MHz RadHARD up to 200MRad Silicon Proven

Shunt-LDO

21/09/201026

+ -

+

-

+

-

Iin

Iout

Vref

Vout

A1

A2

A3

M1M2

M3

M4

M5

R1

R2

Vin

Iload

R3

M6

Ishunt

Combination of LDO and shunt transistor „Shunt-LDO“ regulators having completely different output voltages can

be placed in parallel without any problem regarding mismatch & shunt current distribution

„Shunt-LDO“ can cope with an increased supply current if one FE-I4 does not contribute to shunt current e.g. disconnected wirebond

Can be used as an ordinary LDO when shunt is disabled Silicon Proven

RadHARD Memory

21/09/201027

Silicon Proven RadHARD and SEU Tolerant