The Fabrication and Characterization with Dielectric HfTiO n...
Transcript of The Fabrication and Characterization with Dielectric HfTiO n...
中 華 大 學
碩 士 論 文
題目:高介電係數材料氧化鈦鉿之 n 型場效電晶
體之研製
The Fabrication and Characterization with
High-� Dielectric HfTiO n-MOSFETs
系所別:電機工程學系碩士班
學號姓名:M09601033 羅方鴻
指導教授:謝焸家博士、荊鳳德博士
中華民國九十八年七月
i
高介電係數材料氧化鈦鉿之
n 型場效電晶體之研製
研究生:羅方鴻
指導教授:謝焸家教授、荊鳳德教授
中華大學 電機系研究所 電子電路組
摘 要
隨著傳統元件尺寸微縮面臨了越來越多困難的挑戰,一些新的解決方法能
夠持續元件的微縮。其中之一,就是使用金屬閘極來替代傳統的多晶矽閘極。可
消除多晶矽的空乏、硼穿透及高阻抗的問題。而另一個方法則是使用高介電係數
材料去取代傳統的絕緣層-二氧化矽,來解決過大的漏電流問題。因此,我們將
探討高介電係數材料絕緣層及閘極材料的研究與應用。對高介電係數材料來說,
必須要有夠高的介電係數,能隙寬度也要夠寬。氧化鈦有著相當高的介電係數,
但能隙寬度不夠寬,而氧化鉿有夠寬的能隙,也有足夠的介電係數,因此,吾人
提出將兩種材料混合的高介電係數材料取代二氧化矽做絕緣層。
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The Fabrication and Characterization with
High-� Dielectric HfTiO n-MOSFETs
Student::::Fang-Hung Lo
Advisor::::Dr. Ing-Jar Hsieh and Dr. Albert Chin
Department of Electrical Engineering
Chung Hua University
Abstract
As traditional device scaling is facing increasingly difficult challenges, some
novel solutions are enabling continued performance scaling. One way to the continued
performance improvements has been to use metal gate electrodes to replace the
polycrystalline silicon (poly-Si) gate electrodes. The metal gate will eliminate the
poly-Si depletion, boron penetration and high resistivity problems. The other way,
which has used high-κ dielectric to replace traditional insulator layer-SiO2 , to solve
the large leakage current problem. As the result, we will investigate the application of
high-κ dielectric and metal gate process technologies. For high permittivity materials,
we must have high enough permittivity and wide bandgap. TiO2 has very high
permittivity but narrow bandgap. HfO2 has high enough permittivity and wide
bandgap .As the result, we combine these two high permittivity materials to replace
SiO2 for gate insulator.
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Acknowledgement
First of all, I would like to thank my advisor Prof. I. J. Hsieh and Prof. Albert
Chin for their fruitful discussions and illuminative suggestions during the period of
my working toward master degree. Their inspiration benefits me a lot on the creative
ideas, effective schedule control and the integrity to the processing tasks. I am also
grateful to ED633 group members – Dr. N. C. Su, Dr. C. H. Wu, Dr. W. B. Chen, Dr.
K. Y. Cho, Dr. M. F. Zhang, Dr. S. H. Lin, and my classmate C. C. Tang for their
enthusiastic assistance and cooperation.
Moreover, I am appreciative of the financial and equipment supports form
National Science Council, National Nano Device Lab (NDL), and Semiconductor
Center of NCTU. I am also grateful to those who ever assisted this work.
Finally, I greatly appreciate my parents and family. Without them, I can’t finish
this dissertation.
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Contents
Abstract (in Chinese)…………………………………………………………………i
Abstract (in English)...................................................................................................ii
Acknowledgement........ ................... ............................................... ....iii
Contents... .. ... .. .. .. .... . . .. .. ... .. .. .. ... .. . . .. ... .. .. .. .. .. .. . .. .. .. ... .. .. .. ... .. .. .. .. .. ... .iv
Figure Captions……………………………………………………………...………vi
CHAPTER 1 Introduction
1.1 High-� Gate Dielectrics Materials……………………………………… 1
1.2 Motivation Metal Gate Electrodes……………………………………….4
CHAPTER 2 The Basic MOSFET Operation
2.1 MOSFET Structure………………………………………………...……9
2.2 Current-Voltage relationship………………………………………….10
2.3 Transconductance……………………………………………………...14
2.4 The CMOS Technology………………………………….……………..16
CHAPTER 3 Experimental steps
3.1 Device Fabrication Process……………………………………………..27
3.2 The n-MOSFET Device of Fabrication………………………………….28
CHAPTER 4 Result and Discussion
4.1 C-V and J-V Characteristics measured and analysis……………...45
4.2 I-V Characteristics measured and analysis…………………………..46
4.3 Mobility Characteristics measured and analysis……………………...47
v
CHAPTER 5 Conclusion and Suggestion for Future Work
5.1 Conclusion…………………………………….……………………....59
5.2 Suggestion for Future Work………………………………………….…60
Reference………………………………………………………………61
Vita……………………………………………………………………...67
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Figure Captions
CHAPTER 1
Fig. 1-1 The High Performance Logic of CMOS technology requirements
(ITRS2008).
Fig. 1-2 The band offset of popular high-κ materials.
CHAPTER 2
Fig. 2-1 Cross section for an n-channel enhancement-mode MOSFET
Fig. 2-2 Cross section for an n-channel depletion-mode MOSFET
Fig. 2-3 The n-channel enhancement mode MOSFET with an applied gate voltage
VGS − VT
Fig. 2-4 ID versus VDS characteristics for small values of VDS at three VGS
voltages
Fig. 2-5 Cross section and ID versus VDS curve when VGS > VT for a small VDS value
Fig. 2-6 Cross section and ID versus VDS curve when VGS > VT for a large VDS value
Fig. 2-7 Cross section and ID versus VDS curve when VGS > VT for a value of
VDS = VDS(sat)
Fig. 2-8 Cross section and ID versus VDS curve when VGS > VT for a value of
VDS > VDS(sat)
Fig. 2-9 Family of ID versus VDS curves for a n-channel enhancement mode
MOSFET
Fig. 2-10 Family of ID versus VDS curves for a n-channel depletion mode MOSFET
Fig. 2-11 CMOS structures p-well
vii
Fig. 2-12 CMOS structures n-well
Fig. 2-13 CMOS inverter ciriuit
Fig. 2-14 Simplified integrated circuit cross section of CMOS inverter
Fig. 2-15 The splitting of the basic pnpn structure and two-transistor equivalent
circuit of the four-layered pnpn device
CHAPTER 3
Fig. 3-1 RCA clean
Fig. 3-2 Filed-oxide growth
Fig. 3-3 PR deposition 1st
Fig. 3-4 Source and Drain region define
Fig. 3-5 Devlope 1st
Fig. 3-6 Hard Bake 1st
Fig. 3-7 Etch SiO2
Fig. 3-8 Remove PR 1st
Fig. 3-9 Implantation with phosphorus
Fig. 3-10 Activation
Fig. 3-11 PR deposition 2nd
Fig. 3-12 Source and Drain define
Fig. 3-13 Devlope 2th
Fig. 3-14 Hard Bake 2nd
Fig. 3-15 Etch SiO2 on gate
Fig. 3-16 Remove PR 2nd
Fig. 3-17 HfO2 and TiO2 deposition
Fig. 3-18 PDA
Fig. 3-19 PR deposition 3rd
Fig. 3-20 Mask 3#
Fig. 3-21 Devlope 3rd
Fig. 3-22 Hard bake 3rd
Fig. 3-23 Etch HfTiO on Source and Drain
Fig. 3-24 Remove PR 3rd
Fig. 3-25 Al deposition
Fig. 3-26 PR deposition 4th
Fig. 3-27 Mask 4#
viii
Fig. 3-28 Devlope 4th
Fig. 3-29 Hard bake 4th
Fig. 3-30 Etch Al
Fig. 3-31 Remove PR 4th
Fig. 3-32 n-MOSFET device
CHAPTER 4
Fig. 4-1 C-V characteristics of Al/HfTiO in N2 at different temperatures
Fig. 4-2 C-V characteristics of Al/HfTiO in O2 at different temperatures
Fig. 4-3 J-V characteristics of Al/HfTiO in N2 at different temperatures
Fig. 4-4 J-V characteristics of Al/HfTiO in O2 at different temperatures
Fig. 4-5 C-V characteristics of Al/HfTiO and TaN/HfTiO capacitors
Fig. 4-6 J-V characteristics of Al/HfTiO and TaN/HfTiO capacitors
Fig. 4-7 The Id-Vd characteristics of Al/HfTiO n-MOSFET, the gate length is 4µm
Fig. 4-8 The Id-Vd characteristics of TaN/HfTiO n-MOSFET, the gate length is 4µm
Fig. 4-9 The Id-Vg characteristics of Al/HfTiO n-MOSFET, the gate length is 4µm
Fig. 4-10 The Id-Vg characteristics of TaN/HfTiO n-MOSFET, the gate length is
4µm
Fig. 4-11 The extracted electron mobility from Id-Vg characteristics of Al/HfTiO
n-MOSFET.
1
Chapter1
Introduction
1.1 High-� Dielectrics Materials
Since the very beginning of the microelectronics era, the SiO2 gate oxide in the
first transistors was a few hundred nanometers, the functionality and performance of
state-of-the-art devices currently rely on gate oxide that are just a few atomic layers
(~1-2 nm) thick. Until recently, the evolutionary scaling of the gate dielectric and
ULSI devices in general has been accomplished by shrinking physical dimensions. As
the physical thickness of SiO2-based gate oxides approaches ~2 nm, a number of
fundamental problems arise. In this ultrathin regime, some key dielectric parameters
degrade: gate leakage current, oxide breakdown, boron penetration from the
polysilicon gate electrode, and channel mobility. To prevent form short channel effect
in high speed transistor, direct tunneling and mobility degradation. To solve the
problem above, scientists use high dielectric constant material that get thicker
physical thickness with the same EOT as silicon oxide for gate dielectric film.
2
The purpose of CMOS scaling is to enhance the performance of circuit and
increase the packing density in a chip. Driving current of a MOSFET Ids can be well
modeled by the following equation [1],
I�� = 12� COX µn (W L⁄ )(VGS − VT)(VDS) [Eq-1]
Where µn is the effective mobility, COX is the gate capacitance, W is the channel
width, L is channel length. Obviously, drive current is inversely proportional to the
channel length L. Therefore, the shrinkage of channel length is the most effective way
to promote the driving current of a transistor. Another way to improve the Ids is
increasing the COX , i.e. scaling down oxide thickness. [1]
COX = κ�� ε�
���A [Eq-2]
However, thinning gate dielectrics inevitably accompany with larger direct
tunneling current. The more recent high-κ approach is to increase the physical
thickness to reduce the direct tunneling current, at the same time obtain higher values
of gate capacitance using a dielectric material with a higher dielectric constant (high-κ)
Relative to SiO2, [1]
�
��� =
κ�����κ
������κ [Eq-3]
Therefore, we still have enough capacitance value to obtain excellent gate
control ability, lower leakage current and sufficiently large drive current. The gate
leakage current through the gate oxide increases significantly because direct tunneling
3
is the primary conduction mechanism in down-scaling CMOS technologies. To reduce
the leakage current related higher power consumption in highly integrated circuit and
overcome the physical thickness limitation of silicon dioxide, the conventional SiO2
will be replaced with high dielectric constant (high-κ) materials as the gate dielectrics
beyond the 65 nm technology mode [1]-[6]. Therefore, the engineering of high-κ gate
dielectrics have attracted great attention and played an important role in VLSI
technology. Although high-κ materials often exhibit smaller bandgap and higher
defect density than conventional silicon dioxide, using the high-κ gate dielectric can
increase efficiently the physical thickness in the same effective oxide thickness (EOT)
that shows lower leakage characteristics than silicon dioxide by several orders without
the reduction of capacitance density [2]-[5]. According to the ITRS (International
Technology Roadmap for Semiconductor) [7], the suitable gate dielectrics must
have κ value more than 8 for 50-70 nm technology nodes and that must be more than
15 when the technology dimension less than 50 nm. Fig.1-1 shows the evolution of
CMOS technology requirements.
Research on finding an appropriate substitute to the superior SiO2 has been going
on for almost a decade. Oxy-nitrides (SiOxNy) have been introduced to extend the use
of SiO2 in production but eventually it has to be replaced by a high-κ material, such
as Ta2O5, TiO2, HfO2, ZrO2, Al2O3, La2O3 or mixtures of them or metal-oxide-silicates
of the mentioned compounds. Fig. 1-2 shows the summaries of the κ value and band
offset for popular high-κ dielectric candidates.
4
1.2 Motivation of metal-gate electrodes
The poly depletion for reduces the gate capacitance in the inversion regime and
hence the inversion charge density, leading to a lower gate over drive and thus
degrading the device performance. As the result, metal-gate electrodes will be
required for complementary metal-oxide-semiconductor (CMOS) transistors to
eliminate the gate depletion and dopant penetration problems that are associated with
the conventional polycrystalline silicon (poly-Si) gate electrode [7]. In selecting
metal-gate materials for device integration, the metal work function is an important
consideration since it directly affects the threshold voltage and the performance of a
transistor [8]-[10].
However, thermal instability of the effective metal electrode work function (Φ)
on underlying gate dielectric as well as the equivalent oxide thickness (EOT) of the
gate stack remains a major concern for CMOS integration. In addition, an
understanding of how the gate dielectric affects Φ of the metal gate stack is
scientifically and technologically important. Although the interfacial dipole theory
was proposed to describe the dependence of Φ on underlying gate dielectrics [11], it is
not clear whether it can be applied to explain the work functions instability during
high-temperature source/drain annealing.
The work functions (Φm) of metal shown in Fig. 1-3 [] play an important role for
metal-gate/high-κ CMOSFETs. The preferred work function of the metals are ~5.2 eV
for p-MOSFETs and ~4.1 eV for n-MOSFETs. Recently, lots of metal or metal-nitride
5
materials have been widely researched and successfully intergraded in advanced
CMOSFETs, such as TiN, TaN, Pt, Mo and Ir. And Al is one of the most commonly
used metals in the industry, more cheap, low resistance, and low work function.
Fig.1-1 The 1 The High Performance LogicHigh Performance Logic
(ITRS 2008)
6
High Performance Logic of CMOS technology requirements
(ITRS 2008)
of CMOS technology requirements
of CMOS technology requirements of CMOS technology requirements
7
Fig. 1-2 The band offset of popular high-κ materials.
Fig. 1Fig. 1-3 The values of work functioThe values of work functio
8
The values of work function for different metal materialsn for different metal materialsn for different metal materials
n for different metal materials
9
Chapter 2
The Basic MOSFET Operation
2.1 MOSFET Structures
There are four basic MOSFET device types. Fig. 2-1 show an n-channel
enhancement mode MOSFET. Implicit in the enhancement mode notation is the idea
that the semiconductor substrate is not inverted directly under the oxide with zero gate
voltage. A positive gate voltage induces the electron inversion layer, which then
“connects” the n-type source and the n-type drain regions. The source terminal is the
source of carriers that flow through the channel to the drain terminal. For this
n-channel device, electrons flow from the source to the drain conventional current
will enter the drain and leave the source. The conventional circuit symbol for this
n-channel enhancement mode device is also shown in this figure.
Fig. 2-2 shows an n-channel depletion mode MOSFET. An n-channel region
exists under the oxide with zero volts applied to the gate. However, we have shown
that the threshold voltage of an MOS device with a p-type substrate may be negative;
this means that an electron inversion layer already with zero gate voltage applied.
Such a device is also considered to be a depletion mode device. The n-channel shown
in this figure can be an electron inversion layer or an intentionally doped n-region.
The conventional circuit symbol for the n-channel depletion mode MOSFET is also
shown in the figure.
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2.2 Current-Voltage Relationship
Fig. 2-3 shows the MOSFET with an applied gate voltage such that VGS > VT. An
electron inversion layer has been created so that, when a small drain voltage is applied,
the electrons in the inversion layer will flow from the source to the positive drain
terminal. The conventional current through the oxide to the gate terminal and leaves
the source terminal. In this ideal case, there is no current through the oxide to the gate
terminal.
For small VDS values, the channel region has the characteristics of a resistor, so
we can write
IDS = g�VDS [Eq-4]
Where g� is defined as the channel conductance in the limit as VDS → 0. The
channel conductance is given by
g� = W
L∙ µ"#Q"
′ # [Eq-5]
Where µn is the mobility of the electrons in the inversion layer and #Q"′ # is the
magnitude of the inversion layer charge per unit area. The inversion layer charge is a
function of the gate voltage; thus, the basic MOS transistor action is the modulation of
the channel conductance by the gate voltage. The channel conductance, in turn
determines the drain current.
11
The ID versus VDS characteristics, or small values of VDS, are shown in Fig. 2-4.
When VGS < VT, the drain current is zero. As VGS becomes larger than VT, channel
inversion charge density increases, which increases the channel conductance. A larger
value of gd produces a larger initial slope of the ID versus VDS characteristic as
shown in the figure.
Fig. 2-5 shows the basics MOS structure for the case when VGS > VT and the
applied VDS voltage is small. The thickness of the inversion channel layer in the
figure qualitatively indicates the relative charge density, which is essentially constant
along the entire channel length for this case. The corresponding IDS versus VDS
curve is shown in the figure.
Fig. 2-6 shows the situation when the VDS value increases. As the drain voltage
increases, the voltage drop across the oxide near the drain terminal decreases, which
means that the induced inversion charge density near the drain also decreases. The
incremental conductance of the channel at the drain decreases, which the means that
the slope of the ID versus VDS curve will decrease. This effect is shown in the ID
versus VDS curve in the figure.When VDS increases to the point where the potential
drop across the oxide at the drain terminal is equal to VT, the induced inversion charge
density is zero at the drain terminal. This effect is schematically shown in Fig. 2-7. At
this point, the incremental conductance at the drain is zero, which means that the
slope of the ID versus VDS curve is zero. We can write
VGS − VDS&sat* = VT [Eq-6]
12
Or
VDS&sat* = VGS − VT [Eq-7]
Where VDS&sat* is the drain-to-source voltage producing zero inversion charge
density at the drain terminal.
When VDS becomes larger than the VDS&sat* value, the point in the channel at
which the inversion charge is just zero moves toward the source terminal. In this case,
electrons enter the channel at the source, travel through the channel toward the drain,
and then, at the point where the charge goes to zero, the electrons are injected into the
space charge region where they are swept by the E-filed to the drain contact. If we
assume that the change in channel length ∆L is small compared to the original length
L, then the drain current will be constant for VDS > VDS&sat*. The region of the ID
versus VDS characteristic is referred to as the saturation region. Fig. 2-8 shows this
region of operation.
As VGS changes, the ID versus VDS curve will change. We saw that, if VGS
increase, the initial slope of ID versus VDS increases. We can also note from eq-7
that the value of VDS&sat* is a function of VGS. We can generate the family of curves
for this n-channel enhancement mode MOSFET as shown in Fig. 2-9. The general ID
versus VDS family of curves for an n-channel depletion mode MOSFET is show in
Fig. 2-10.
13
In the non-saturation region, we will obtain
IDS =W µ-COX
1L22&VGS − VT*VDS − VDS
1 3 [Eq-8]
And, in the saturation region, we will have
ID =W µ-COX
1L&VGS − VT*1 [Eq-9]
14
2.3 Transconductance
The MOSFET transconductance is defined as the charge in drain current with
respect to the corresponding change in gate voltage, or
g4 = 5ID
5VGS [Eq-10]
The transconductance is sometimes referred to as the transistor gain. If we
consider an n-channel MOSFET operating in the non-saturation region, then, using
[Eq-6], we have
g4L = 5ID
5VGS=
Wµ-COX
L∙ VDS [Eq-11]
The transconductance increases linearly with VDS but is independent of VGS in
the non-saturation region. The I-V characteristics of an n-channel MOSFET in the
saturation region were given by [Eq-6]. The transconductance in this region of
operation is given by
gms = 5ID&sat*
5VGS=
WµnCOX
L&VGS − VT* [Eq-12]
In the saturation region, the transconductance is a linear function of VGS and is
independent of VDS.
The transconductance is a function of the geometry of the device as well as of
carrier mobility and threshold voltage. The transconductance increases as the width of
15
the device increase, and it also increases as the channel length and oxide thickness
decrease. In the design of MOSFET circuits, the size of the transistor, in particular the
channel width W, is an important engineering design parameter.
16
2.4 The CMOS technology
The primary objective of this text is to present the basic physics of
semiconductor materials and devices without considering in detail the various
fabrication processes; this important subject is left to other texts. However, there is
one MOS technology that is used extensively, for which the basic fabrication
techniques must be considered in order to understand essential characteristics of these
devices and circuits. The one MOS technology we will consider briefly is the
complementary MOS, or CMOS, process.
We have considered the physics of both n-channel and p-channel enhancement
mode MOSFETs. Both devices are used in a CMOS inverter, which is the basis of
CMOS digital logic circuits. The dc power dissipation in a digital circuit can be
reduced to very low levels by using a complementary p-channel and n-channel pair.
It is necessary to form electrically isolated p- and n-substrate regions in an
integrated circuit to accommodate the n- and p-channel MOSFET will be fabricated.
A diffused p-region, called a p well, is formed in which the p-channel MOSFET will
be fabricated. A diffused p-region, called a p well, is formed in which the n-channel
MOSFET will be fabricated. In most cases, the p-type substrate doping level must be
larger than the n-type substrate doping level to obtain the desired threshold voltages.
The larger p doping can easily compensate the initial n doping to form the p well.
A simplified cross section of the p-well CMOS structure is shown in Fig.2-11.The
notation FOX stands for field oxide, which is a relatively thick oxide separating the
17
devices. The field oxide prevents either the n or p substrate from becoming inverted
and helps maintain isolation between the two devices. In practice, additional
processing steps must be included; for example, providing connections so that the p
well and n substrate can be electrically connected to the appropriate voltages. The n
substrate must always be at a higher potential than the p well; therefore, this pn
junction will always be reverse biased.
With ion implantation now being extensively used for threshold voltage control,
both the n-well CMOS process and twin-well CMOS process can be used. The n-well
CMOS process, shown in Fig. 2-12, starts with an optimized p-type substrate that is
used to form the n-channel MOSFETs.(The n-channel MOSFETs, in general, have
superior characteristics, so this starting point should yield excellent n-channel devices.)
The n well is then added, in which the p-channel devices are fabricated. The n-well
doping can be controlled by ion implantation.
The twin-well CMOS process, shown in Figure xxx, allows both the p-well and
n-well regions to be optimally doped to control the threshold voltage and
transconductance of each transistor. The twin-well process allows a higher packing
density because of self-aligned channel stops.
One major problem in CMOS circuits has been latch-up. Latch-up refers to a
high-current, low-voltage condition that may occur in a four-layer pnpn structure. Fig.
2-13 shows the circuit of a CMOS inverter and Fig. 2-14 shows a simplified
integrated circuit layout of the inverter circuit. In the CMOS layout, the p+-source to
n-substrate to p-well to n+-source forms such a four-layer structure.
18
The equivalent circuit of this four-layer structure is shown in Fig. 2-15. The
silicon controlled rectifier action involves the interaction of the parasitic pnp and npn
transistors. The npn transistor corresponds to the vertical n+ source to p well to n
substrate to p+-source structure. Under normal CMOS operation, both parasitic bipolar
transistors are cut off. However, under certain conditions, avalanche breakdown may
occur in the p-well to n-substrate junction, driving both bipolar transistors into
saturation. This high-current, low-voltage condition latch-up can sustain itself by
positive feedback. The condition can prevent the CMOS circuit from operating and
can also cause permanent damage and burn-out of the circuit.
Latch-up can be prevented if the product β"β< is less than unity at all times,
where β" and β< are the common-emitter current gains of the npn and pnp parasitic
bipolar transistors, respectively. One method of preventing latch-up is to “kill” the
minority carrier lifetime. Minority carrier lifetime degradation can be accomplished
by gold doping or neutron irradiation, either of which introduces deep traps within the
semiconductor. The deep traps increase the excess minority carrier recombination rate
and reduce current gain. A second method of preventing latch-up is by using proper
circuit layout techniques. If the two bipolar transistors can be effectively decoupled,
then latch-up can be minimized or prevented. The two parasitic bipolar transistors can
also be decoupled by using a different fabrication technology. The silicon-on-insulator
technology, for example, allows the p-channel MOSFETs to be isolated from each
other by an insulator. This isolation decouples the parasitic bipolar transistors.
19
Fig. 2-1 Cross section for an n-channel enhancement-mode MOSFET
Fig. 2-2 Cross section for an n-channel depletion-mode MOSFET
20
Fig. 2-3 The n-channel enhancement mode MOSFET with an applied gate voltage
VGS − VT
Fig. 2-4 ID versus VDS characteristics for small values of VDS at three VGS
voltages
21
Fig. 2-5 Cross section and ID versus VDS curve when VGS > VT for a small VDS
value
Fig.2-6 Cross section and ID versus VDS curve when VGS > VT for a large VDS
value
22
Fig. 2-7 Cross section and ID versus VDS curve when VGS > VT for a value of
VDS = VDS(sat)
Fig. 2-8 Cross section and ID versus VDS curve when VGS > VT for a value of
VDS > VDS(sat)
23
Fig. 2-9 Family of ID versus VDS curves for a n-channel enhancement mode MOSFET
Fig. 2-10 Family of ID versus VDS curves for a n-channel depletion mode
MOSFET
24
Fig.2-11 CMOS structures p-well
Fig. 2-12 CMOS structures n-well
25
Fig. 2-13 CMOS inverter ciriuit
Fig. 2-14 Simplified integrated circuit cross section of CMOS inverter
26
Fig. 2-15 The splitting of the basic pnpn structure and two-transistor equivalent
circuit of the four-layered pnpn device
27
Chapter 3
The Experimental Steps
3.1 Device Fabrication Process
In this study we use a p-type silicon and clean it by a full process from RCA
clean. For device isolation, 500nm oxide was deposited by furnace and device active
region was defined by photolithography and wet etching in BOE for about 5 minutes.
The source and drain regions in the active device region were formed by
ion-implantation with phosphorus (35 Kev at 5×1015cm-2) and activated at 900℃ for
30 minutes annealing in N2 ambient. The second mask was used to remove silicon
oxide in the gate region, and again RCA clean was done to assure the high-κ/Silicon
interface. The third mask was used to remove high-κ dielectrics which on the source
and drain regions by BOE for about 2 minutes. 90 nm thick HfTiO was deposited by
PVD as the gate dielectric, following by a 600℃ post deposition annealing (PDA).
Then gate was formed by depositing 300 nm Al using PVD. Finally, the n-MOSFET
was completed by gate definition with the fourth mask process.
3.2
2 The n
1. RCA clean P
n-MOSFETs Device
1. RCA clean P-type silicon wafer
MOSFETs Device
type silicon wafer
Fig. 3
28
MOSFETs Device of F
type silicon wafer
Fig. 3-1 RCA clean
Fabrication
RCA clean
abrication
2. Filed
3. Photoresist deposition
2. Filed-oxide grow in H
3. Photoresist deposition
oxide grow in H2
3. Photoresist deposition
4800 sccm and O
Fig. 3-
Fig. 3
29
4800 sccm and O2 3000 sccm at 1050
-2 Filed-oxide grow
Fig. 3-3 PR deposition 1st
3000 sccm at 1050
oxide growth
PR deposition 1st
3000 sccm at 1050℃ by furnace
by furnace
4. Source and Drain region define (Mask 1#)
4. Source and Drain region define (Mask 1#) 4. Source and Drain region define (Mask 1#)
Fig. 3
4. Source and Drain region define (Mask 1#)
Fig. 3-4 Source and Drain region define
30
4. Source and Drain region define (Mask 1#)
Source and Drain region defineSource and Drain region define
Source and Drain region define
5. Devlope 45 sec
6. Hard bake at 120
5. Devlope 45 sec
6. Hard bake at 120
5. Devlope 45 seconds by FHD
6. Hard bake at 120 ℃ 3 minutes
ds by FHD-5
Fig. 3
3 minutes
Fig. 3
31
Fig. 3-5 Devlope 1st
Fig. 3-6 Hard Bake 1st
Devlope 1st
Hard Bake 1st
7. Etching SiO
8. Remove PR by ACE
7. Etching SiO2
8. Remove PR by ACE
2 on Source and Drain region by BOE
8. Remove PR by ACE
on Source and Drain region by BOE
Fig. 3
Fig.3
32
on Source and Drain region by BOE
Fig. 3-7 Etch SiO
Fig.3-8 Remove PR
on Source and Drain region by BOE
Etch SiO2
Remove PR 1st
9. Source and Drain imp
10. Activation in N
9. Source and Drain imp
10. Activation in N
9. Source and Drain implantation with phosphorus (35
Fig. 3
10. Activation in N2 at 900
lantation with phosphorus (35
Fig. 3-9 Implantation with phosphorus
00 ℃ for 30 min
Fig. 3
33
lantation with phosphorus (35
Implantation with phosphorus
30 minutes
Fig. 3-10 Activation
lantation with phosphorus (35 Kev at 5
Implantation with phosphorus
Activation
ev at 5x1015 cm
Implantation with phosphorus
cm-2)
11. Photoresist deposition
12. Source and Drain region define (Mask 2#)
11. Photoresist deposition
12. Source and Drain region define (Mask 2#)
11. Photoresist deposition
12. Source and Drain region define (Mask 2#)
11. Photoresist deposition
Fig. 3-
12. Source and Drain region define (Mask 2#)
Fig. 3-12
34
-11 PR deposition 2nd
12. Source and Drain region define (Mask 2#)
Source and Drain define
PR deposition 2nd
Source and Drain define
Source and Drain define
13. Devlope
14. Hard bake
3. Devlope
14. Hard bake
14. Hard bake
Fig. 3
Fig. 3
35
Fig. 3-13 Devlope 2th
Fig. 3-14 Hard Bake 2nd
Devlope 2th
Hard Bake 2nd
15. Etch SiO
16. Remove PR
15. Etch SiO2 on gate by BOE
16. Remove PR
on gate by BOE
16. Remove PR
on gate by BOE
Fig. 3-
Fig. 3
36
-15 Etch SiO
Fig. 3-16 Remove PR 2nd
Etch SiO2 on gate
Remove PR 2nd
17. Hf
18. PDA 600
17. HfO2 and TiO
18. PDA 600℃
and TiO2 deposition by PVD
℃ 5 minutes
deposition by PVD
Fig. 3-17 HfO
s
37
deposition by PVD
HfO2 and TiO
Fig. 3-18 PDA
and TiO2 deposition
PDA
deposition
19. Photoresist deposition
20. Mask 3#
19. Photoresist deposition
20. Mask 3#
19. Photoresist deposition
19. Photoresist deposition
Fig. 3-
Fig. 3
38
-19 PR deposition 3rd
Fig. 3-20 Mask 3#
PR deposition 3rd
Mask 3#
21. Develope
22. Hard bake
21. Develope
22. Hard bake
22. Hard bake
Fig. 3
Fig. 3-
39
Fig. 3-21 Devlope 3rd
-22 Hard bake 3rd
Devlope 3rd
Hard bake 3rd
23. Etch Hf
24. Remove PR by ACE
23. Etch HfTiO on Source and Drain region
24. Remove PR by ACE
TiO on Source and Drain region
Fig. 3
24. Remove PR by ACE
TiO on Source and Drain region
Fig. 3-23 Etch HfTiO on Source and Drain
Fig. 3
40
TiO on Source and Drain region by BOE
Etch HfTiO on Source and Drain
Fig. 3-24 Remove PR 3rd
y BOE
Etch HfTiO on Source and Drain
Remove PR 3rd
Etch HfTiO on Source and Drain
25. Al 500 nm deposition by PVD
26. Photoresist deposition
25. Al 500 nm deposition by PVD
26. Photoresist deposition
25. Al 500 nm deposition by PVD
26. Photoresist deposition
25. Al 500 nm deposition by PVD
Fig. 3
26. Photoresist deposition
Fig. 3-
41
Fig. 3-25 Al deposition
-26 PR deposition 4th
Al deposition
PR deposition 4th
27. Metal region definition (Mask 4#)
28. Develope
27. Metal region definition (Mask 4#)
28. Develope
27. Metal region definition (Mask 4#)
27. Metal region definition (Mask 4#)
Fig. 3
Fig. 3
42
27. Metal region definition (Mask 4#)
Fig. 3-27 Mask 4#
Fig. 3-28 Devlope 4th
Mask 4#
Devlope 4th
29. Hard bake
30. Etch Al
29. Hard bake
30. Etch Al
29. Hard bake
Fig. 3
Fig. 3
43
Fig. 3-29 Hard bake 4th
Fig. 3-30 Etch Al
Hard bake 4th
Etch Al
31. Remove
32. Source
31. Remove PR
32. Source, Gate and Drain definition
PR by ACE
, Gate and Drain definition
Fig. 3
, Gate and Drain definition
Fig. 3-
44
3-31 Remove PR 4th
, Gate and Drain definition
-32 n-MOSFET device
Remove PR 4th
MOSFET device
45
Chapter 4
Result and Discussion
4.1 C-V and J-V Characteristics measured and analysis
Figs. 4-1, Fig. 4-2, Fig. 4-3 and Fig. 4-4 shows the C-V and J-V characteristics
of different PDA temperature and different gas for Al/HfTiO capacitors. We could
found a large capacitance density about 1.8 (µF/cm2) and low leakage current about 7
×10-3 (A/cm2) where is PDA in N2 at 600℃. An equivalent oxide thickness (EOT) of
~1.9 nm is measured. Combining the EOT with a physical thickness of 9 nm, the
dielectric constant of this PVD HfTiO is about 18.3, which is a high value to
overcome the more severe gate leakage current problem for MOSFETs. Fig. 4-5 and
Fig. 4-6 shows the C-V and J-V characteristics of different metal gate n-MOS
capacitors. We could found the value of VFB from Al/HfTiO capacitor is lower than
the value of VFB from TaN/HfTiO.
46
4.2 I-V Characteristics measured and analysis
Fig. 4-7 and Fig. 4-8 shows the transistor Id-Vd characteristics as a function of
Vg-Vt for Al/HfTiO and TaN/HfTiO n-MOSFETs. Al/HfTiO has a large Idsat about
8mA when VG and VD =2 V. It is good enough for a high performance n-MOSFET.
Fig. 4-9 and Fig. 4-10 shows the Id-Vg characteristics of Al and TaN n-MOSFETs
with HfTiO film as the gate dielectric. The Vth is as low as 0.35 V and 0.38 V are
obtained from the linear Id-Vg plot, which is consistent with the φm,eff of 4.1 eV and 4.3
eV from C-V curves.
47
4.3 Mobility Characteristics measured and analysis
Figs. 4-11 show the extracted electron motility versus gate electric field from
measured Id-Vg curves of n-MOSFETs. High electron mobility of 121 cm2/V-s is
obtained at peak value and 1 MV/cm effective field for Al/HfTiON n-MOSFETs.
48
Fig. 4-1 C-V characteristics of Al/HfTiO in N2 at different temperatures
49
Fig. 4-2 C-V characteristics of Al/HfTiO in O2 at different temperatures
50
Fig. 4-3 J-V characteristics of Al/HfTiO in N2 at different temperatures
51
Fig. 4-4 J-V characteristics of Al/HfTiO in O2 at different temperatures
52
Fig. 4-5 C-V characteristics of Al/HfTiO and TaN/HfTiO capacitors
53
Fig. 4-6 J-V characteristics of Al/HfTiO and TaN/HfTiO capacitors
54
Fig. 4-7 The Id-Vd characteristics of Al/HfTiO n-MOSFET, the gate length is 4µm
55
Fig. 4-8 The Id-Vd characteristics of TaN/HfTiO n-MOSFET, the gate length
is 4µm
56
Fig. 4-9 The Id-Vg characteristics of Al/HfTiO n-MOSFET, the gate length is 4µm
57
Fig. 4-10 The Id-Vg characteristics of TaN/HfTiO n-MOSFET, the gate length
is 4µm
58
Fig. 4-11 The extracted electron mobility from Id-Vg characteristics of Al/HfTiO
n-MOSFET.
59
Chapter 5
Conclusion and Suggestion for Future Work
5.1 Conclusion
We have fabricated and characterized high-performance n-MOSFET which
incorporates high-κ HfTiO dielectric with low work-function Al metal gate that
provides good dielectric properties such as low threshold voltage and low leakage
current. These devices exhibit excellent electrical characteristics and high drive current.
Investigation on the temperature variation of HfTiO n-MOSFETs shows improved
electrical characteristics for 600℃ in N2. It is improved not only capacitance density
but also low leakage current.
60
5.2 Suggestion for Future Work
Although we have fabricated Al gated n-MOSFETs on HfTiO gate dielectric with
1.9 nm EOT. The fully Al/HfTiO device has high effective work function of 4.2 eV,
high peak electron mobility of 121 cm2/V-s, several works are worthy to do in the
future and are recommended here:
1. We need to find the way how to fabricate the device of CMOSFET.
2. Because the threshold voltage is not small enough, we need to search new
electrode of high-κ metal gate to improve the thermal voltage.
3. In future, we will apply this work in my investigation to the present circuit
design in order to check the influences of short channel effects in the advanced
CMOSFET technology.
4. We should also measure the reliability of the Al/HfTiO CMOSFET.
61
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67
Vita
姓名:羅方鴻
性別:男
出生年月日:民國 74 年 9 月 28 日
籍貫:台北市
住址:台中市西區模範街 40 巷 4-1 號 1 樓
學歷:私立中華大學電機工程學系
(92 年 9 月~96 年 6 月)
私立中華大學電機工程研究所電子電路組
(96 年 9 月~98 年 6 月)
論文題目:
高介電係數材料氧化鈦鉿之 n 型場效電晶體之研製
The Fabrication and Characterization with High-κ Dielectric HfTiO nMOSFETs