The DSP Flow for SmartFusion2 SoC FPGA

8/13/2019 The DSP Flow for SmartFusion2 SoC FPGA

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The DSP Flow For SmartFusion2 SoC

FPGAQuickstart and Design Tutorial


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The DSP Flow For SmartFusion2 SoC FPGA - Quickstart and Design Tutorial

The DSP Flow For SmartFusion2 SoC FPGA - Quickstart and Design Tutorial 2

Table of Contents

Introduct ion .................................................................................................... 3Tutorial Requirements ................................................................................................................ 3Synphony Model Compiler ME (Microsemi SoC Products Group Edition) Software andLicense Availability ..................................................................................................................... 3Tutorial for Using Synphony Model Compiler ME G-2012.09M-2 withLibero SoC ...................................................................................................... 5Synphony Model Compiler ME G-2012.09M-2 .......................................................................... 5Tutorial Steps ............................................................................................................................. 6Step 1 Create a RTL from the DSP Block in Matlab ............................................................... 7Step 2 Create a New Libero Soc Project .............................................................................. 15Step 3 Import the RTL, Testbench, and Test Vector Files ................................................... 16Step 4 Set Up the Simulation Environment and Perform Simulation .................................... 19Step 5 Synthesize the Design with Synplify Pro AE ............................................................. 23Step 6 Place-and-Route the Design Using Libero SoC Tool ................................................ 28List of Changes ............................................................................................ 31Product Support .......................................................................................... 33Customer Service ..................................................................................................................... 33Customer Technical Support Center ........................................................................................ 33Technical Support .................................................................................................................... 33Website .................................................................................................................................... 33Contacting the Customer Technical Support Center ............................................................... 33ITAR Technical Support ........................................................................................................... 34


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The DSP Flow for SmartFusion2 SoC FPGA - Quickstart and Tutorial 3

Introduction

The DSP flow for SmartFusion

2 system-on-chip (SoC) field programmable gate array (FPGA) tutorialdemonstrates the essential flow for directly generating the RTL files from the design/ higher level algorithm

created in Mathworks MATLAB/Simulink

software.

This Tutorial assumes that the Mathworks MATLAB /Simulink software and license are already installed. In

addition, you need to install the SynopsysSynphony Model Compiler ME. The Synphony Model Compiler

ME can only be launched from the MATLAB/Simulink tools.

Visit www.mathworks.com/products/product_listing/index.html for more information on MATLAB/Simulink

software.

Visitwww.microsemi.com/soc/download/software/dsp/default.aspxfor Synphony Model Compiler ME.

Tutorial Requirements

Software RequirementsThis tutorial requires the following software installed on your PC:

Microsemi Libero SoC 11.0

ModelSim v10.1c

Synphony Model complier ME G-2012.09M-2

Matlab/simulink

Project Files

The project files associated with this tutorial includes the following:

Source

Solution

A readme file

Download the project files from:

www.microsemi.com/soc/download/rsc/?f=SmartFusion2_DSP_Flow_Tutorial_DF.Refer to the readme file

for the complete directory structure.

Synphony Model Compiler ME (Microsemi SoC Products GroupEdition) Software and License Availability

The Synphony Model Compiler ME software and licenses are available for free to MicrosemiSoC Products

Group customers at:www.microsemi.com/soc.
http://www.mathworks.com/products/product_listing/index.htmlhttp://www.mathworks.com/products/product_listing/index.htmlhttp://../www.microsemi.com/soc/download/software/dsp/default.aspxhttp://../www.microsemi.com/soc/download/software/dsp/default.aspxhttp://../www.microsemi.com/soc/download/software/dsp/default.aspxhttp://www.microsemi.com/soc/download/rsc/?f=SmartFusion2_DSP_Flow_Tutorial_DFhttp://www.microsemi.com/soc/download/rsc/?f=SmartFusion2_DSP_Flow_Tutorial_DFhttp://www.microsemi.com/sochttp://www.microsemi.com/sochttp://www.microsemi.com/sochttp://www.microsemi.com/sochttp://www.microsemi.com/soc/download/rsc/?f=SmartFusion2_DSP_Flow_Tutorial_DFhttp://../www.microsemi.com/soc/download/software/dsp/default.aspxhttp://www.mathworks.com/products/product_listing/index.html


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Tutorial for Using Synphony Model Compiler

ME G-2012.09M-2 with Libero SoC

The Synphony Model Compiler ME translates a design from a higher level algorithm description in Simulink

into RTL code that can be synthesized using Synplify Pro AE. The Synphony Model Compiler ME also

creates an HDL testbench for the design by capturing the stimulus used to test the design within the

Simulink environment. This facilitates verification and makes the RTL- bit and cycle accurate, when

compared to the Simulink model of the DSP design.

Currently MATLAB and Simulink (including Synphony Model Compiler ME) are not integrated in Libero

System-on-Chip (SoC). Also, the current Synphony Model Compiler ME supports SmartFusion2 SoC FPGA

family. To infer the MACC blocks, Smartfusion2 SoC FPGA device is used for RTL generation in Synphony

Model Compiler.

This document gives step-by-step instructions on how to run Synphony Model Compiler ME and import the

design files, testbench, and test vector files into Libero SoC. It also describes the options and settings

required by Libero SoC for a smooth design flow. This Tutorial uses DDC model design. This design wascreated in Simulink using Synphony Model Compiler Blockset. Visit www.mathworks.com to learn more

about creating design using Simulink.

Synphony Model Compiler ME G-2012.09M-2Figure 1shows the overall DSP design flow using MATLAB/Simulink and Libero SoC with Synplify Pro AE.

The Synphony Model Compiler ME translates the DSP design created in Simulink into RTL.

This RTL can be imported to Libero SoC directly to facilitate smooth synthesis, simulation, place-and-route,

and programming of the design.
http://www.mathworks.com/http://www.mathworks.com/http://www.mathworks.com/


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Tutorial for Using Synphony Model Compiler ME G-2012.09M-2 with Libero SoC

6 The DSP Flow for SmartFusion2 SoC FPGA - Quickstart and Tutorial

Matlab/Simulink

Synphony Model

Compiler ME G-

2012.09M-2

Synplify Pro AEModelsim

Place and Route

User Design

(optional)

MATLA

BENVIRONMENT

LIBEROSoC

ENVIRONMENT

Microsemi SoC FPGA

Figure 1.Microsemi SoC Products Group DSP Design Flow

Tutorial StepsThis tutorial comprises of the following steps:

Step 1 Create the RTL from the DSP block in Matlab

Step 2 Create a New Libero SoC Project

Step 3 Import the RTL, Testbench, and Test Vector Files

Step 4 Set Up the Simulation Environment and Perform Simulation

Step 5 Synthesize the Design with Synplify Pro AE

Step 6 Place and route the Design Using Libero SoC tool

Step 1is performed in the MATLAB environment; the rest of the steps are completed in Libero SoC. In thistutorial, you will use both VHDLand Verilog flow.


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Step 1 Create a RTL from the DSP Block in Matlab


Step 1 Create a RTL from the DSP Block in MatlabIn this step you will open MATLAB and create RTL using the Synphony Model Compiler ME.

1. Download the ddc.zip file fromwww.microsemi.com/soc/documents/DDC.zipto your desktop. Unzip the

file, and save ALL items to C:\demo .

2. Open MATLABand set the current folder location to C:\demo .

3. Double-click the ddc.mdlfile to open the design file. This file is located in C:\demo.The ddc.mdl design is shown inFigure 2.Ignore if any message pops-up by clicking ok andif

ddc_obsolete.mdl pops-up close the file.

Figure 2.DDC Design

4. Click Q_out and set the Function Block Parameters to Capture test vectors fo r RTL Test bench and

Register ou tput, as shown inFigure 3.
http://www.microsemi.com/soc/documents/DDC.ziphttp://www.microsemi.com/soc/documents/DDC.ziphttp://www.microsemi.com/soc/documents/DDC.ziphttp://www.microsemi.com/soc/documents/DDC.zip


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Figure 3.Setting the Output Port Q_out

5. Click I_out and set the Function Block Parameters to Capture test vectors for RTL Test benchand

Register ou tput, as shown inFigure 4.

Figure 4.Setting the Output Port I_out

6. Click the arrow button to simulate the design and you can view the spectrums in the scope, as shown in

Figure 5.


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Figure 5.DDC Design After Simulation

7. Double-click the SHLS Tooltoolbox inside the model file and launch the Synphony Model Compiler ME

G-2012.09M-2, as shown inFigure 6.


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Figure 6.Synphony Model Compiler ME User Interface

8. Click New Implementationand in Target Optionstab, select SmartFusion2as the family.


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Figure 7.Target Options

9. To generate the VHDL file, Verilog file and the testbench, set the options in the RTL Options, as shown

inFigure 8.

Figure 8.RTL Options Tab in Implementation Options Dialog Box

10. Click the Design Optionstab and set the options, as shown inFigure 9.


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Figure 9.Design Options Tab in Implementation Options Dialog Box

Note: The Flip Flop Reset Sensitivity can be either Synchronous/Asynchronous, as shown inFigure 9.

11. Click OKto accept all the other implementation settings.

12. Click RUNto run synthesis with the Synphony Model compiler, as shown inFigure 10.

Figure 10.Run Synphony Model Compiler


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Figure 12.Verilog Files Generated by Synphony Model Compiler ME

14. Close the MATLAB.

The RTL files generated from the Matlab/Simulink software using synphony Model compilerME G-2012.09M-2 are ready to use and evaluate on a hardware platform. The Libero SoC is thecomprehensive software suite for designing with Microsemi's SmartFusion2 SoC FPGA family, managing

the entire design flow from design entry, synthesis and simulation, through place-and-route, timing andpower analysis, with enhanced integration of the embedded design flow.


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Step 2 Create a New Libero Soc Project


Step 2 Create a New Libero Soc ProjectThis step uses the Libero Soc software to create a project for the tutorial design. A Libero SoC project sets

the design name, the HDL flavor (VHDL or Verilog), and the tool locations.

1. Double-click the Libero SoC Icon on your desktop to start the Libero SoC Project Manager.

2. From the Project menu, choose New Project. This displays the New Project dialog box, as shown in

Figure 13.

Figure 13.Libero SoC New Project Dialog Box

3. Set the following values in the New Project dialog box:

Project name: DDC_top

Project location: C:\demo

Preferred HDL type:VHDL

Note: For Verilog flow, Preferred HDL type: Verilog.


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4. Set the following values for the Family, Die, and Package in device (as shown inFigure 13):

Family: SmartFusion2

Die: M2S050T_ES

Package: 896 FBGA

Speed:STD

Die voltage:1.2 v

Operating Conditions:COM

5. Clear the Use Design Toolcheck box. The MSS will be used in this tutorial.

6. Click OKto continue.

7. Choose the appropriate tools settings, if they are not already selected, as shown inFigure 14.The tools

shown in this dialog box depend on your installation. If you want to change the default tool settings,

refer to the Libero SoC online help.

Note: You will not perform any FPGA programming as a part of the tutorial. So, the programming tool

selection is not important for this tutorial.

Figure 14.Select Edit Tool Profiles Dialog Box

Step 3 Import the RTL, Testbench, and Test Vector FilesIn this step you import the RTL, testbench, and test vector into Libero SoC

1. Navigate to the File menu in Libero SoC, and choose Import Files. For File of type select HDL source

files(*.vhd,*.v,*.h) and import the ddc.vhd, SynLib_asynch.vhd and Cordic_asynch.vhdfiles from the

path c:\demo\ddc_impl1\vhdl, as shown inFigure 15.Note that in this design tutorial you use only the

ddc.vhdlfile and its associated files generated inStep 2 Create a New Libero Soc Project.


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Step 3 Import the RTL, Testbench, and Test Vector Files


Figure 15.Importing VHDL Source Files

Note: For Verilog flow, import ddc.v, SynLib.v and Cordic.vand define .hfiles, from the path

c:\demo\ddc_impl1\verilog, as shown inFigure 16.

Figure 16.Importing Verilog Source Files

2. From the Filemenu in Libero SoC, select Import Files. For File of type, select HDL Stimulus file

(*.vhd,*.v) and import the ddc_Test.vhdfile. For Verilog flow, import ddc_Test.vfile.


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3. From the Filemenu in Libero SoC, and select Import Files. For File of type, select Simulation files

(*.mem,*.bfm,*.dat,*.txt,*. do) and import all the *.datfiles. The required files are copied into respective

folders, as shown inFigure 17.The Verilog files are copied into respective folders as shown in

Figure 18.

Figure 17.Imported VHDL Source Files into Libero SoC

Figure 18.Imported Verilog Source Files into Libero SoC


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4. In VHDL flow, open the ddc.vhd, SynLib_asynch.vhd, and Cordic_asynch.vhd files. Use the Libero SoC

Find and Replace feature to replace the SHLSLibwith work andsavethe file. This change is needed to

use work, a default library, so that ModelSim and Synplify can find the package definition from the work

library.

5. In Verilog flow, open ddc.v, SynLib.v, and Cordic.vfiles and add `include "define.h" before module

declaration and save the file.

Step 4 Set Up the Simulation Environment and PerformSimulation

After the RTL, testbench, and test vector files have been imported, use ModelSim to perform a pre-synthesis

simulation. First, you need to associate a stimulus file with the design. This lets the ModelSim tool know

which testbench has to be used for the simulation.

To Set up the Stimulus File:

1. In the Design hierarchy tab, for a VHDL flow, right-click ddc.vhdand select Set As Rootwhereas for a

Verilog flow right-click ddc.vselect Set As Root, as shown inFigure 19.

Figure 19.Set As Root

2. Right-click Simulateunder Verify Pre-synthesized Design. Under Organize Input files, select Organize

Stimulus Filesto launch the Organize Stimulus dialog box, as shown inFigure 20.

Figure 20.Organize Stimulus File

3. Select User option to add the stimulus file underAssoc iated Stimulus Fi les , as shown in the

Organize Stimulusdialog box inFigure 21for VHDL flow andFigure 22for Verilog flow.


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Figure 21.Organize Stimulus Dialog Box for VHDL

Figure 22.Organize Stimulus Dialog Box for Verilog

After selecting the stimulus file, you must set the simulation environment.

4. From the Projectmenu, choose ProjectSettingsto open the Project Settingsdialog box, as shown in

Figure 23.

5. In the Simulation options, click the Dotab and set the following:

Testbench module name: test_ddc

Top Level instance: i_ddc

Simulation runtime: -all


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and save the project settings by clicking on the Savebutton.

Figure 23.Project Settings Simulation Options Dialog Box

6. Right-click Simulate underVerify Pre-synthesized Designand choose Open interactively. The

ModelSim VHDL simulator opens and runs simulation using the run.do file, as shown inFigure 24.


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Figure 24.ModelSim User Interface for VHDL

The following message appears after successful completion of testbench simulation and takes two seconds

to complete.

Ti me: 2000275 ns I t er at i on: 5 I nst ance: / t est _ddc

# ** Not e: ******* VHDL Ver i f i cat i on Successf ul ! *******


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Figure 25.ModelSim User Interface for Verilog

The following message appears successful completion of testbench simulation******* Veri l og Veri f i cat i on Successful ! *******

Ti me: 2000275 ps I t er at i on: 2 I nst ance: / t est _ddc

Note: Click Yesto finish Verilog simulation.

Step 5 Synthesize the Design with Synplify Pro AEThe next step is to generate an EDIF netlist (*.edn file) by synthesizing the design with Synplify Pro AE, as

shown inFigure 29.Synplify Pro AE instantiates I/O buffers, synthesizes logic for any behavioral blocks in

the design, utilizes hardcore math blocks for multiplication and addition operations, and generates an EDIF

netlist for Designer to Place-and-Route.

1. Add constraints by providing sdc file (ddc.sdc) to synthesis tool from the paths

C:\demo\ddc_impl_1\verilog or C:\demo\ddc_impl_1\vhdl, as shown inFigure 26, Figure 27,andFigure

28.


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Figure 26.Importing sdc Source File

Figure 27.Selecting Constraints to Synthesis Tool


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Figure 28.Organize Constraint Files of ddc for Synthesis Tool

2. Right-click synthesizeunder Implement design, and click Open Interactively. During invoking ignore

if any pop-up messages are displayed. This launches the synopysis Synplify Pro AE tool with the

appropriate design files, as shown inFigure 29.

3. Set the Frequency to 40 MHz (Default).

4. For VHDL flow, select Run to synthesize the design.

After successful synthesis, in Project Status window under Area summary click on detailed report to

notice the number of DSP math blocks inferred for multiplier operations as shown inFigure 29.


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Figure 29.Synplify Pro GUI for VHDL Flow

5. For a Verilog flow, click Implementation Optionsunder Synopsys Synplify Pro AE GUI and select

Verilog language as Verilog2001, as shown inFigure 30,and select runto synthesize the design.


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Figure 30.Implementation Options for Verilog Flow

InFigure 31,notify the number of DSP math blocks inferred for multiplier operations in DDC design.


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Step 6 Place-and-Route the Design Using Libero SoC Tool


Figure 33.Add Constraint in SmartTime Tool

Figure 34.Specifying the Clock Constraints


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Figure 35.Constraints Editor

3. Close the SmartTime Constraint Editor. Open the I/O attribute editor to assign top-level ports to device

I/O pins by right-clicking Edit I/OAtt ributes under constrain place and route on the Libero design flow

tab and click Open Interactively,asshown inFigure 32.

4. Right-click on Place and Routein the Design flowtab of the Libero SoC. Choose Run . On successful

completion, a green color tick is displayed at Place and Route, as shown inFigure 36.

Figure 36.Implementing Place-and-Route

This concludes the tutorial.


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List of Changes

Revision Changes Page

Revision 5

(April 2013)

Updated the document for 11.0 production SW release (SAR 47102). NA

Revision 4

(February 2013)

Updated the document for Libero 11.0 beta SP1 software release (SAR 45203). NA

Revision 3

(November 2012)

Updated the document for Libero 11.0 beta SPA software release (SAR 42881). NA

Revision 2

(October 2012)

Updated the document for Libero 11.0 beta launch (SAR 41733). NA

Revision 1

(May 2012)

Updated the document for LCP2 software release (SAR 38955). NA

Note: The revision number is located in the part number after the hyphen. The part number is displayed at the bottom of thelast page of the document. The digits following the slash indicate the month and year of publication.


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Product Support

Microsemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This

appendix contains information about contacting Microsemi SoC Products Group and using these support

services.

Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,

update information, order status, and authorization.

From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world 408.643.6913

Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers

who can help answer your hardware, software, and design questions about Microsemi SoC Products. The

Customer Technical Support Center spends a great deal of time creating application notes, answers to

common design cycle questions, documentation of known issues and various FAQs. So, before you contact

us, please visit our online resources. It is very likely we have already answered your questions.

Technical SupportVisit the Microsemi SoC Products Group Customer Support website for more information and support

(http://www.microsemi.com/soc/support/search/default.aspx). Many answers available on the searchable

web resource include diagrams, illustrations, and links to other resources on website.

WebsiteYou can browse a variety of technical and non-technical information on the Microsemi SoC Products Group

home page,athttp://www.microsemi.com/soc/.

Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted

by email or through the Microsemi SoC Products Group website.

Email

You can communicate your technical questions to our email address and receive answers back by email,

fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. Weconstantly monitor the email account throughout the day. When sending your request to us, please be sure

to include your full name, company name, and your contact information for efficient processing of your

request.

The technical support email address [email protected].

My Cases

Microsemi SoC Products Group customers may submit and track technical cases online by going to My

Cases.
http://www.microsemi.com/soc/support/search/default.aspxhttp://www.microsemi.com/soc/support/search/default.aspxhttp://www.microsemi.com/soc/support/search/default.aspxhttp://www.microsemi.com/sochttp://www.microsemi.com/sochttp://www.microsemi.com/soc/http://www.microsemi.com/soc/http://www.microsemi.com/soc/mailto:[email protected]:[email protected]:[email protected]://www.microsemi.com/soc/mycases/http://www.microsemi.com/soc/mycases/http://www.microsemi.com/soc/mycases/http://www.microsemi.com/soc/mycases/http://www.microsemi.com/soc/mycases/http://www.microsemi.com/soc/mycases/mailto:[email protected]://www.microsemi.com/soc/http://www.microsemi.com/sochttp://www.microsemi.com/soc/support/search/default.aspx


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Product Support


Outside the U.S.

Customers needing assistance outside the US time zones can either contact technical support via email

([email protected]) or contact a local sales office. Sales office listings can be found at

www.microsemi.com/soc/company/contact/default.aspx.

ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations(ITAR), contact us [email protected], withinMy Cases,select Yesin the ITAR

drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.
mailto:[email protected]:[email protected]:[email protected]://www.microsemi.com/soc/company/contact/default.aspxhttp://www.microsemi.com/soc/company/contact/default.aspxhttp://www.microsemi.com/soc/company/contact/default.aspxhttp://www.microsemi.com/soc/company/contact/default.aspxhttp://www.microsemi.com/soc/company/contact/default.aspxhttp://www.microsemi.com/soc/company/contact/default.aspxhttp://www.microsemi.com/soc/company/contact/default.aspx#itartechsupportmailto:[email protected]:[email protected]:[email protected]://www.microsemi.com/mycases/http://www.microsemi.com/mycases/http://www.microsemi.com/mycases/http://www.microsemi.com/soc/ITAR/http://www.microsemi.com/soc/ITAR/http://www.microsemi.com/soc/ITAR/http://www.microsemi.com/mycases/mailto:[email protected]://www.microsemi.com/soc/company/contact/default.aspx#itartechsupporthttp://www.microsemi.com/soc/company/contact/default.aspxhttp://www.microsemi.com/soc/company/contact/default.aspxhttp://www.microsemi.com/soc/company/contact/default.aspxmailto:[email protected]


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Microsemi Corpor ate Headquarters

Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor

solutions for: aerospace, defense and security; enterprise and communications; and industrial

and alternative energy markets. Products include high-performance, high-reliability analog and

RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and

complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at

www.microsemi.com.
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The DSP Flow for SmartFusion2 SoC FPGA

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