VLSI DESIGNA COMPLETE VISION OF VLSI DESIGN STYLES

Surya Teja Swamy, Vijay VemuriII/IV - B. Tech , ECE,KL University, Guntur.

WHAT IS VLSI ?

• VLSI refers • V : Very• L : Large• S : Scale• I : Integrated Circuits

CONT…

• VLSI is a process of creating an integrated circuit (IC) by combining thousands of transistors into a single Silicon Chip.

• Before VLSI there are other design process* SSI - 10-100* MSI - 100-1000* LSI - 1000-20000* ULSI - 1000000-100lakhs* GSI - >100lakhs

MOORE’S LAW

• Regarding this IC technology “ ” introduced a law

• For every 18 months transistors are doubled.

MOORE’S LAW

• Regarding this IC technology “GORDON MOORE” introduced a law

• For every 18 months transistors are doubled.

Transistors per Chip

VLSI DESIGN

• In present days all the Electronic Devices are made of using these VLSI CHIPS.

• These VLSI are designed by CMOS.• In Earlier they used several types of active devices.

COMPARISON OF AVAILABLE TECHNOLOGY

VLSI DESIGN USING CMOS

• CMOS ---- C M O S

VLSI DESIGN USING CMOS

• CMOS ---- Complementary Metal Oxide Semiconductor

VLSI DESIGN USING CMOS

• CMOS ---- Complementary Metal Oxide Semiconductor• Combination of PMOS and NMOS• The output of the CMOS is Complement.• For getting true value we need to take a “Invertor” at the

output.

TYPES OF CMOS FABRICATIONS

• N-WELL PROCESS• P-WELL PROCESS• TWIN TUB PROCESS

CMOS P-WELL FABRICATION

Steps 1-4

CONT..

CMOS P-well inverter showing VDD and VSS Substrate connections

Formation of n-well regions

Define nMOS and pMOS active areas

Field and Gate Oxidations (thinox)

Form and Pattern Polysilicon

p+ diffusion

n+ diffusion

Contact cuts

Deposit and pattern metallization

Over glass with cuts for bonding pads

MAIN STEP IN A TYPICAL N-WELL PROCESS

DRAWBACKS OF N-WELL &P-WELL

• In both N-WELL and P-WELL we may got come across two problems.Body Effect &Latch Up problem

• To over come this drawback, we are going for “Twin Tub”.

TWIN-TUB PROCESS* It is made with both n-well and p-well region.

* Epitaxial layer: High purity silicon grown with accurately determined dopant concentrations

CONT…

• At present the CMOS technologists are using “TWIN TUB” process.

• As It is giving effective result.• Also it is more efficient.

DRAWBACKS OF CMOS

• CMOS is quite good for all the ELECTRONIC Gadgets.• As they required 0-5V voltage.• But coming to the ANALOG Equipment's … CMOS is poor to

use.• For that problem we are going to use BICMOS technology.

COMPARISON BETWEEN CMOS AND BIPOLAR TECHNOLOGIES

CMOS• Low static power dissipation• High input impedance• High noise margin• High packing density• High delay sensitivity to load• Low output drive current• Low gm• Bidirectional capability• A near ideal switching device• Scalable threshold voltage

BIPOLAR TECHNOLOGIES• High power dissipation• Low input impedance• Low voltage swing logic• Low packing density• Low delay sensitivity to load• High output drive current • High gm• Essentially unidirectional

BICMOS…

• BICMOS BJT + CMOS

BICMOS…

• BICMOS BJT + CMOS• As the drawback of CMOS is output load.• At the output of the circuits we use BJT.• Entire circuit is designed with CMOS.

CROSS SECTIONAL VIEWBi-CMOS(n-p-n Transistor (orbit 2 um CMOS)

n-well BiCMOS fabrication process steps

BICMOS

FABRICATION

PROCESS