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Vxr3processing and Microprogramming 7 (13811 346350 -.- ,I _“__~_ “.~..____ ._.. ̂ .--.-^ . ,. ._ I __-M ___~_

The Circular Synchronous BUS

Dan Tarnescu, Cristian Baleanu ar:d Alexandru Botta Electrunxs Department. I.P.B.. C P. 68-86, Of. post. L8,

Buwresh, Romank

The concept of a circular synchronous bus is introduced as a way of transferring information in a computing system. The

interconnection protocol for the modules coupled to the bus is detailed. as well as ?echnological aspects of the mtetfaces. In the iast se:tion the circular synchronous bus is compared with other interconnection techniques from the point of view of their

respectiva per%rmances.

K~v,vords Multiprocessor System, System Bus. Bus Algo- rithms. S~nchronovs Bus, Circular Bus.

I. Introdactian

The interconnection model using a circular Tvtichronotis bus (C.S.B.) described in this paper has been worked out a; aa answer to the problem of dcsifning il computing system meeting the following rcquiremcnts:

the system was to be made up of a diversified set of functional modules (bipolar and MOS prwnsors, memories, input-output devices);

the hardware configuration was to be cuntinuuusly changed, as the system had to be a cr’rmpu~er architecture research framework;

any functional module had to communicate wilh any other at a ‘reasonable’ speed;

EIX co51 of the system had to be maintained %llilin low limits.

None of the standard interconnection techniques [I, 3, 41 fulfilled the rechnoiogical and cost restrictions imposed upon the project, so that a IXW ?c>lution had to be devised.

information is circularly shifted from ow rcyistt~

to another under the control of a single clock.

Each register may be coupled through an interface to a functional module M, (Fig. I).

Fig. 1. The Circular Synchronous Bus Principle.

Blocks C,. . . , (3, ensure the bus synchroni- zation by circu1ar.y shifting the clock signal, The interfaces I; implement a unified access discipline to the bus. In the experimental version of the system, each register is actually coupled to a module.

For convenience we shall call ‘waggon’ the information that may be stored in a register and ‘station’ i the register coupled to the interface f,. The waggons succeed each other throuqtl the station at the clock frequency. The structure of a waggon is presented in the Fig. 2.

The waggon type: (1) free - to be used by anybody on any

purpose;

1 he USi% is made up of a set of registers where Fig. 2. The Waggon Structure.

I I

Fiq 4. Module M, Becomes Producer ilnitiarioii).

l’wu main problems have arisen in defining the CSB: the data flow canrrol on the bus and the clsck siguaf generation. Double buffering is used to delay the loading of a new waggon until

Fig. 6. Module M; Becomes Producer (Terminationi,

Fig. 7. Module Mi Becomes Producer Errors Detecrionl.

complclron of the previous waggofl emissian. The ciock signal generation is achieved usirrg a very simple method for triggering and maintairhg the oscillation. Figa 13 shows the structure of a stntion

_---..----~ Fig 13 The Strucrure of the Statkn

-- *og&er with the waveforms which characterize the data flow and the clock @ai generation.

RI, and RO, are the <tation’s input and output registers, respectively (a waggon enters the ;tation by RI! and knaves it from ROi). CDi k the clock ~gmi propagation circuit, which receive the Cl signal from the previous station and generate C, + I tar the next station.

Each sterion introduces a fixed delay d 7, of the clock signal so that the maximum transfer speed helween two adjacent cells is:

I I $) _I_ -- 5 -,--.-; 7 d7ys-dTp

~i’ere Lq T’,, is rile time needed by the interface to I’~I.)CCI;S 2nd alter the waggo];.

T’hc B,.‘, signal rising edge (I) controls the loading ot thr M’, waggon into RI,, and the laading of the X;, into R0,, hence the emission of the previous tvitggtrn {, W, /) towards the next station. The fixed dcl;ty ATi ensures the appropriate loading of the M ‘/ , t w~l;pnrr into the RI, + I, register, and:

- hits 19 . 17 = type 000 = free 001 = reserved 010 = busy 100 = connect command 101 = disconnect command 110 = YES answer 111 = NO answer

- bits 16 _ 9 = receiver address - bits 8 . , I = info / structure - bit 0 = parity bit on waggon

Hence our implementation of the CSB ha5 21 lines (waggo t clock signal).

Fig. 14 presents the block diagram of the interface I,.

The interface is made up of the following modules:

the address recognition block - it recognizes the interface’s own address i and its partner’s k; the data buffer (at least one character) with the facility of detecting transmission errors (parity check); the programmable clock bfock, which measures the transfer quantum of M,, B T, (the minimum amount of time that Mi needs for processing a character);

r----- - - - - _ - _ - _ _ - l - - - - - - - - - _ - _ ,

I#9 i* ..L, I,. ,* ;. :-.r~: Ir*,j3 -71.‘1 ‘li -L

-_---- I

---_--~_-‘-_~

1

Fig. 14. The Structure of the Interface.

-.-~-_-.- -_.- ._.. --^-.._ -..-- ̂ .

5; -,__ _ .-._., -. _. -,-

i-l -!3

fib K--KII_7i

c; -I y* “2 . I ‘

Fg. 15. The Structure al the lmplenonfed Sysrtm.

I, 2. I * ,

4.

5.

6.

:7.

8.

Requires the most expensive memory modules. VW imerconnection hardwsre is expensive. 11 is difficult to modify the system configura- tion. The overall transfer rate is potentially very high. The large number of cables and connectors may affect the system reliability. The possible size ~4 car figuration options are limiicd by the number of memory ports available. The multiport memary considerably improves the system efficiency. This interconnection technique is appropriate for multiprocessor a&d multicomputer systems.

More expensive than time shared bus but cheaper in comparkm with crossbar switch and 3nrdtiport memory. A simple interconnecCon technique from hardware point of view (a limited number of interface circuits and unified interface logic). ii ii LXISL LO modify t!tc hardware configuration of sys;em’:; modules (this implies only ~onnc~tors changing and bus address switch modifying). E hcrt 1:~ a po~enrkl for a very high total transfer rsiit’ which dn2.s nat depend upon the bus lett;?_i ti.

3 hc bus [iirarions) failure is a catastrophic system Failure. Thr overall system performance may be :rnproved by adding new functional modules. ‘liris notution theoretically allows N/2 simul- taneous transfers. Thi% ktcrconnecting technique is appropriate fi?r nardium size systems (including multi- pKKcWlr systems).

The CSB maximum cransfcr rate is obtain& under the fallowing conditions: - utilization of short cables {the system is not fit

for distributed networks); - initiatiorr of dialogues between cfose modules in

relation to the data flow on the bus. If N is the number of modules coupled to the &ES, then at most N/2 dialogues can take place at a time, if they are initiated between ‘neighbours’.

- utilization of symmetric modules wirh respect to their response time:

- an ef’ficient software, in order to rcducc the initiation part of the dialogue.

The erperimcntal results with i: limited rruclcrrs of modules made us conclude that we can use rhc CSB as a system bus for large multiprocessor computers.

References

11 M. COWW~, A Multiprocessor System Desr~n, Proc Af IP5 1963 Fall Int. Computer Conf. (Spartan Books, Baltinore

MD, 1963). 121 D. Del Corso. An ekpenmental multlmicro~roce5~or system

with improved internal communications fat ilities. Euromicro

J. 4 161 (Nov. 19781. 131 P.H. Enslow. Multiprocessor organizatrons - A survey.

Computiq Surveys 9 (1) (March !977). 141 P.H. Enslow (ad.). Multiprocessors and Parallel Processing

(John Wiley, New York, 19741.

Dan Tomescu. born in 1952, is a research ang~near at Bucuresti Polytechnic Ins~tute. where he graduated in Comwtcr Science in 1976. His interest include computer architecture, operating systems, miiroprr.grammable computers. He is currently involved in the design of the s&&are for a grephics system.

Cristian Baleanu, burn in 1452, graduated in Electronics Engineering from Bucuresti Polylechnic Institute in 1976. He is a research enginesr at I.P.B.. currently involved in thedaaign of the hardware for a graphics system. His interests Include microprocessor-based system, computer architectura and he is co-author of a book on computer peripherals.

Alexandra Botta, born t? 1952, graduated in Computer Science from Bucurest; Polytechnic Institute in 1976. He is interested in computer arcnitecture, compiler design and application of syntactic mathods.

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