The challenges and opportunities of Advanced...
Transcript of The challenges and opportunities of Advanced...
The challenges and opportunities ofAdvanced Packaging Materials
Wun-Yan Chen
Industrial Technology Research InstituteMaterial & Chemical Research Laboratories
2014.10.16
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Outline
Global Trends
Taiwan ICT industry overview
IC Packaging material market update
Overview of Advanced packaging technology
Challenges of Advanced packaging material technology
Summary
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Cloud Integrated Services and Living Style
Source: ITRI/IEK Research (2013/10)
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Internet of Things-Pervasive Intelligence
Source: ITU; Morgan Stanley; Samsung Securities; ITRI/IEK Research (2013/09)
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Smartphone Trend of thinner thickness
Thi
ckne
ss (
mm
)
iPhone
iPhone 3G
iPhone 3GS
iPhone 4
iPhone 4S
iPhone 5
GALAXY S
GALAXY S II
GALAXY S III GALAXY
S 4
iPhone
iPhone 3G
iPhone 3GS
iPhone 4iPhone
4S
iPhone 5
600MHz
1.2GHz
1.8GHz
2.4GHz
GALAXY S
GALAXY S II
GALAXY S III
GALAXY S 4
Smartphone pursue the higher clock Rate
ITRI/IEK Research (2013/09)
The Demands and Trend of Mobile Devices
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From Business to Consumer/ From Notebook to Mobile & Internet
Strategy Evolution
Source:Lenovo (2013/11)
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Consumer Electronics -Fast changes
Source: Gartner; ITRI/IEK Research (2013/10)
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Three Key Enabling Technologiesfor IOT applications
Advanced system in package (SiP) technologyMeet with the Light, thin, compact(integrated SiP), multiple functions, power saving, affordable, fast and esthetics.
Sensor technology Measurement of temperature, blood pressure, motion, MEMS sensor, and image sensor are also important and need to be integrated in SiP.
Ultra low power technology Power consumption should be 1/10 of today’s smart cellphones and one charging per week is more appreciative.
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Remark: Inner circles indicate relative market size of Taiwan industries (2012) while outer circles indicate relative global market size; Market share is indicated by %; Value-add and capital investment is estimated based on 2012 data of market leaders in Taiwan, typically better than industry average
Source: ITRI/IEK Analysis (2013/05)
Overview of Taiwan ICT industry performance
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Structure of Taiwan Semiconductor Industry
Wafer probing & Dicing
Fabless
Leadframe
Packaging & TestingFabrication Mask
Wafer
Mask mfg.IC Design Packaging
Chemicals
250 3 16 37
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4
19
Final Testing
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Wafer growth Wafer Slicing
IC Substrate
Source: IEK/ITRI (2012 05)
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Source:IEK/ITRI (2014/05)
Unit: (100M NTD)
Taiwan Semiconductor Industry
1,3951,2661,2151,2081,278IC Testing
3,1502,8442,7202,6962,870IC Packaging
2,5802,3731,8092,1383,167Memory
8,6437,5926,4835,7295,830IC Foundry
11,2239,9658,2927,8678,997IC Manufacturing
5,5754,8114,1153,8564,548IC Design
21,34318,88616,34215,62717,693IC Gross Revenue
2014(f)2013201220112010
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More Moore vs. More than Moore
More Moore
More than Moore
35%
PowerConsumption BandwidthPackage Size
50%
X 8
PoP
TSV
TSV Technology
Low PowerDRAM
‧Multi-core Application Processor and DRAM Controller
3D Memory
Heterogeneous Integration
3D IC Integration
ITRI/IEK Research (2013/09)
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3D IC Advantages
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2016
Tablet1,221,84113%
Mobile Phone3,950,51443%
Laptop440,8665%
Server561,2106%
Total: 6M wafers
Source:Yole Development;IEK/ITRI (2013/09)
The Devices adopt 3D IC by 2016
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Unit : MUSD 2011 2012 2013 2014 2015 2016 CAGR
Wafer-level-underfills (Film Type) 0 0 2 8 14 28 NA
Thick resists hard mask for DRIE 4 6 10 17 25 37 56.0%
Temporary bonding / de-bonding materials 4 7 13 24 37 60 71.9%
Strippable thick resists & dry films for bumping/plating 119 129 146 176 207 256 16.6%
Sputtering targets (for PVD) 77 92 114 148 189 249 26.5%
Solder spheres 46 59 76 97 121 147 26.2%
Plating chemistries (ECD, Electroless...) 48 54 63 82 103 136 23.2%
BEOL photo-resists 1 2 4 10 15 19 80.2%
Wafer-level-molding compounds 11 15 21 29 38 51 35.9%
Capping and Spacer wafers (Glass / Silicon) 23 31 40 51 59 64 22.7%
Carrier support wafers (Glass/Silicon/Metal) 3 5 9 15 23 35 63.5%
Gas for DRIE etch 4 7 11 20 30 47 63.7%
Dielectric passivation thick resists & dry films 73 87 108 143 175 222 24.9%
Gas precursors for CVD / ALD deposition 3 5 9 17 24 34 62.5%
CMP pad & slurries 48 57 71 99 126 165 28.0%
Cleaning chemistries (strip, etch, etc⋯) 60 70 85 113 143 188 25.7%
Adhesive tapes (BG / Dicing) 24 26 30 36 42 50 15.8%
In total $548 $652 $812 $1,085 $1,431 $1,771 26.4%
☆
☆
☆
ITRI/IEK Research (2013/09)
The Market Of 3D IC Packaging Materials
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Key Processes & Materials of 2.5D/3DIC
TSV Formation• Thick Resists Hard Mask For Drie• Dielectric passivation thick resists & dry films for all WLP / TSV wafers (BCB, PI,
epoxies, SU8, PBO, WPR, Al-X, etc… ).• Sputtering Targets (used in PVD) & Plating Chemistries (ECD, Electroless)• Gas Precursors for CVD / ALD Depositions / Cleaning Chemistries• Gas For DRIE (C4F6, SF6)
Bonding / Assembly• C2W, W2W Bonding • Wafer-level-underfills• Strippable Thick Resists & Dry Films For Bumping / Plating• Wafer-Level-Molding Compounds• Solder Spheres / Balls
Interposer• BEOL Wiring Photo-
Resists• Wafer-level-underfills
Wafer ThinningTechnologies
• Adhesive Tapes (BG / Dicing)
• CMP pad & slurries• Cleaning Chemistries
Wafer Handling• Adhesive Tapes (Back
Grinding / Dicing)• Temporary bonding / de-
bonding materials• Carrier support wafers
(Glass / Silicon / Metal)
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SiP Solution for Mobile andwearable Applications
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EIC Embedded Interposer Carrier
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ITRI GIP Technology Roadmap
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Platforms of Glass substrates
Source: Yole Developpment 2013
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3DIC Technologies in ITRI
The Material needs for EICEmbedded Interposer Carrier
(Wafer Level-Underfill)
u-Ball
InterposerTSV/TGV Ball
(Build-up)
Carrier
Re-distribution layer, RDL
interposer
Fan-out Wafer Level Panel
(Build-up)
carrier
TBARelease layer
(RDL)
(TBA;Temporary Bonding Material)
Source: MCL/ITRI(2013)
• RDL -Organic dielectric/passivation material• Multi-layer dielectric material• Photosensitive isolation polymer
• Bonding Material (Temporary/Permanent)• Low CTE build-up material• Wafer-level NFU/NCF/NCA underfill
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Process flow of EIC
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Fan-out WLP
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Cost Structure of 3DIC
Factors:1. Yield2. Throughput3. Reliability
Bonding Technology-Key Issue
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Bonding Technology-finer pitch, Lower Tm.
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NCF for Wafer Bonding
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NCF RequirementsProperties NCF
Transparency Yes For alignment
Uniformity Variation ≦10% 12” wafer, t 20 um
Warpage Z 5% 12” wafer, t 50 um
Flux agent Yes Remove oxides
Filler content 40 ~ 60% Filler size = 0.3 m
Tg 100 ~ 140C
CTE 1 40 ppm and 2 130 ppm
Modulus 4 ~ 7 GPa
Curing time Fully cured after bonding Min. viscosity 150C
Void 1% C-SAM
MSL 30C / 60% RH LV3
TCT -55 ~ 125C for 1000 cycles
HTS 150C for 1000 h
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Source:Hitachi Chemical (2013)
Double the Transmission Rate of PCB Every 3 Years
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Advanced Organic Substrate Outlook
Substrate
Evolution
Substrate
Features
Bottlenecksto be
solved
1990 2000 201X
•Embedded Passive Components•Ultra fine line enabling the Direct Chip Attach
•High temperature endurance formultiple processes
•High Tg, compatible withbonding & Molding Proc. .
•Fine line capability for routing•CTE match with the siliconchip
•Embedded Active Chips•Optical & Electrical interconnection capability
•Micro E/O via hole capability
DSP
ASIC CPU
Memory
•Signal/Power Redistribution 2D System Integration 3D System Integration
•Need to enhance High Tg characteristics .•CTE matching problem is even worse for Embedded Interposers.•High K & Low K dielectric need to be improved for higher performance application.•Low cost finer line & smaller via substrate will be the challenge for future chips.•Heat dissipation & High frequency characterization need to be studied.
Future
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Low Loss Substrate Technologyfor High Speed Transmission
3) 3) High Speed Matched Impedance ViP4) (Via in PTH)
Integration 1)+2)+3) toachieve ultra speed (20Gbps) High Function Substrates
Future demand(2015~2020)BenchmarkITRI current status
DK<3.5@10GHzDK<3.4@10GHzDK<3.0@10GHz
t<40umt<40umt<10um
Df<0.005@10GHzDf<0.004@10GHzDf<0.003@10GHz
Tg: 200℃Tg: 210℃Tg: 210℃CTE: 45ppm/℃CTE: 45ppm/℃CTE: 40ppm/℃
a. Low loss/low shrinkage plugging materialsb. High aspect ratio/ high adhesion plugging process
1) TLL (Thin Low-Loss) Substrate Materials
2) USC (Ultra Speed De-Coupling Capacitors)
a. Ultra thin low loss materials
b. Low profile thin copper
a. Embedded USC high speed substrate design
b. High frequency/low characteristic impedance capacitor integration
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Low CTE DielectricsL-PAI/BMI/Filler/Glass fabric*-6Plies CCL1 CCL2 CCL3 CCL4
Filler content (wt%) 0 10 20 30
properties
Tg ( ) 265 275 258 261
Td ( @5wt% loss) 438 426 474 443
CTEX,Y
(ppm/ )27 25 11 8
CTEZ
(ppm/ )41 38 25 16
UL-94 V0 V0 V0 V0
Peel strength(lb/in)
7.1 6.8 6.8 6.5
* Glass fabric : 2116 type
Synthesis of L-PAI/BMI Resins
CO
C
CO
O
N N
b
NOO
H 2 C C H
R 1
R 2 CO
C
CO
O
Nn
+ N
O
O
C H 2
S o l v e n t
R 2 CO
C
CO
O
N N HR 1
a
C
O
C
C
O
O
NN
N OO
H 2 C C H
R 1
CO
C
CO
O
N N
c
NOO
H 2 C C H
R 3R 1
N
O
O
N H R 3R 1
N OO
C H 2 C H 2
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The global bandwidth shortage facing wireless carriers has motivated the exploration of the underutilized millimeter wave (mm-wave) frequency spectrum for future broadband cellular communication networks.
Millimeter Wave Mobile Communications for 5G
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Thin and low loss• Laminate electrical performance in mm-wave range.
For thin dielectric laminate, foil roughness will seriously affect thedielectric properties
Homogeneous concern• Glass fiber issue• X-Y and Z direction concern
Copper foil roughness vs. peel strength
Stable Dk/Df in different frequency,• temperature and humidity
Requirement of PCB Laminate for mm-Wave Applications
Source: BOARDTEK ELECTRONICS CORP.
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Most of laminates has glass fiber reinforced structure. It makes the laminate non-homogeneous
• The Dk varies a little everywhere• The impedance or signal skew will be affected• Most RF laminate keep glass content in low level
The Dk/Df in X-Y and Z-direction• Because of glass reinforcement, the Dk in X-Y direction will be higher than Z-
direction about 0.15 range• Some test method measure material for its X-Y direction and some in Z-direction• X-Y direction data is good for coplanar microstrip line, band-pass filter or coupler.
Z-direction data is good for other application
Some material has no woven glass fiber.• This kind of isotropic material has less effect for such issue
PCB Homogeneous Issue
Source: BOARDTEK ELECTRONICS CORP.
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Low Loss Laminate Inlay
Potential cost savingSolution of integrate RF and digital function into one board
Source: BOARDTEK ELECTRONICS CORP.
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High Dk material for CCL
RF Chip
Base-Band Chip
Chip 30um / Pad 15um
PI FCCL /12um
ABF
ABF
重分佈重分佈
L1
L2
L3L4
L7
L8
PI FCCL / 12um
L5L6
SONY/DuPont
High DK / 15um
High DK / 15um
Cu (6um)
Cover Layer
Cover Layer
Cover Layer
Cover Layer
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
綠漆/ 0um
綠漆/ 0um
M0
M12
Cu (6um)
M3
Cu (6um)
Hi-DK
Hi-DK
Multilayer laminate with Embedded capacitor R2R FCCL with High Dk Core
Embedded capacitor Laminate
30um Hi-dk
30um Hi-dk 30um Hi-dk
L6 L6 L6
L5
L5 L5L7
L7 L7
L8
L8 L8RO4350B
RO4350B RO4350B
Cross section of
fine line width
30um Hi-dk
30um Hi-dk 30um Hi-dk
L6 L6 L6
L5
L5 L5L7
L7 L7
L8
L8 L8RO4350B
RO4350B RO4350B
Cross section of
fine line width
High Dk/ Low loss P.P. Process
• ITRI has developed a super-high Dk substrate with a low leakage current, which can improve the reliability during practical applications. By embedding a capacitor lower than 0.1µF into a substrate can boost the embedded ratio of device and its electrical efficiency.
• The high dielectric substrate material, made by super-thin glass cloth impregnated with high-Dk/ low-loss resin, can make a thin substrate with an dielectric layer of 30µm thickness, Dk=15 and Df≤0.015@1GHz. These characteristics are fully compatible with the existing processes for PCB circuit board fabrication, and also with good workability requirements.
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GPS Module
Embedded ChipBuilt-in component
Public board 8 Layers Substrate GPS positioning
Ultra Thin SubstrateHigh Dk
Substrate material
30.9% surface area was reduced
13×16×2.3 mm313×16×1.3 mm3
Technology:Embedded Active componentsBuilt-in passive components
The substrate thickness was thinned.
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Electromagnetic wave shield composite film
The Electromagnetic wave shield composite film developed by ITRI, have great shielding process and low cost. The R2R process to manufacture.
•Porous EMI shielding Silver layer
•Shielding effectiveness >50dB
ITRI A Company B Company
Product thickness a(μm) 18~25 16~28 22
EMI shielding @1GHz (dB) 50~64 52~65 45
Surface resistance ( mΩ/□ ) <350 300 or less <300
Peel strength to PI (10mm) >3.0N 3.0N or more 4.0N
Resistance to flame(UL94) VTM-0 VTM-0 VTM-0
Heat resistance reflow-soldering Pass
(288℃;10sec×3)
Pass
(260℃soldering reflow)
Pass
(260℃soldering reflow)
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Application : • RFID Tag Conductor• Die Attach Material• Membrane Switch• Solar Cell Electrode• EMI Shielding Film
Technology Background:•Metallic-Organic-Decomposition Paste (MOD) Technology•MOD Technology
- MOD Hybrid or MOD modification technology- Low Temperature MOD sintering technology- Light Enhance or Nano Catalyst using MOD- Nano, Sub-micro Silver Powder synthesis- Metal-Semiconductor Interface
Technology Core for Low Temperature Curing Silver Paste
Core TechnologyR-Metal Metal(s)↓ + R(g)↑
Metallic-Organic Decomposition (MOD)
Sintering Modify Densification Sintering Low Fire Sintering
In-Site Coating
Functional Paste Technology
Conductor Paste Technology
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Conclusions The form-factor demands of IOT applications and wearable
electronics provide lots of new technology challenges and great opportunities for SiP technology.
The bandwidth shortage could introduce the use of new mm-wave spectrum, the low loss and cost effective substrate materials are increasingly important.
3D IC integration still facing the cost and yield challenges, need innovative architecture to help walking across the gap.
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Thank You