The 8051 Microcontoller mahmudou Unit2-PT

8/13/2019 The 8051 Microcontoller mahmudou Unit2-PT

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Unit 2: Integrated-circuit amplifiers

INTRODUCTION

This chapter begins with a brief discussion on the design philosophy of integrated

circuits, and how it differs from that of discrete circuits. Next is the comparison of MOS& BJT in terms of their parameters, characteristics and models. This is followed by

current mirror circuits and steering circuits. These circuits are realized using both MOS

and BJTs. The chapter ends with general considerations in high frequency response of

amplifiers.

IC DESIGN PHOLOSOPHY

Integrated-circuit fabrication technology poses constraints on-and provides

opportunities to- the circuit designer. Thus, while chip-area considerations dictate that

large-and even moderate-value resistors are to be avoided, constant-current sources are

readily available. Large capacitors, for signal coupling and bypass, are not to be used,

except perhaps as components external to the IC chip. Even then, the number of such

capacitors has to be kept to a minimum; otherwise the number of pin terminals and hence

its cost increase. Very small capacitors, in the picofarad and fraction of picofarad range,

however, are easy to fabricate in IC MOS technology and can be combined with MOS

amplifiers and MOS switches to realize a wide range of signal processing functions, both

analog and digital.

As a general rule, in designing IC MOS circuits, one should strive to realize as many

of the functions required as possible using MOS transistors only and, when needed,

small MOS capacitors. MOS transistor can be sized; that is, their W and L values can

be selected, to fit a wide range of requirements. To pack a larger number of devices on

the same IC chip, the trend has been to reduce the device dimensions. CMOS process

technologies capable of producing devices with a 0.1m minimum channel length are in

use. Such small devices need operate with dc voltage supplies close to 1V. While low-

voltage operation can help to reduce power dissipation, it poses lot of challenges to the

circuit designer. For example, such MOS transistors must be operated overdrive voltages

of only 0.2V or so.

The MOS-amplifier circuits that we shall study will be designed almost entirely

using MOSFETs of both polarities-that is, NMOS and PMOS.They are readily available

in CMOS process technology. As mentioned earlier, CMOS is currently the most widely

used IC technology for both analog and digital as well as combined analog and

digital(or mixed-signal)applications. Nevertheless, bipolar integrated circuit still offer

many exciting opportunities to the analog design engineer. This is especially the case for

general-purpose circuit packages, such as high-quality op amps that are intended for

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assembly on printed-circuit(pc) board. As well, bipolar circuits can provide much higher

output currents and are favoured for certain applications, such as in the automotive

industry, for their high reliability under severe environment conditions. Finally, bipolar

circuits can be combined with CMOS in innovative and exciting ways.

Introduction to MOSFET Scaling

In 1965, G.E. Moore predicted that the number of transistors in ICs would double

after every two years. This prediction has come true and todays Pentium processor

accommodates approximately 14.2million transistors in 1.7 x 2 cm2.The only way to

assemble a large number of transistors in given silicon area is to reduce the size of the

transistor. The process of reducing vertical and horizontal dimensions of MOSFETs is

called scaling. In order to meet Moores law, the channel length (L) and width (W) of the

MOSFET are reduced by a factor 0.7. If we reduce by a factor of 0.7, the area of the

MOSFET, which is W X L, reduces by half. Hence, in the given area we can assemble

double the number of transistors.

Scaling is defined as the process of reducing the horizontal and vertical

dimensions of a MOS device by some scaling factor S, which is greater than 1. Thus, the

scaled device is obtained by simply dividing the key dimensions of the MOSFET such as

channel length (L), channel width (W),oxide thickness(tox), and junction depth (Xj),by

scaling factor S. MOSFET scaling offers several benefits such as increased component

density, increase speed, reduction in power consumption, and cost per chip.

Two type of schemes commonly used for MOSFET scaling are constant voltage scaling

are constant-field scaling.

Constant Field Scaling: In constant-field scaling, the MOSFET dimensions as well

as supply voltages are scaled by the same scaling factor S, greater than 1.The scaling of

supply and terminal voltage maintains the same electric field as that of original device;

hence such scaling is termed constant-field scaling. Such scaling is also called full

scaling, as the geometric dimensions and supply voltages are scaled simultaneously. In

order to maintain charge and electric field relationship, the doping densities are scaled by

scaling factor S. Constant scaling offers benefits such as increased component density,

increased speed, decreased cost, etc. The impact of constant-field scaling on the physical

parameters of the MOSFET is summarized in below table. Let MOSFET current beforescaling be given by

Idsn Cox(VGS-Vt)2

where Vtis threshold voltage. After constant field scaling, the drain current becomes,

2

Idsn S Cox(VGS/S- Vt/S)2

Ids= Ids/S


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Hence, the drain current decreases by scaling factor S. Now, before scaling, delay is

given by

Where C is the load capacitance, V is supply voltage, and I is the charging current. we

know that in constant field scaling, C,V and I decrease by a factor of S; hence, the delay

after scaling is given by

The impact of constant-field scaling on the physical parameters of the MOSFET is

summarized in the table below:

Parameters Before Scaling After Scaling

Channel width W W/S

Channel length L L/S

Area WL WL/S2

Oxide Thickness Tox Tox/S

Oxide capacitance Cox SCox

Threshold voltage VTO VTO

Supply Voltage VDD VDD/S

Gate Voltage VGS VGS/S

Drain Voltage VDS VDS/S

Doping density NA NAS

Constant-Voltage Scaling: In constant-voltage scaling, the geometrical dimensions of

the MOSFET are scaled by the scaling factor S while the supply and terminal voltage

are kept constant. In addition to this, the densities are increased by the factor of S2 to

maintain the charge electric field relationship. Such scaling is also known as partial

scaling because scaling applied only physical dimensions and not to voltages. In this

scheme, all voltages are kept constant to maintain the logic level as that of the original

device to provide a compatible interface with peripheral circuitry such as I/O devices.

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=

= = /S (1)


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The impact of constant-voltage scaling on the physical parameters of the MOSFET is

summarized in the table below:

Parameters Before Scaling After Scaling

Channel width W W/S

Channel length L L/S

Area WL WL/S2

Oxide Thickness Tox Tox/S

Oxide capacitance Cox S Cox

Threshold voltage Vt Vt

Supply Voltage VDD VDD

Gate Voltage VGS VGS

Drain Voltage VDS VDS

Doping density NA NAS2

From Eq.(1) it is clear that in constant-field-scaling, delay decreases by a factor S, while

in constant-voltage scaling, delay decreases by the factor S2. Hence, in constant-field

scaling improvement in delay is less as compared to constant-voltage scaling. However,

power in constant-field scaling is less and power density before and after the scaling

remains the same. Thus with the slightest penalty in delay, constant-field scaling offers

several advantages compared to constant-voltage scaling. For example, as physical

dimensions and voltages are scaled simultaneously by the same factor the electric fields

as well as the power density before and after scaling remains the same. Therefore,

constant-field scaling improves the reliability of the scaled device, circuits and systems as

compared to constant-voltage scaling.

Impact of constant-voltage scaling on electrical properties of MOSFET. Let CGSbe

the total gate oxide capacitance before scaling given by

Gate capacitance after scaling is given by

Thus the total gate capacitance after scaling decreases by a factor of S. Similarly, we

can also show that other parasitic capacitances as well as interconnect capacitances will

decrease by scaling factor S. This is a very important result of scaling and applicable to

both constant-voltage and constant-field scaling. Let the MOSFET drain current before

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CGS= COXWL= (ox/Tox)WL

CGS= COX(W/S)(L/S) =[ox/(Tox/S)](W/S)(L/S) = CGS/S ..(2)


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scaling be Ids, which is given by

After scaling, the drain current becomes

Thus, in constant-voltage scaling, drain current increases by a factor of S. The most

important parameter used to compare MOSFET performance is delay, which is given by

CV/I , where is C is the load capacitance, V is the supply voltage and I , the charging

and discharging current. From eqn(2) and (3) , it is clear that in constant-voltage scaling

the total capacitance decreases by factor S, while the current is increased by the same

factor S. This decreases the delay of scaled device by S2. In constant voltage scaling,

the power dissipation , which is a product of current and voltage, increases by a factorof S. Similarly the power density, which is defined as the power per unit area increases

by a factor of S3.In addition to the increased power density, constant-voltage scaling

also increases the internal peak electric-fields. The combined effect of increased power

density and electric-field eventually leads to device reliability problems, such as oxide

break-down and electro-migration. Hence constant field scaling is preferred to constant-

voltage scaling.

Short-Channel Effects and Recent Scaling Trends: We have seen that to achieve

higher integration density and performance, channel lengths of MOSFETs have been

continuously reduced as shown in Table 1. However, in short-channel MOSFETs, suchbenefits are obtained at the cost of increased short-channel effects, such as the following:

1. Drain induced barrier lowering (DIBL)

2. Punch through effect

3. Threshold voltage roll-off

4. Gate tunneling currents

5. Hot carrier effect

Drain induced barrier lowering (DIBL) A MOSFET is considered a short-channel

device when its channel length is of the order of the depletion widths of the source/drain

junctions. In a long-channel MOSFET. when gate voltage is sufficiently smaller than

threshold voltage, electrons from the source region are prevented from entering into the

channel due to the potential barrier of the source-channel junction. However, in short-

channel devices, this barrier is lowered by the drain electric field, which eventually

allows electron flow into the channel. This flow of electrons gives rise to the drain

current, which in turn gives rise to sub-threshold leakage current and static leakage

power. In short-channel devices, DIBL effect is controlled by increasing the channel

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IdsnCox(VGS- Vt)2

IdsnSCox(VGS- Vt)2 = S Ids .(3)


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doping; however, such increased doping will degrade the carrier mobility and, hence, the

drain current.

Punch through effectWe know that in short-channel devices, channel lengths are of the

order of the source/drain depiction region thickness. When drain voltage is increased, thedrain depletion region touches the source depletion region. This condition is known as the

punch through effect, in which gate voltage loses the control of the channel and the drain

current increases sharply. The punch through effect is reduced by using thin gate oxide

and high channel doping.

Threshold voltage roll-offFor MOSFETs, the threshold voltage expression is derived

with the assumption that the depletion bulk charge in the channel region is due to gate

voltage. This assumption is valid only for long-channel devices, as the contribution of

source/drain depletion charge to channel depletion charge is negligible. However, as

channel lengths are reduced, the contribution of source/drain depletion charge increases;hence, the expression for threshold voltage predicts higher threshold voltage than the

actual value. Therefore, in short-channel devices, as channel lengths are reduced, the

contribution of source/drain depletion charge to total charge in the channel region

increases and, hence, the threshold voltage decreases as shown in Fig. 1. The reduction in

threshold voltage eventually leads to higher sub-threshold leakage currents, which results

in increased static power dissipation.

0.05 0.1 0.2 0.5 1 urn 2 urn

5 um 10 urn

Channel length

FIGURE 1 : Threshold voltage roll-off.

Gate tunneling currentsshort-channel MOSFETs require very thin gate oxide to control

the various short-channel effects, as mentioned earlier. For example, MOSFETs with a

channel length of 65 nm require gate oxide thickness of about 1.2 nm. Such a thin gate

oxide consists of only four to five atomic layers and electrons can easily tunnel through

the thin oxide. The direct tunneling of electrons across thin gate oxide eventually leads

to gate leakage current, which also increases the power dissipation. Hence, tunneling

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currents limit the further scaling of oxide thickness. To overcome this problem, the

conventional silicon dioxide is replaced with high dielectric constant (high-K) materials

such as silicon nitride, hafnium oxide, etc. The high-K material allows higher physical

thickness than the conventional silicon dioxide thickness for the same capacitance.

Therefore, high-K materials decrease gate tunneling currents and allow further scaling ofMOS transistors.

Hot carrier effect The reduction of MOSFET dimensions to achieve higher integration

density and performance increases lateral and vertical electric fields in the device. The

increased electric field increases the velocity of electrons and holes and, hence, their

kinetic energy. Electrons and holes with high kinetic energy are known as hot electrons

and hot holes, respectively. Due to high vertical electric field, hot electrons and holes

strike or penetrate into the oxide and get trapped at the Si-Si02interface as well as in the

oxide. These trapped carriers modulate the threshold voltage of MOSFETs and degrade

the reliability.

COMPARISON OF THE MOSFET AND THE BJT

In this section we present a comparison of the characteristics of the two major electronic

devices: the MOSFET and the BJT. To facilitate this comparison, typical values for the

important parameters of the two devices are first presented.

Typical Values of MOSFET Parameters

Typical values for the important parameters of NMOS and PMOS transistors fabricatedin a number of CMOS processes are shown in Table. Each process is characterized by

the minimum allowed channel length, Lmin,thus, for example, in a 0.18-m process, the

smallest transistor has a channel length L = 0.18 m. The technologies presented in

Table are in descending order of channel length, with that having the shortest channel

length being the most modern. Although the 0.8-m process is now obsolete, its data are

included to show trends in the values of various parameters. It should also be mentioned

that although Table stops at the 0.18-m process, at the time of this writing (2003),

a 0.13-m fabrication process is commercially available and a 0.09-m process is in

the advanced stages of development. The 0.18-m process, however, is currently the

most popular and the one for which data are widely available. The trends shown help

us to illustrate design trade-offs as well as enable us to work out design examples and

problems with parameter values that are as realistic as possible.

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TABLE 3 : Typical Values of CMOS Device Parameters

As indicated in Table-3, the trend has been to reduce the minimum allowable channel

length. This trend has been motivated by the desire to pack more transistors on a chip as

well as to operate at higher speeds or, in analog terms, over wider bandwidths.

Observe that the oxide thickness, tox, scales down with the channel length, reaching 4

nm for the 0.18-m process. Since the oxide capacitance Cox is inversely proportional

to tox, we see that Cox increases as the technology scales down. The surface mobility

decreases as the technology minimum-feature size is decreased, and pdecreases much

faster thann. As a result, the ratio of ptonhas been decreasing with each generation

of technology, falling from about 0.5 for older technologies to 0.2 or so for the newer

ones. Despite the reduction of ) nandp, the transconductance parameters k'n=nCox

and k'p= nCoxhave been steadily increasing. As a result, modern short-channel devices

achieve required levels of bias currents at lower overdrive voltages. As well, they achieve

higher transconductanc, a major advantage.

Although the magnitudes of the threshold voltages Vtn and Vtp have been decreasing

withLmiafrom about 0.7-0.8 V to 0.4-0.5 V, the reduction has not been as large as that

of the power supply VDD. The latter has been reduced dramatically, from 5 V for older

technologies to 1.8 V for the 0.18-m process. This reduction has been necessitated by

die need to keep the electric fields in the smaller devices from reaching very high values.

Another reason for reducing VDD is to keep power dissipation as low as possible given

that the IC chip now has a much larger number of transistors.1

The fact that in modern short-channel CMOS processes |V t| has become a much larger

proportion of the power-supply voltage poses a serious challenge to the circuit design

engineer. Recalling that | VGS| = | Vt| +|Vov|, where Vov is the overdrive voltage, to keep

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| VGS| reasonably small, |Vov| for modern technologies is usually in the range of 0.2 V to

0.3 V. To appreciate this point further, recall that to operate a MOSFET in the saturation

region. |VDS| must exceed | Vov|; thus, to be able to have a number of devices stacked

between the power-supply rails in a regime in which VDDis only 1.8 V or lower, we need

to keep |V0V| as low as possible. We will shortly see, however, that operating at a low |Vov| has some drawbacks.

Another significant though undesirable feature of modern submicron CMOS technologies

is that the channel length modulation effect is very pronounced. As a result of V'A

steadily decreasing, which combined with the decreasing values of L has caused the Early

voltage V A = V'A L to become very small. Correspondingly, short-channel MOSFETs

exhibit low output resistances.

We know that two major MOSFET capacitances are Cgs and Cgd. While Cgs has an

overlap component, Cgd is entirely an overlap capacitance. Both Cgd and the overlapcomponent of Cgsare almost equal and are denoted Cov. The last line of Table provides

the value Covper micron of gate width. Although the normalized Covhas been staying

more or less constant with the reduction in Lmin, we will shortly see that the shorter

devices exhibit much higher operating speeds and wider amplifier bandwidths than the

longer devices. Specifically, we will, for example, see that fT for a 0.25-m NMOS

transistor can be as high as 10 GHz.

Typical Values of IC BJT Parameters

Table below provides typical values of major parameters that characterize integrated-circuit bipolar transistors. Data are provided for devices fabricated in two different

processes: the standard, old process, known as the "high-voltage process"; and an

advanced process, referred to as a "low-voltage process." For each process we show the

parameters of the standard npn transistor and those of a special type of pnp transistor

known as a lateral (as opposed to vertical as in the npn case) pnp. In this regard we

should mention that a major drawback of standard bipolar integrated-circuit fabrication

processes has been the lack ofpnp transistors of a quality equal to that of the npn devices.

Rather, there are a number of pnp implementations for which the lateral pnp is the most

economical to fabricate. Unfortunately, however, as should be evident from Table the

TABLE -4 : Typical Parameter Values for BJTs1

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lateral pnp has characteristics that are much inferior to those of the npn.Note in particular

the lower value of and the much larger value of the forward transit time F that

determines the emitter-base diffusion capacitance Cde and, hence, the transistor speedof operation. The data in Table can be used to show that the unity-gain frequency of the

lateral pnp is two orders of magnitude lower than that of the npn transistor fabricated

in the same process. Another important difference between the lateral pnp and the

corresponding npn transistor is the value of collector current at which their values reach

their maximums: For the high-voltage process, for example, this current is in the tens of

microamperes range for thepnp and in the milliampere range for the npn. On the positive

side, the problem of the lack of high-quality pnp transistors has spurred analog circuit

designers to come up with highly innovative circuit topologies that either minimize the

use of pnp transistors or minimize the dependence of circuit performance on that of the

pnp.

The dramatic reduction in device size achieved in the advanced low-voltage process

should be evident from Table. As a result, the scale current Isalso has been reduced by

about three orders of magnitude. Here we should note that the base width, W B, achieved

in the advanced process is of the order of 0.1 m, as compared to a few microns in the

standard high-voltage process. Note also the dramatic increase in speed; for the low-

voltage npn transistor, F= 10 ps as opposed to 0.35 ns in the high-voltage process. As

a result, fTfor the modem npn transistor is 10 GHz to 25 GHz, as compared to the 400

MHz to 600 MHz achieved in the high-voltage process. Although the Early voltage,

VA, for the modern process is lower than its value in the old high-voltage process, it is

still reasonably high at 35 V. Another feature of the advanced processand one that is

not obvious from Tableis that for the npn peaks at a collector current of 50 A or

so. Finally, note that as the name implies, npn transistors fabricated in the low-voltage

process break down at collector-emitter voltages of 8 V, as compared to 50 V or so

for the high-voltage process. Thus, while circuits designed with standard high-voltage

process utilize power supplies of 15 V (e.g., in commercially available op amps of the

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741 type), the total power-supply voltage utilized with modern bipolar devices is 5 V (or

even 3.3 V to achieve compatibility with some of the submicron CMOS processes).

Comparison of Important Characteristics

Table -5 provides a compilation of the important characteristics of the NMOS and the

npn transistors. The material is presented in a manner that facilitates comparison. It is to

be noted that the PMOS and thepnp transistors can be compared in a similar way.

TABLE 5 Comparison of the MOSFET and the BJT

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Operating Conditions At the outset, we shall use active mode or active region to

denote both the active mode of operation of the BJT and the saturation-mode of operation

of the MOSFET.

The conditions for operating in the active mode are very similar for the two devices: The

explicit threshold Vt of the MOSFET has VBEon as its implicit counterpart in the BJT.

Furthermore, for modern processes, VBEonand Vtare almost equal.

Also, pinching off the channel of the MOSFET at the drain end is very similar to reverse

biasing the CBJ of the BJT. Note, however, that the asymmetry of the BJT resultsin VBCon and VBEon being unequal, while in the symmetrical MOSFET the operative

threshold voltages at the source and the drain ends of the channel are identical (V t).

Finally, for both the MOSFET and the BJT to operate in the active mode, the voltage

across the device (vDS, vCE) must be at least 0.2 V to 0.3 V.

Current-Voltage Characteristics The square-law control characteristic, iD-vGS, in the

MOSFET should be contrasted with the exponential control characteristic, ic,vBE,

of the BJT. Obviously, the latter is a much more sensitive relationship, with the result

that iccan vary over a very wide range (five decades or more) within the same BJT. In

the MOSFET, the range of iD achieved in the same device is much more limited. Toappreciate this point further, consider the parabolic relationship between iDand vov, and

recall from our discussion above that vovis usually kept in a narrow range (0.2 V to 0.4

V).

Next we consider the effect of the device dimensions on its current. For the bipolar

transistor the control parameter is the area of the emitter-base junction (EBJ), AEwhich

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(a) ID= (nCox) (v2ov

Substituting ID= 100A, W/L = 10, and, from data Table,nC0x= 387 A/V2, VT=0.48V

results in

100= x 387 x 10 x V2ov,

Vov= 0.23 V

Thus,

VGS= Vtn+ Vov= 0.48 + 0.23 = 0.71 V

(b)Ic= IS eVBE / Vr

SubstitutingIc= 100 A and, from Table, Is= 6 x 10-18A gives,

VBE= 0.025 ln = 0.76 V

Low-Frequency Small-Signal Models The low-frequency models for the two devices

are very similar except, of course, for the finite base current (finite ) of the BJT, which

gives rise to r in the hybrid model and to the unequal currents in the emitter and

collector in the T models (a < 1). Here it is interesting to note that the low-frequency

small-signal models become identical if one thinks of the MOSFET as a BJT with =

( = 1).

For both devices, the hybrid- model indicates that the open-circuit voltage gainobtained from gate to drain (base to collector) with the source (emitter) grounded is -gmr0.

It follows thatgmr0is the maximum gain available from a single transistor of either type.

This important transistor parameter is given the name intrinsic gainand is denotedA0.

Although not included in the MOSFET low-frequency model shown in Table, the

body effect can have a significant implication for the operation of the MOSFET as an

amplifier. In simple terms, if the body (substrate) is not connected to the source, it can

act as a second gate for the MOSFET. The voltage signal that develops between the body

and the source, vbs, gives rise to a drain current component gmb = vbs, where the body

transconductancegmbis proportional to gm; that is, gmb= gm, where the factor is inthe range of 0.1 to 0.2. We shall take the body effect into account in the study of IC MOS

amplifiers in the succeeding sections. The body effect has no counterpart in the BJT.

The Transconductance For the BJT, the transconductance gmdepends only on the dc

collector currentIc. (Recall that VTis a physical constant =0.025 V at room temperature).

It is interesting to observe that gmdoes not depend on the geometry of the BJT, and its

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dependence on the EBJ area is only through the effect of the area on the total collector

current Ic- Similarly, the dependence of gm on VBE is only through the fact that VBE

determines the total current in the collector. By contrast, gmof the MOSFET depends on

ID, Vov, and W/L. Therefore, we use three different (but equivalent) formulas to expressgm

of the MOSFET.

The first formula given in Table for the MOSFET's gm is the most directly comparable

with the formula for the BJT. It indicates that for the same operating current, gmof the

MOSFET is much smaller than that of the BJT. This is because Vov/2 is in the range of

0.1 V to 0.2 V, which is four to eight times the corresponding term in the BJT's formula,

namely VT.

The second formula for the MOSFET's gm indicates that for a given device (i.e., given

W/L),gmis proportional to Vov. Thus a higher gmis obtained by operating the MOSFET

at a higher overdrive voltage. However, we should recall the limitations imposed onthe magnitude of Vovby the limited value of VDD. Put differently, the need to obtain a

reasonably high gmconstrains the designer's interest in reducing Vov.

The thirdgmformula shows that for a given transistor (i.e., given W/L), gmis proportional

to . This should be contrasted with the bipolar case, where gmis directly proportional to

IC.

Output Resistance The output resistance for both devices is determined by similar

formulas, with robeing the ratio of VA to the bias current (ID or Ic). Thus, for both

transistors, ro is inversely proportional to the bias current. The difference in nature andmagnitude of VAbetween the two devices has already been discussed.

Intrinsic Gain The intrinsic gain A0 of the BJT is the ratio of VA which is solely a

process parameter (35 V to 130 V), and VT, which is a physical parameter (0.025 V at

room temperature). Thus A0of a BJT is independent of the device junction area and of

the operating current, and its value ranges from 1000 V/V to 5000 V/V. The situation in

the MOSFET ' is very different: Table provides three different (but equivalent) formulas

for expressing the MOSFET's intrinsic gain. The first formula is the one most directly

comparable to that of the BJT. Here, however, we note the following:

1.The quantity in the denominator is Vov/2. which is a design parameter, and althoughit is becoming smaller in designs using short-channel technologies, it is still much

larger than VT.

2.The numerator quantity VAis both process- and device-dependent, and its value has

been steadily decreasing.

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As a result, the intrinsic gain realized in a single MOSFET amplifier stage fabricated

in a modern short-channel technology is only 20 V/V to 40 V/V, almost two orders of

magnitude lower than that for a BJT.

The third formula given for A0 in Table points out a very interesting fact: For a givenprocess technology (VA and n Cax) and a given device (W/L), the intrinsic gain is

inversely proportional to . This is illustrated in Fig below which shows a typical plot

of A0versus the bias current ID. It is clear that the gain increases as the bias current is

lowered. The gain, however, levels off at very low currents. This is because the MOSFET

enters the sub threshold region of operation, where it becomes very much like a BJT with

an exponential current-voltage characteristic. The intrinsic gain then becomes constant,

just as in BJT. Although a higher gain is achieved at lower bias currents, the price paid is

a lowergmand less ability to drive capacitive loads and thus a decrease in bandwidth.

FIGURE2: The intrinsic gain of the MOSFET versus bias current ID. Outside the

subthreshold region, this is a plot of for the Case : nCox= 20 A/

V2. V'A= 20 V/m,L = 2m, and W = 20m

EXAMPLE

It is required to compare the values of gm, input resistance at the gate (base). r0, andA0

for an NMOS transistor fabricated in the 0.25-m technology specified in Table and an

npn transistor fabricated in the low-voltage technology specified in Table. Assume both

devices are operating at a drain (collector) current of 100 A. For the MOSFET, let L=

0.4 m and W = 4 m, and specify the required Vov.

Solution

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For the NMOS transistor,

High-Frequency Operation The simplified high-frequency equivalent circuits for the

MOSFET and the BJT are very similar, and so are the formulas for determining their

unity-gain frequency (also called transition frequency)fT. Recall thatfTis a measure of

the intrinsicbandwidth of the transistor itself and does not take into account the effectsof capacitive loads. We shall address the issue of capacitive loads shortly. For the time

being, note the striking similarity between the approximate formulas given in Table 6.6

for the value of fT of the two devices. In both cases fT is inversely proportional to the

square of the critical dimension of the device: the channel length for the MOSFET and

the base width for the BJT. These formulas also clearly indicate that shorter-channel

MOSFETs" and narrower-base BJTs are inherently capable of a wider bandwidth of

operation. It is also important to note that while for the BJT the approximate expression

for fT indicates that it is entirely process determined, the corresponding expression

for the MOSFET shows that fT is proportional to the overdrive voltage Vov. Thus we

have conflicting requirements on Vov: While a higher low-frequency gain is achievedby operating at a low Vov, wider bandwidth requires an increase in Vov. Therefore the

selection of a value for Vov involves, among \ other considerations, a trade-off between

gain and bandwidth.

For npn transistors fabricated in the modern low-voltage process, fTis in the range of 10

GHz to 20 GHz as compared to the 400 MHz to 600 MHz obtained with the standard

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high-voltage process. In the MOS case, NMOS transistors fabricated in a modern

submicron technology, such as the 0.18-m process, achieve fTvalues in the range of 5

GHz to 15 GHz.

Before leaving the subject of high-frequency operation, let's look into the effect of acapacitive load on the bandwidth of the common-source (common-emitter) amplifier. For

this purpose we shall assume that the frequencies of interest are much lower thanfTof the

transistor. Hence we shall not take the transistor capacitances into account. Figure shows

a common-source amplifier with a capacitive load CL. The voltage gain from gate to drain

can be found as follows:

... (4)

Thus the gain has, as expected, a low-frequency value of gmr0 = A0 and a frequency

response of the single-time-constant (STC) low-pass type with a break (pole) frequency

at

Obviously this pole is formed by ro and CL. A sketch of the magnitude of gain versus

frequency is shown in Fig. We observe that the gain crosses the 0-dB line at frequencywt,

20

(5)


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FIGURE3 Frequency response of a CS amplifier loaded with a capacitance CLand fed with an ideal

voltage source. It is assumed that the transistor is operating at frequencies much lower than fT, and

thus the internal capacitances are not taken into account.

Thus

Wt =

That is, the unity-gain frequency or, equivalently, the gain-bandwidth product wt,

is the ratio gmand CL. We thus clearly see that for a given capacitive load CL, a larger

gain-bandwidth product is achieved by operating the MOSFET at a higher gm. Identical

analysis and conclusions apply to the case of the BJT. In each case, bandwidth increases

as bias current is increased.

Design ParametersFor the BJT there are three design parametersIc, VBE, and Is (or,

equivalently, the area of the emitter-base junction)of which any two can be selected

by designer. However, sinceIcis exponentially related to VBEand is very sensitive to the

value of VBE(VBEchanges by only 60 mV for a factor of 10 change in Ic),Icis much more

than VBEas a design parameter. As mentioned earlier, the utility of the EBJ area as a

21


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design parameter is rather limited because of the narrow range over whichAEcan vary. It

follows that for the BJT there is only one effective design parameter: the collector current

1c. Finally, note that we have not considered VCEto be a design parameter, since its effect

onIc is only secondary. Of course, VCE affects the output signal swing.

For the MOSFET there are four design parametersID, Vov, L, and Wof which any

three can be selected by the designer. For analog circuit applications the trade-off

in selecting a value for L is between the higher speeds of operation (wider amplifier

bandwidth) obtained at lower values of L and the higher intrinsic gain obtained at larger

values ofL. Usually one selects anL of about 25% to 50% greater than Lmin.

The second design parameter is Vov. We have already made numerous remarks about ,

the effect of the value of Vovon performance. Usually, for submicron technologies, Vovis

selected in the range of 0.2 V to 0.4 V.

Once values for L and Vov are selected, the designer is left with the selection of the

value ofIDor W (or, equivalently, W/L). For a given process and for the selected values

of L and Vov, lD is proportional to W/L. It is important to note that the choice of IDor,

equivalently, of W/L has no bearing on the value of intrinsic gain A0and the transition

frequencyfT. However, it affects the value of gmand hence the gain-bandwidth product.

Figure illustrates this point by showing how the gain of a common-source amplifier

operated at a constant Vov varies with ID (or, equivalently, W/L). Note that while the

dc gain remains unchanged, increasing W/L and, correspondingly, ID increases the

bandwidth, proportionally. This, however, assumes that the load capacitance CL is not

affected by the device size, an assumption that may not be entirely justified in some

cases.

22

Figure4 IncreasingID

or W/Lincreases the bandwidth of a MOSFET amplifier loaded by a constant ca


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Combining MOS and Bipolar Transistors-BiCMOS Circuits

It is evident that the BJT has the advantage over the MOSFET of a much higher

transconductance (gm) at the same value of dc bias current. Thus, in addition to realizing

much higher voltage gains per amplifier stage, bipolar transistor amplifiers have superior

high-frequency performance compared to their MOS counterparts.

On the other hand, the practically infinite input resistance at the gate of a MOSFET

makes it possible to design amplifiers with extremely high input resistances and an

almost zero input bias current. Also, the MOSFET provides an excellent implementation

of a switch, a fact that has made CMOS technology capable of realizing a host of analog

circuit functions that are not possible with bipolar transistors.

It can thus be seen that each of the two transistor types has its own distinct and unique

advantages: Bipolar technology has been extremely useful in the design of very-high-

quality general-purpose circuit building blocks, such as op amps. On the other hand,

CMOS, with its very high packing density and its suitability for both digital and analog

circuits, has become the technology of choice for the implementation of very-large-scale

integrated circuits. Nevertheless, the performance of CMOS circuits can be improved if

the designer has available (on the same chip) bipolar transistors that can be employed in

functions that require their highgmand excellent current-driving capability. A technologythat allows the fabrication of high-quality bipolar transistors on the same chip as CMOS

circuits called BiCMOS.

Validity of the Square-Law MOSFET Model

We conclude this section with a comment on the validity of the simple square-law model

we have been using to describe the operation of the MOS transistor. While this simple

model works well for devices with relatively long channels (>1 m) it does not provide

an accurate representation of the operation of short-channel devices. This is because a

number of physical phenomena come into play in these submicron devices, resulting in

what are called short-channel effects. Although the study of short-channel effects is

beyond the scope, it should be mentioned that MOSFET models have been developed

that take these effects into account. However, they are understandably quite complex and

do not lend themselves to hand analysis of the type needed to develop insight into circuit

operation. Rather, these models are suitable for computer simulation and are indeed used

in SPICE. For quick, manual analysis, however, we will continue to use the square-law

23


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model which is the basis for the comparison in Table above.

IC BIASING-CURRENT SOURCES, CURRENT MIRRORS & CURRENT-

STEERING CIRCUITS

Biasing in integrated-circuit design is based on the use of constant-current sources. On

an IC chip with a number of amplifier stages, a constant dc current (called a reference

current) is generated at one location and is then replicated at various other locations

for biasing the various amplifier stages through a process known as current steering.

This approach has the advantage that the effort expended on generating a predictable and

stable reference current, usually utilizing a precision resistor external to the chip, need

not be repeated for every amplifier stage. Furthermore, the bias currents of the various

stages track each other in case of changes in power-supply voltage or in temperature.

In this section we study circuit building blocks and techniques employed in the biasdesign of IC amplifiers. These circuits are also utilized as amplifier load elements.

The Basic MOSFET Current Source

Figure 5 shows the circuit of a simple MOS constant-current source. The heart of the

circuit is transistor Q1 the drain of which is shorted to its gate, thereby forcing it to

operate in the saturation mode with

(6)

where channel-length modulation is neglected. The drain current of Q1 is supplied by

VDDthrough resistorR, which in most cases would be outside the IC chip. Since the gate

currents are zero,

.. (7)

where the current throughR is considered to be the reference current of the current source

and is denotedIREF. Equations (6) and (7) can be used to determine the value required for

R.

24


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FIGURE 5 Circuit for a basic MOSFET constant-current source.

Now consider transistor Q2: It has the same VGS as Q1; thus, if we assume that it is

operating in saturation, its drain current, which is the output current lo of the current

source, will be

where we have neglected channel-length modulation. the above two equations enable usto relate the output currentIoto the reference current IRFFas follows:

This is a simple and attractive relationship: The special connection of Q1and Q2provides

an output current I0that is related to the reference current IREFby the ratio of the aspect

ratios of the transistors. In other words, the relationship between Io and IREF is solely

determined by the geometries of the transistors. In the special case of identical transistors,

I0=

IREF, and the circuit simply replicates or mirrors the reference current in the output

terminal. This has given the circuit composed of Q1, and Q2the name current mirror, a

name that is used irrespective of the ratio of device dimensions.

25

...(8)


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increased above this value,I0will increase according to the incremental output resistance

ro2of Q2. This is illustrated in Fig. 7, which shows I0versus V0. Observe that since Q2

is operating at a constant VGS(determined by passing IREF through the matched device

Q1), the curve in Fig. 7 is simply the iD-vDScharacteristic curve of Q2for VGSequal to the

particular value VGS.

In summary, the current source of Fig. 5 and the current mirror of Fig. 6 have a finite

(.13

output resistance R0,

where I0 is given by Eq. (8) and VA2 is the Early voltage of Q2. Also, recall that for

a given process technology, VA is proportional to the transistor channel length; thus,

to obtain high output-resistance values, current sources are usually designed using

transistors with relatively long channels. Finally, note that we can express the current I0

as

27

.(11)

.(12)


28/48


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MOS Current Steering Circuits

Once a constant current is generated, it can be replicated to provide DC bias currents

for the various amplifier stages in the IC. Current mirrors can obviously be used to

implement this current steering function. Figure 8 shows a simple current steeringcircuit.

FIGURE 8 A current-steering circuit.

Here Q1together withR determine the reference current IREF. Transistors Q1, Q2, and Q3

form a two-output current mirror,

To ensure operation in the saturation region, the voltages at the drains of Q2and Q3are

constrained as follows:

VD2,VD3 -VSS+VGS1-Vtn

VD2,VD3 -VSS+Vov1

29

.(13)

.(14)

.(16)

.(15)


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where Vov1is the overdrive voltage at which Q1, Q2, and Q3are operating. In other words,

the drains of Q2and (Q3will have to remain higher than - V ssby at least the overdrive

voltage, which is usually a few tenths of a volt.

Continuing our discussion of the circuit in Fig. 8, we see that current I3is fed to the input

side of a current mirror formed by PMOS transistors Q4and Qs. This mirror provides

Where I4= I3. To Keep Q5in saturation, its drain voltage should be

where V0V5is the overdrive voltage at which Q5is operating.

Finally, an important point to note is that while Q2pulls its current I2from a load (not

shown in Fig. 8), Q5 pushes its current I5 into a load (not shown in Fig. 8). Thus Q5

is appropriately called a current source, whereas Q2 should more properly be called a

current sink. In an IC, both current sources and current sinks are usually needed.

BJT Circuits

The basic BJT current mirror is shown in Fig. 9. It works in a fashion very similar to that

of the MOS mirror. However, there are two important differences: First, the nonzero base

current of the BJT (or, equivalently, the finite ) causes an error in the current transfer

ratio of the bipolar mirror. Second, the current transfer ratio is determined by the relative

areas of the emitter-base junctions of Q1, and Q2.

Let us first consider the case when is sufficiently high so that we can neglect the base

currents. The reference current IRFF is passed through the diode-connected transistor Q1

and thus establishes a corresponding voltage VBE, which in turn is applied between baseand emitter of Q2.Now, if Q2is matched to Q1or, more specifically, if the EBJ area of Q2

is the same as that of Q1and thus Q2has the same scale currentIsas Q1, then the collector

current of Q2will be equal to that of Q1; that is,

(6.21)

Io= IREF

30

.(17)

. (18)

. (19)


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For this to happen, however, Q2must be operating in the active mode, which in turn is

achieved so long as the collector voltage V0is 0.3 V or so higher than that of the emitter.

To obtain a current transfer ratio other than unity, say m, we simply arrange that the area

of the EBJ of Q2is m times that of Q1. In this case,

Io= m IREF

Figure 9 : The basic BJT Current mirror

31

. (20)


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Where VA2 and ro2 are the Early voltage and the output resistance, respectively, of

Q2. Thus even if we neglect the error due to finite , the output current I0 will be at

its nominal value only when Q2has the same VCEas Q1, namely at V0= VBE. As V0 is

increased, I0 will correspondingly increase. Taking both the finite and the finite R0

into account, we can express the output current of a BJT mirror with a nominal current

transfer ratio m as

We may observe, the error term due to the Early effect reduces to zero for V0= VBE.

EXERCISE

Consider a BJT current mirror with a nominal current transfer ratio of unity. Let the

transistors have Is= 10-15A, = 100, and VA= 100 V. For IREF= 1 mA, findI0when V0

= 5V. Also, find the output resistance.

Ans. 1.02 mA: 100 k

A Simple Current Source Just in the same way as MOS, the basic BJT current mirror

can be used to implement a simple current source, as shown in Fig. 11. Here the reference

current is

where VBE is the base-emitter voltage corresponding to the desired value of output

currentI0,

The output resistance of this current source is r0of Q2,

33

. (25)

. (26)

. (27)

. (28)


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To generate a dc current twice the value of IREF, TWO transistors, Q5 and Q6, each of

which is matched to Q1, are connected in parallel, and the combination forms a mirrorwith Q1. Thus I3= 2IREF.

The parallel combination of Q5 and Q6 is equivalent to a transistor with an EBJ area

double of Q1which is actually done when this circuit is fabricated in IC form.

Q4forms a mirror with Q2; so Q4provides a constant current I2, which equals IREF. If Q3

sources its current to parts of the circuit whose voltage should not exceed Vcc- 0.3V. Q4

sinks its current from parts of the circuit whose voltage should not decrease below, -VEE

+ 0.3 V.

To generate a current three times IREF. Three transistors, Q7, Q8 and Q9 each of which

is matched to Q2, are connected in parallel, and the combination is placed in a mirror

arrangement with Q2. Again, in an IC implementation, Q7, Q8, and Q9 shall be replaced

with a transistor having a EBJ area three times that of Q2.

35

Figure 12: Generation of constant

currents with different magnitudes


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GENERAL CONSIDERATIONS IN HIGH FREQUENCY RESPONSE OF

AMPLIFIERS

The amplifier circuits that we shall be going through further are intended for fabrication

using IC technology. Therefore they do not use bypass capacitors. Moreover, the various

stages in an integrated-circuit cascade amplifier are directly coupled; that is, they do not

employ

FIGURE 13 Frequency response of a direct-coupled (dc) amplifier.

large coupling capacitors, such as what we observe in discrete circuits. The frequency

response of these direct-coupled or DC amplifiers have the general form shown in

Fig. 13. It is clear that the gain remains constant at its midband value AMdown to zero

frequency (DC). That is, compared to the capacitively coupled amplifiers that use bypass

capacitors, direct-coupled IC amplifiers do not suffer gain reduction at low frequencies.

However, gain falls off at the high-frequency end due to the internal capacitances of the

transistor. These capacitances represent the charge storage phenomena that take place

inside the transistors and are included in the high-frequency device models.

The High-Frequency Gain Function

The amplifier gain, considering the effect of internal transistor capacitances, can be

expressed as a function of the complex-frequency variables in the general form

A(s) = AMFH(s)

36

. (31)


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Where AM is the mid-band gain, which is equal to the low-frequency or dc gain. The

value ofAMcan be determined by analysing the amplifier equivalent circuit by neglecting

the effect of the transistor internal capacitancesthat is, considering them to act as open

circuits. When we consider these capacitances, the gain has the factorFH(s), which can

be expressed as shown below, in terms of its poles and zeros,which are usually real

where Pl, P2, . . . , Pnare positive numbers indicating the frequencies of the n real

poles and z1, z2,.... Zn are positive, negative, or infinite numbers indicating the

frequencies of the n real transmission zeros. It is clear that, when sapproaches 0, FH(s)approach unity and the gain approachesAM.

The 3-dB Frequency,fH

The region of the high-frequency band which is close to the midband, is the region

of interest for an amplifier designer. The designer needs to estimateand if need be

modifythe value of the upper 3-dB frequency fH(or H = 2fH). It should be known

that in many cases the zeros are either at infinity or such high frequencies as to be of

little significance to the determination of H. If one of the poles, say Pl, is of much

lower frequency than any of the other poles, then this pole will have the greatest effecton the value of the amplifier H. It means that, this pole (referred as dominant pole) will

dominate the high-frequency response of the amplifier. In those cases the function FH(s)

can be approximated by

which is the transfer function of a first-order (or Single Time Constant) low-pass

network. So, if a dominant pole exists, then the value of H can be written as

37

. (32)

. (33)

. (34)


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The lowest-frequency pole which is at least two octaves (a factor of 4) away from the

nearest pole or zero can be referred as a dominant pole.

If a dominant pole does not exist, the 3-dB frequency Hcan be determined from a plot

of |FH(j)|. Alternatively, an approximate formula for H can be derived as follows:Consider, for the sake of simplicity, the case of a circuit that has two poles and two zeros

in the high-frequency band; and so,

Substitutings =jand considering the square of magnitude results

By definition, at = H, |FH|2= ; thus,

His usually smaller than the frequencies of all the poles and zeros, we may neglect the

III term in numerator and denominatorand solve for Hto obtain

This relationship can be extended to any number of poles and zeros as

From the above equation we may note that, if one of the poles, say wp1 is dominant, then

Eq.39 reduces to Eq.34.

38

. (35)

. (36)

. (37)

. (38)

. (39)


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EXAMPLE

The high-frequency response of an amplifier is characterized by the transfer function

Determine the 3-dB frequency approximately and exactly.

Solution The lowest-frequency pole is 104rad/s and is two octaves lower than the second

pole and a decade lower than the zero, we note that a dominant-pole situation almost

exists and H= 104rad/s. An estimate of Hcan be determined using Eq.39, as follows:

The exact value of wHcan be obtained from the given transfer function as 9537 rad/s.,

Fig. 14, represents a Bode and an exact plot for the given transfer function. This is a plot

of the high-frequency response of the amplifier normalized relative to its midband gain.

39

Figure14: Normalized high-

frequency response of the

amplifier in Example.


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Open-Circuit Time Constants

It is very clear that if the poles and zeros are known, then any one of the above methods

can be used to find fH. Usually, it is not an easy task to find poles and zeros by hand

analysis. In those cases, the following method is used which gives approximate value of

fH.

The numerator and denominator factors of FH(s) (eq.32) can be multiplied out and FH(s)

can beexpressed in the form as shown below:

the coefficients b and aare related to the frequencies of the poles and zeros, respectively.

The coefficient b1can be written as,

40

. (40)


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The value of b1 can be obtained by considering the various capacitances in the high-

frequency equivalent circuit one at a time while all other capacitors are set to zero

(replacing them with open circuits) [see Gray and Searle (1969)]

This means, the value of b1 is obtained by adding the individual time constants, called

open-circuit time constants.

A capacitance Ciis considered, we reduce all other capacitances to zero, the input signal

source is set to zero, and we find the resistance Rioas seen by Ci . This process is then

repeated for all other capacitors in the circuit. Therefore, b1is now given by,

[It is assumed that there are n capacitors in the high-frequency equivalent circuit]

The value of b1obtained is exact. The approximation comes into picture when the value

of b1is usedto determine H. If the zeros are not dominant and if one of the poles, say

P1, is dominant, then from Eq. (41), we may write,

Also, the upper cut-off (3-dB) frequency can be approximated as P1, leading to

In the complicated circuits, it will be not known to us whether a dominant pole exists or

not. However, we use the above equation to determine wHwhich gives good results in

most of the cases.

EXAMPLE

41

. (41)

. (42)

. (43)

. (44)


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Figure 15(a) shows the high-frequency equivalent circuit of a common-source MOSFET

amplifier. The amplifier is fed with a signal generator Vsig having a resistance Rsig.

ResistanceRin is due to the biasing network. Resistance R'L is the parallel equivalent of

the load resistance RL, the drain bias resistance RD, and the FET output resistance r0.

Capacitors Cgs and Cgd are the MOSFET internal capacitances. For Rsig = 100 k, Rin

= 420 k, Cgs= Cgd= 1pF,gm= 4 mA/V, andR'L=3.33 k, find the midband voltage

gain,AM= V0/Vsigand the upper 3-dB frequency,fH.

Solution

The midband voltage gain can be determined by considering the capacitors in the

MOSFET model to be open circuits. This results in the midband equivalent circuit

shown in Fig. 15(b), from which we find

AM=Vo/Vsig= -Rin(gmRL)/(Rin+Rsig) = -10.8 V/V

His foundusing the method of open-circuit time constants. The resistance Rgsas seen

by Cgs is found by setting Cgd =0 and short-circuiting the signal generator Vsig. This

results in the circuit of Fig. 15(c), from which we find that

FIGURE 15 Circuits for Example above (a) MOSFET amplifiers high-frequency equivalent circuit

(b) the equivalent circuit at midband frequencies; (c) circuit for determining the resistance Rgsand

(d) circuit for determining the resistance Rgd.

42

. (i)


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The open-circuit time constant of Cgsis given by

Tgs= CgsRgs= 1 x 10-12x 80.8 x 103= 80.8 ns

The resistance Rgdas seen by Cgd is found by setting Cgs= 0 and short-circuiting Vsig.

The result is the circuit in Fig. 15(d), to which we apply a test current I x. Writing a node

equation at G gives

Where R' = Rin// Rsig. A node equation at D Provides

Substituting for Vgsfrom Eq. (v) and rearranging terms yields

The open-circuit time constant of Cgdis

The upper 3-dB frequency Hcan now be determined from

43

. (ii)

. (iii)

. (iv)

. (v)

. (vi)

. (vii)

M


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The method of open-circuit time constants specifies the circuit designer, which of the

various capacitances is significant in determining the amplifier frequency response.

In the above example we see that Cgdis the dominant capacitance in determining fH. We

also note that, in effect to increase fHeither we use a MOSFET with smaller Cgdor, for

a given MOSFET, we reduce Rgd by using a smallerR' or R'L. IfR' is fixed, then for a

given MOSFET the only way to increase bandwidth is by reducing the load resistance.

Unfortunately, this also decreases the midband gain. This is an example of the usual

trade-off between gain and bandwidth.

Miller's Theorem

Consider the situation in Fig. 16(a), which can be a part of a larger circuit which is not

shown. We observe two isolated circuit nodes, labeled 1 and 2, between which an

impedance Z is connected. Nodes 1 and 2 are also connected to other parts of the circuit,

as indicated by the dashed lines emanating from the two nodes. Furthermore, it is

assumed that the voltage at node 2 is known and is related to that at node 1 by V2=KV1.

In typical situations K is a gain factor that can be +ve or -ve and has a magnitude usually

larger than one.

44

. (viii)


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FIGURE 16 The Miller equivalent circuit.

Miller's theorem states that impedance Z can be equivalently replaced by twoimpedances: Z1connected between node 1 and ground and Z2connected between node 2

and ground, where

Z1= Z / (1-K)

And

Z2= Z / (1 - )

to obtain the equivalent circuit shown in Fig. 16(b).

Proof of Miller's theorem can be given by deriving Eq. (45 &46) as follows:

In the original circuit of Fig. 16(a), from node-1 impedance Z carries the current I.

Therefore, to keep this current unchanged in the equivalent circuit, we must choose the

value ofZ1so that it draws an equal current.

I1= =

which yields the value of Z1 in Eq. (45). Similarly, to keep the current into node 2

unchanged, we must choose the value of Z2so that,

45

(45)

(46)


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,

which yields the expression for Z2in Eq. (46). The Miller equivalent circuit obtained is

based on the fact that the rest of the circuit remains unchanged. If not, the ratio of V2to

V1might change.

It should be known that the Miller equivalent circuit cannotbe used directly to determine

the output resistance of an amplifier. This is because in determining output resistances it

is implicitly assumed that the source signal is reduced to zero and that a test-signal source

is applied to the output terminalsleading to a major change in the circuit, which results

Millers equivalent circuit to be invalid.

Example: Figure 17(a) shows an ideal voltage amplifier having a gain of -100 V/V

with an impedance Z connected between its output and input terminals. Find the Miller

equivalent circuit when Z is (a) a l-M resistance, and (b) a 1-pF capacitance. Use the

equivalent circuit to find Vo/Vsig

Solution

(a) For Z = 1 M, using Miller's theorem which leads to the equivalent circuit in Fig.

17(b), where

46

Figure 17: Circuits for Exa

above

= -kV1/ [-k z/(1-k)]


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The voltage gain is given by:

(b) For Z, as a 1-pF capacitancethat is, Z =1/sC = 1/s x 1 x 10-12Miller's theorem

allows us to replace Z by Z1and Z2where

It is clear that Z1is a capacitance of value 101C = 101 pF and Z2is a capacitance 1.01 C

= 1.01 pF. The equivalent circuit is shown in Fig. 17(c), from which the voltage gain can

be found as follows:

The transfer function of a first-order low-pass circuit with a dc gain of -100 and a cut-off

frequency,f3dB

47


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we see that the replacement of a feedback or bridging resistance results, for a negative K,

in a smaller resistance [divided by a factor (1 - K)] at the input. If the feedback element

is a capacitance, its value is multiplied by (1- K) to result in a equivalent capacitance at

the input side. The multiplication of a feedback capacitance by (1 - K) is referred to as

Millers multiplication or Millers effect.

Drawn from Microelectronics by sedra and smith, 5thedition.

The 8051 Microcontoller mahmudou Unit2-PT

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