Tezzaron Semiconductor 04/08/2013 1 Implementing 2.5D and 3D Devices Bob Patti, CTO...

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  • Slide 1
  • Tezzaron Semiconductor 04/08/2013 1 Implementing 2.5D and 3D Devices Bob Patti, CTO [email protected]
  • Slide 2
  • Tezzaron Semiconductor 04/08/2013 2 The Effect of 2.5/3D on Devices
  • Slide 3
  • Tezzaron Semiconductor 04/08/2013 3 Span of 3D Integration CMOS 3D Analog Flash DRAM CPU Analog Flash DRAM CPU 3D Through Via Chip Stack 100,000,000s/sqmm Transistor to Transistor Ultimate goal 1s/sqmm Peripheral I/O Flash, DRAM CMOS Sensors Tezzaron 3D-ICs 100-1,000,000/sqmm 1000-10M Interconnects/device Packaging Wafer Fab IBM IBM/Samsung
  • Slide 4
  • Tezzaron Semiconductor 04/08/2013 4 10um TSV 20um Pitch TSV Pitch Area Number of TSVs TSV pitch issue example 1024 bit busses require a lot of space with larger TSVs They connect to the heart and most dense area of processing elements The 45nm bus pitch is ~100nm; TSV pitch is >100x greater The big TSV pitch means TOF errors and at least 3 repeater stages FPUFPU 1024 bit bus Single layer interconnect 1um TSV 2um Pitch
  • Slide 5
  • Tezzaron Semiconductor 04/08/2013 5 3D Interconnect Characteristics SuperContact TM I 200mm Via First, FEOL SuperContact TM III 200mm Via First, FEOL SuperContact TM IV 200mm Via First, FEOL Interposer TSV Bond PointsDie to Wafer Size L X W X D Material 1.2 X 1.2 X 6.0 W in Bulk 0.85 X 0.85 X 10 W in Bulk 0.60 X 0.60 X 2 W in SOI 10 X 10 X 100 Cu 1.7 X 1.7 Cu 3 X 3 Cu Minimum Pitch

DRAM Pricing – A White Paper - Tezzaron Semiconductor Pricing – A White Paper ©2002 Tachyon Semiconductor September 30th, 2002 Page 2 of 7 1415 Bond Street, Suite 111, Naperville,

DRAM Pricing – A White Paper - Tezzaron Semiconductor Pricing – A White Paper ©2002 Tachyon Semiconductor September 30th, 2002 Page 2 of 7 1415 Bond Street, Suite 111, Naperville,

3D_IC for Real Chips Bob Patti, CTO rpatti@tezzaron.con

3D_IC for Real Chips Bob Patti, CTO [email protected]

DiRAM™ Architecture Makes - Tezzaron Semiconductor · •Burn-In & Test Stack MemCon 2013 18 ... Photonic I/O • Lowest Power • Highest Performance DiRAM4 Launches with 1.2 V

DiRAM™ Architecture Makes - Tezzaron Semiconductor · •Burn-In & Test Stack MemCon 2013 18 ... Photonic I/O • Lowest Power • Highest Performance DiRAM4 Launches with 1.2 V

How 3D Memory is Changing Computing€¦ · Tezzaron Semiconductor 03/13/2015 How 3D Memory is Changing Computing DATE 2015 W05 Robert Patti, CTO rpatti@tezzaron.com 1

How 3D Memory is Changing Computing€¦ · Tezzaron Semiconductor 03/13/2015 How 3D Memory is Changing Computing DATE 2015 W05 Robert Patti, CTO [email protected] 1

Implementing 2.5D and 3D Devices Bob Patti, CTO rpatti@tezzaron.com

Implementing 2.5D and 3D Devices Bob Patti, CTO [email protected]

Tezzaron Semiconductor 06/14/2011 3D_IC for Real Chips Bob Patti, CTO rpatti@tezzaron.con 1.

Tezzaron Semiconductor 06/14/2011 3D_IC for Real Chips Bob Patti, CTO [email protected] 1.

Tezzaron Semiconductor FaStack Technology A Look at Various 3D Applications, Their Designs, and Ultimate Silicon Results.

Tezzaron Semiconductor FaStack Technology A Look at Various 3D Applications, Their Designs, and Ultimate Silicon Results.

Tezzaron Semiconductor Device Summary Fully functional devices demonstrating a wide variety of applications Good yield –90% process, 96% device Demonstrated.

Tezzaron Semiconductor Device Summary Fully functional devices demonstrating a wide variety of applications Good yield –90% process, 96% device Demonstrated.

3D-ICs and Integrated Circuit Security - tezzaron.com · 3D-ICs and Integrated Circuit Security Page 1 of 2 ... Each substrate is aggressively thinned. The entire circuit is integrated

3D-ICs and Integrated Circuit Security - tezzaron.com · 3D-ICs and Integrated Circuit Security Page 1 of 2 ... Each substrate is aggressively thinned. The entire circuit is integrated

Lessons and Future for 3D Circuit Design With focus on Chartered/Tezzaron Activities

Lessons and Future for 3D Circuit Design With focus on Chartered/Tezzaron Activities

3D Integration: New Opportunities for Speed, Power …infieri-network.eu/.../Tezzaron_Presentation_INSS_070713_dist.pdf© Tezzaron Semiconductor INFIERI 2013 07/07/2013 3D Integration:

3D Integration: New Opportunities for Speed, Power …infieri-network.eu/.../Tezzaron_Presentation_INSS_070713_dist.pdf© Tezzaron Semiconductor INFIERI 2013 07/07/2013 3D Integration:

2.5/3D Integrated Circuit Technology - Tezzaron

2.5/3D Integrated Circuit Technology - Tezzaron

Tezzaron Semiconductor And Then a Miracle Occurs…. 5 years and many dollars later…….. What’s so Funny about Science? By Sidney Harris (1977)

Tezzaron Semiconductor And Then a Miracle Occurs…. 5 years and many dollars later…….. What’s so Funny about Science? By Sidney Harris (1977)

Preparation run Tezzaron-Chartered 06.01.2009 A.Rozanov 1 Introduction Restarts test on PS en Avril 2009 Mesure PS SEU chip SEU-IBM-2008 40 Mhz avec FPGA.

Preparation run Tezzaron-Chartered 06.01.2009 A.Rozanov 1 Introduction Restarts test on PS en Avril 2009 Mesure PS SEU chip SEU-IBM-2008 40 Mhz avec FPGA.

Tezzaron Semiconductor 11/15/2013 1 A Perspective on Manufacturing 2.5/3D Bob Patti, CTO rpatti@tezzaron.com.

Tezzaron Semiconductor 11/15/2013 1 A Perspective on Manufacturing 2.5/3D Bob Patti, CTO [email protected].

Tezzaron Semiconductor 04/27/2015 New Trends in Advanced 3D Vertical Interconnect Technology rpatti@tezzaron.com 1.

Tezzaron Semiconductor 04/27/2015 New Trends in Advanced 3D Vertical Interconnect Technology [email protected] 1.