Testing22.pdf

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Mar 24, 2008 E0286@SERC 1 VLSI Testing Delay Test Virendra Singh Indian Institute of Science Bangalore [email protected] E0286: Testing and Verification of SoC Designs Lecture 22

Transcript of Testing22.pdf

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Mar 24, 2008 E0286@SERC 1

VLSI Testing Delay Test

Virendra SinghIndian Institute of Science

[email protected]

E0286: Testing and Verification of SoC Designs

Lecture 22

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Definitions

Controlling value (cv) : An input of a gate is said to have a controlling value if it uniquely determines the output of the gate independent of other inputs

For example, 0 for AND or NAND

A path R in a circuit is a sequence (g0g1……gr), where g0 is a PI, g1g2.. are gate outputs, gr is a PO

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DefinitionsAn on-input of path R is a connection between two gates along path R

A side-input (off-input) of path R is any connection to a gate along path R other than its on-input

A path that starts at a primary input and ends at a side-input of path R is called a side-pathof R

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Transition Delay Fault

Two faults per gate; slow-to-rise and slow-to-fall.Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault.Models spot (or gross) delay defects.

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Transition Delay Test

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3

1

1

1

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Path P1

P2

P3SA0

D’

D’

D’ D

1

D’

1

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Transition Delay Test

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1

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Path P1

P2

P3

Single lumped inertial delay modeled for each gatePI transitions assumed to occur without time skew

SA0

D’

D’

D’ D

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0

D

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Transition Delay Test

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01

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Path P1

P2

P3SA00D’

0D’

0D’ 1D

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X0

1D

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Path Delay Fault

Cheng’s classificationRobustly testableNon-robustly (NR) testableFunctional sensitizable (FS) testableFunctionally unsensitizable(functionally redundant)

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Path Delay Fault

Robust testable : detect target PDF independent of delays in rest of the circuit.It must satisfies the following conditions

It launches the desired transition at primary inputAll side inputs of target path settle to non-controlling values under V2Whenever the logic transition at an on-inputis from non-controlling to controlling value (ncv to cv), each side-input should maintain steady non-controlling value (ncv)

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Path Delay Fault

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Path Delay FaultNon-Robust (NR ) testable :

It must satisfies the following conditionsIt launches the desired transition at primary inputAll side-inputs of target path settle to non-controlling values (ncv) under V2

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Path Delay FaultFunctional Sensitizable (FS) testable:

Detection of faults on paths that are sensitizableunder FS criterion depends on the delays on signals outside the target pathIt must satisfies the following conditions

It launches the desired transition at primary inputWhenever the logic transition at an on-inputis non-controlling value (ncv) under vector V2, each side-input should have non-controlling value (ncv) under V2

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Path Delay Fault

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Path Delay FaultFunctionally unsensitizable

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Path Delay Fault

On-input Side-inputs testabilitycv -> ncv Stable cv Untestable

Stable ncv Robustcv -> ncvncv -> cv Untestable

ncv -> cv Stable cv UntestableStable ncv Robustcv -> ncv NRncv -> cv FS

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Thank You