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VLSI Testing Sequential Circuits with

Combinational TG complexity

VLSI Testing Sequential Circuits with

Combinational TG complexity

Virendra SinghIndian Institute of Science

Bangalorevirendra@computer.org

E0-286: Testing and Verification of SoC Design

Lecture – 19

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ClassificationClassification

Sequential Circuit ofAcyclic structure

Sequential Circuit of Balance Structure[Gupta & Breuer]

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Balanced Circuit ?Balanced Circuit ?

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Transformation C*Transformation C*1. For a PI with fanout branches, the set of fanout

branches of the PI is denoted by X. Obtain a smallest partition of X which satisfies the following statement:

If branches xi and xj belongs to different blocks X(i) , X(j) of the partition, then xi and xj are separable. Each partitioned block is provided with a new PI separated from original PI.

2. FF are replaced by wires

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Internally Balanced CircuitInternally Balanced CircuitIf a circuit S* resulting from operation 1 in transformation C* on circuit S is a balanced circuit, then S is regarded as an internally balanced circuit

Fujiwara TC 2000

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ClassificationClassification

Sequential Circuit ofAcyclic structure

Sequential Circuit of Internally Balance structure

[Fujiwara]Sequential Circuit of

Balance Structure[Gupta et al]

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FSM RealizationFSM RealizationTheorem1 : The necessary and sufficient condition for realization of an FSM M as an acyclic structure is mk(I) = O for some constant, where mk(I) is inductively defined as m1(I) = m(I) and mk(I) = m(mk-1(I)) for k>1

Lemma1: The statement that an FSM M is expressed as mk(I) = O for any k is equivalent to the statement that M can be realized by a finite memory machine of length k. In addition, it is equivalent to the statement any input sequence of length k become a synchronizing sequence of M

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FSM RealizationFSM Realization

Corollary 1: The necessary and sufficient condition for realization of an FSM M as an acyclic structure is that M can be realized by a finite input memory machine

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Acyclic RealizationAcyclic RealizationTheorem 2: Any sequential circuit of acyclic structure can be transformed into an equivalent circuit allowing realization with a finite input memory, by operation of retiming and logic duplication

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TransformationTransformation

Retiming

Logic Duplication

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Acyclic Seq. CircuitsAcyclic Seq. CircuitsTheorem 2: Any FSM allowing realization as an acyclic structure can be realized as an internally balanced structure

Theorem 3: An FSM exists which can be realized as an acyclic structure, but which cannot be realized as a balanced structure

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FSM RealizationFSM Realization

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TGC: Acyclic CircuitsTGC: Acyclic Circuits

Duplicates

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TGC: Balanced CircuitsTGC: Balanced Circuits

C-Transformed circuit

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TGC: Internally BalancedTGC: Internally Balanced

Theorem 4: If a sequential circuit S is an internally balanced structure, S allows TG with combinational TG complexity

If fault f in S can be tested, then fault fc in C*(S) corresponding to f can be testedin C*(S)

It is sufficient to prove that a test pattern Tc for fc in C*(S) can be generated from the test sequence T for f in S

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TGC: Internally BalancedTGC: Internally BalancedIf sequential depth of S is d, the length of T is d+1

Assume f can be detected in time frame t at PO zk (1 < t < d+1)

From this test sequence T, we define the PI value xi in C*(S) for test pattern Tc, in following way:

1. Case of xi not being a PI resulting from separation:

The sequential depth from xi is uniquely determined. Let the depth from be dik . The value of xi require to detect f in T at zk is the value of the PI xi in time frame t-dik . Therefore the PI value xi in time frame t-dik in T can be set to define the PI value xi of test pattern Tc.

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TGC: Internally BalancedTGC: Internally Balanced2. Case xi being a PI resulting from separation

Suppose that the original PI value of xi in S is denoted x. Although x is a PI in S, xi is not a PI. In C*(S), xi is a PI. Since this is a case of an internally balance structure, we can uniquely determine the sequential depth from xi to zk , which is denoted as dik . The value of xi required to detect f in T at zk equals the x value in time frame t-dik . The x value in time frame t-dik in T is set to define the PI value xi in the test pattern sequence Tc.

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Internally Balanced CircuitInternally Balanced Circuit

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Internally BalancedInternally Balanced

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Kernel ExtractionKernel Extraction

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Kernel ExtractionKernel Extraction

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Internally Balanced CircuitInternally Balanced Circuit

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Internally Balanced CircuitInternally Balanced Circuit

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Internally Balanced CircuitInternally Balanced Circuit

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Internally Balanced CircuitInternally Balanced Circuit

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Thank YouThank You