Feb 27, 2008 E0-286@SERC 1

VLSI Testing Scan Design

VLSI Testing Scan Design

Virendra SinghIndian Institute of Science (IISc)

Bangalorevirendra@computer.org

E0-286: Testing and Verification of SoC Design

Lecture 16

Feb 27, 2008 E0-286@SERC 2

Cyclic Circuit ExampleCyclic Circuit Example

F1 F2CNT

Z

Modulo-3 counter

s - graph

F1 F2

Feb 27, 2008 E0-286@SERC 3

Modulo-3 CounterModulo-3 Counter Cyclic structure Sequential depth is undefined. Circuit is not initializable. No tests can be generated

for any stuck-at fault. After expanding the circuit to 9Nff = 81, or fewer,

time-frames ATPG program calls any given target fault untestable.

Circuit can only be functionally tested by multiple observations.

Functional tests, when simulated, give no fault coverage.

Feb 27, 2008 E0-286@SERC 4

Adding Initializing HardwareAdding Initializing Hardware

F1 F2CNT

Z

Initializable modulo-3 counter

s - graphF1 F2

CLR

s-a-0

s-a-1

s-a-1s-a-1 Untestable faultPotentially detectable fault

Feb 27, 2008 E0-286@SERC 5

Difficulties in Seq. ATPGDifficulties in Seq. ATPG Poor initializability. Poor controllability/observability of state

variables. Gate count, number of flip-flops, and sequential

depth do not explain the problem. Cycles are mainly responsible for complexity. An ATPG experiment:

Circuit Number of Number of Sequential ATPG Faultgates flip-flops depth CPU s coverage

TLC 355 21 14* 1,247 89.01%

Chip A 1,112 39 14 269 98.80%

* Maximum number of flip-flops on a PI to PO path

Feb 27, 2008 E0-286@SERC 6

Benchmark CircuitsBenchmark Circuits

CircuitPIPOFFGatesStructureSequential depthTotal faultsDetected faultsPotentially detected faultsUntestable faultsAbandoned faultsFault coverage (%)Fault efficiency (%)Max. sequence lengthTotal test vectorsGentest CPU s (Sparc 2)

s1196141418

529Cycle-free

412421239

030

99.8100.0

3313

10

s1238141418

508Cycle-free

413551283

0720

94.7100.0

3308

15

s14888

196

653Cyclic

--14861384

2267693.194.824

52519941

s14948

196

647Cyclic

--15061379

2309791.693.428

55919183

Feb 27, 2008 E0-286@SERC 7

Scan DesignScan DesignCircuit is designed using pre-specified design rules.Test structure (hardware) is added to the verified

design:Add a test control (TC) primary input.Replace flip-flops by scan flip-flops (SFF) and connect to

form one or more shift registers in the test mode.Make input/output of each scan shift register

controllable/observable from PI/PO.Use combinational ATPG to obtain tests for all

testable faults in the combinational logic.Add shift register tests and convert ATPG tests

into scan sequences for use in manufacturing test.

Feb 27, 2008 E0-286@SERC 8

Scan Flip-Flop (SFF)Scan Flip-Flop (SFF)

DTC

SD

CK

Q

QMUX

D flip-flop

Master latch Slave latch

CK

TC Normal mode, D selected Scan mode, SD selected

Master open Slave opent

t

Logicoverhead

Feb 27, 2008 E0-286@SERC 9

Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)

Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)

D

SD

MCK

Q

Q

D flip-flop

Master latch Slave latch

t

SCK

TCK

SCK

MCK

TCK

N

o

r

m

a

l

m

o

d

e

MCK

TCK

S

c

a

n

m

o

d

e

Logicoverhead

Feb 27, 2008 E0-286@SERC 10

Adding Scan StructureAdding Scan Structure

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANINTC or TCK Not shown: CK or

MCK/SCK feed allSFFs.

Feb 27, 2008 E0-286@SERC 11

Comb. Test VectorsComb. Test Vectors

I2I1 O1 O2

S2S1 N2N1

Combinational

logic

PI

Presentstate

PO

Nextstate

SCANINTC SCANOUT

Feb 27, 2008 E0-286@SERC 12

Comb. Test VectorsComb. Test Vectors

I2I1

O1 O2

PI

PO

SCANIN

SCANOUT

S1 S2

N1 N2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TC

Dont careor random

bits

Sequence length = (ncomb + 1) nsff + ncomb clock periodsncomb = number of combinational vectors

nsff = number of scan flip-flops

Feb 27, 2008 E0-286@SERC 13

Testing Scan RegisterTesting Scan Register Scan register must be tested prior to

application of scan test sequences. A shift sequence 00110011 . . . of length

nsff+4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output.

Total scan test length: (ncomb + 2) nsff + ncomb + 4 clock periods.

Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks.

Multiple scan registers reduce test length.

Feb 27, 2008 E0-286@SERC 14

Multiple Scan RegistersMultiple Scan Registers Scan flip-flops can be distributed among any number

of shift registers, each having a separate scanin and scanout pin.

Test sequence length is determined by the longest scan shift register.

Just one test control (TC) pin is essential.

SFFSFF

SFF

Combinationallogic

PI/SCANIN PO/SCANOUTM

UX

CK

TC

Feb 27, 2008 E0-286@SERC 15

Scan OverheadsScan Overheads IO pins: One pin necessary. Area overhead:

Gate overhead = [4 nsff/(ng+10nff)] x 100%, where ng = comb. gates; nff = flip-flops; Example ng = 100k gates, nff = 2k flip-flops, overhead = 6.7%.

More accurate estimate must consider scan wiring and layout area.

Performance overhead: Multiplexer delay added in combinational

path; approx. two gate-delays. Flip-flop output loading due to one additional

fanout; approx. 5-6%.

Feb 27, 2008 E0-286@SERC 16

Hierarchical ScanHierarchical Scan Scan flip-flops are chained within subnetworks before

chaining subnetworks. Advantages:

Automatic scan insertion in netlist Circuit hierarchy preserved helps in debugging and

design changes

Disadvantage: Non-optimum chip layout.

SFF1

SFF2 SFF3

SFF4SFF3SFF1

SFF2SFF4

Scanin Scanout

ScaninScanout

Hierarchical netlist Flat layout

Feb 27, 2008 E0-286@SERC 17

Optimum Scan LayoutOptimum Scan Layout

IOpad

Flip-flopcell

Interconnects

Routingchannels

SFFcell

TC

SCANIN

SCANOUT

Y

X X

Y

Active areas: XY and XY

Feb 27, 2008 E0-286@SERC 18

ATPG Example: S5378ATPG Example: S5378

Original

2,781179

00.0%

4,60335/49

70.0%70.9%

5,533 s414414

Full-scan

2,7810

17915.66%4,603

214/22899.1%

100.0%5 s

585105,662

Number of combinational gatesNumber of non-scan flip-flops (10 gates each)Number of scan flip-flops (14 gates each)Gate overheadNumber of faultsPI/PO for ATPGFault coverageFault efficiencyCPU time on SUN Ultra II, 200MHz processorNumber of ATPG vectorsScan sequence length

Feb 27, 2008 E0-286@SERC 19

Automated Scan DesignAutomated Scan Design

Behavior, RTL, and logicDesign and verification

Gate-levelnetlist

Scan designrule audits

CombinationalATPG

Scan hardwareinsertion

Chip layout: Scan-chain optimization,timing verification

Scan sequenceand test program

generation

Design and testdata for

manufacturing

Ruleviolations

Scannetlist

Combinationalvectors

Scan chain order

Mask dataTest program

Feb 27, 2008 E0-286@SERC 20

Scan Design RulesScan Design Rules

Use only clocked D-type of flip-flops for all state variables.At least one PI pin must be available for test;

more pins, if available, can be used.All clocks must be controlled from PIs.Clocks must not feed data inputs of flip-flops.

Feb 27, 2008 E0-286@SERC 21

Correcting a Rule ViolationCorrecting a Rule Violation

All clocks must be controlled from PIs.

Comb.logic

Comb.logic

D1

D2CK

Q

FF

Comb.logic

D1D2

CK

Q

FF

Comb.logic

Feb 27, 2008 E0-286@SERC 22

Thank YouThank You

VLSI Testing Scan DesignCyclic Circuit ExampleModulo-3 CounterAdding Initializing HardwareDifficulties in Seq. ATPGBenchmark CircuitsScan DesignScan Flip-Flop (SFF)Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)Adding Scan StructureComb. Test VectorsComb. Test VectorsTesting Scan RegisterMultiple Scan RegistersScan OverheadsHierarchical ScanOptimum Scan LayoutATPG Example: S5378Automated Scan DesignScan Design RulesCorrecting a Rule ViolationThank You