Testing11.pdf

18
Feb 13, 2008 E0-286@SERC 1 VLSI Testing Testability Analysis VLSI Testing Testability Analysis Virendra Singh Indian Institute of Science (IISc) Bangalore [email protected] E0-286: Testing and Verification of SoC Design Lecture - 11

Transcript of Testing11.pdf

Page 1: Testing11.pdf

Feb 13, 2008 E0-286@SERC 1

VLSI Testing Testability Analysis

VLSI Testing Testability Analysis

Virendra SinghIndian Institute of Science (IISc)

[email protected]

E0-286: Testing and Verification of SoC Design

Lecture - 11

Page 2: Testing11.pdf

Feb 13, 2008 E0-286@SERC 2

PurposePurposeNeed approximate measure of:

Difficulty of setting internal circuit lines to 0 or 1 by setting primary circuit inputsDifficulty of observing internal circuit lines by observing primary outputs

Uses:Analysis of difficulty of testing internal circuit parts – redesign or add special test hardwareGuidance for algorithms computing test patterns – avoid using hard-to-control linesEstimation of fault coverageEstimation of test vector length

Page 3: Testing11.pdf

Feb 13, 2008 E0-286@SERC 3

OriginsOriginsControl theoryRutman 1972 -- First definition of controllabilityGoldstein 1979 -- SCOAP First definition of observability First elegant formulation First efficient algorithm to compute

controllability and observabilityParker & McCluskey 1975 Definition of Probabilistic Controllability

Brglez 1984 -- COP 1st probabilistic measures

Seth, Pan & Agrawal 1985 – PREDICT 1st exact probabilistic measures

Page 4: Testing11.pdf

Feb 13, 2008 E0-286@SERC 4

Testability AnalysisTestability Analysis

Involves Circuit Topological analysis, but no test vectors and no search algorithm

Static analysis

Linear computational complexityOtherwise, is pointless – might as well use automatic test-pattern generation and calculate:

Exact fault coverageExact test vectors

Page 5: Testing11.pdf

Feb 13, 2008 E0-286@SERC 5

Types of MeasuresTypes of Measures

SCOAP – Sandia Controllability and ObservabilityAnalysis ProgramCombinational measures:

CC0 – Difficulty of setting circuit line to logic 0CC1 – Difficulty of setting circuit line to logic 1CO – Difficulty of observing a circuit line

Sequential measures – analogous:SC0SC1SO

Page 6: Testing11.pdf

Feb 13, 2008 E0-286@SERC 6

Range of SCOAP MeasuresRange of SCOAP Measures

Controllabilities – 1 (easiest) to infinity (hardest)Observabilities – 0 (easiest) to infinity (hardest)Combinational measures: Roughly proportional to # circuit lines that

must be set to control or observe given lineSequential measures: Roughly proportional to # times a flip-flop

must be clocked to control or observe given line

Page 7: Testing11.pdf

Feb 13, 2008 E0-286@SERC 7

Goldstein’s SCOAP MeasuresGoldstein’s SCOAP Measures

AND gate O/P 0 controllability:output_controllability = min (input_controllabilities)

+ 1AND gate O/P 1 controllability:output_controllability = Σ (input_controllabilities)

+ 1XOR gate O/P controllabilityoutput_controllability = min (controllabilities of

each input set) + 1Fanout Stem observability:Σ

or min (some or all fanout branch observabilities)

Page 8: Testing11.pdf

Feb 13, 2008 E0-286@SERC 8

Controllability ExamplesControllability Examples

Page 9: Testing11.pdf

Feb 13, 2008 E0-286@SERC 9

Controllability ExamplesControllability Examples

Page 10: Testing11.pdf

Feb 13, 2008 E0-286@SERC 10

Observability ExamplesObservability ExamplesTo observe a gate input:Observe output and make other input values non-controlling

Page 11: Testing11.pdf

Feb 13, 2008 E0-286@SERC 11

Observability ExamplesObservability ExamplesTo observe a fanout stem:Observe it through branch with best observability

Page 12: Testing11.pdf

Feb 13, 2008 E0-286@SERC 12

Levelization Algorithm Levelization Algorithm Label each gate with max # of logic levels from primary inputs or with max # of logic levels from primary outputAssign level # 0 to all primary inputs (PIs)For each PI fanout:

Label that line with the PI level number, &Queue logic gate driven by that fanout

While queue is not empty:Dequeue next logic gateIf all gate inputs have level #’s, label the gate with the maximum of them + 1;Else, requeue the gate

Page 13: Testing11.pdf

Feb 13, 2008 E0-286@SERC 13

Controllability - Level 0Controllability - Level 0

Circled numbers give level number. (CC0, CC1)

Page 14: Testing11.pdf

Feb 13, 2008 E0-286@SERC 14

Controllability - Level 2Controllability - Level 2

Page 15: Testing11.pdf

Feb 13, 2008 E0-286@SERC 15

Combinational ControllabilityCombinational Controllability

Page 16: Testing11.pdf

Feb 13, 2008 E0-286@SERC 16

Observability for Level 1Observability for Level 1

Number in square box is level from primary outputs (POs).(CC0, CC1) CO

Page 17: Testing11.pdf

Feb 13, 2008 E0-286@SERC 17

Observabilities - Level 2Observabilities - Level 2

Page 18: Testing11.pdf

Feb 13, 2008 E0-286@SERC 18

Thank YouThank You