Testing of CORDIC Chip Sandeep R Aedudodla Ashok Verma Meena Ramani Roby Thomas.

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Testing of CORDIC Chip Sandeep R Aedudodla Ashok Verma Meena Ramani Roby Thomas

Transcript of Testing of CORDIC Chip Sandeep R Aedudodla Ashok Verma Meena Ramani Roby Thomas.

Page 1: Testing of CORDIC Chip Sandeep R Aedudodla Ashok Verma Meena Ramani Roby Thomas.

Testing of CORDIC Chip

Sandeep R Aedudodla

Ashok Verma

Meena Ramani

Roby Thomas

Page 2: Testing of CORDIC Chip Sandeep R Aedudodla Ashok Verma Meena Ramani Roby Thomas.

CORDIC

CORDIC: A highly efficient computing technique to compute a variety of elementary functions (Ex. Sine, Cosine,Arctan, Sinh, Cosh, Log, Exp etc).

Used extensively in calculators.

Makes use of shifter and adder blocks to compute these functions. Does not need a multiplier.

Page 3: Testing of CORDIC Chip Sandeep R Aedudodla Ashok Verma Meena Ramani Roby Thomas.

Architecture

What to Test? 8-bit Latches 8-bit Adder/Subtractor Units A Variable Length 8-bit Barrel Shifter ROM Table 3-bit Counter

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The Test Plan

IDDQ Test : To detect any non-catastrophic defects.

Functional Test: Test all logic and memory sub-circuits involved and whether the mathematical functions evaluated are accurate enough.

Parametric Test: Test whether Chip meets specifications, such as timing requirements, power consumption etc.

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Modified Design for Test

0.6073 0

ADD/SUB

ADD/SUB

Y-OUTX-OUT

Y-REGX-REG >>k

>>k >>k

MUXMUX

INPUT

ADD/SUB

REG-TEMP >>k

X-REG >>k

MUX

X Y Z

T

M U X

Z

Y

X

T

ROM

3- BIT

CO

UN

TE

RC

LK

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List of Tests

Functional Test : To test the working of various sub-circuits, such as the Latches, Add/Sub Units, Counter, ROM, Shifters.

Functional Test Flow: Test Latches followed by Add/Sub Unit, Counter, ROM,

Shifter. Full Scan Methodology Planned. Estimated No. of extra pins required: 2 or 3 Used PISO for testing the registers. Used verified Registers to test Add/Sub blocks. Used verified registers and Add/Sub blocks to test the

other blocks.

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List of Tests (contd)

Parametric Test : To test the various specification parameters determining Chip – performance.

Measurement of Rise and Fall times: Using the ATE’s Time Measurement System (TMS). May need an advanced TMS capable of accuracy less then a nanosecond.

Measurement of Power Consumption

IDDQ Test : Measures Leakage current at a particular state, by using a current-to-voltage converter on the DIB. State is set by the ATE.

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Components Required on DIB Buffers to overcome the parasitic capacitance of Tester A Current to Voltage converter (for IDDQ) A Local Relay Connection to bypass the Current-Voltage Converter

CORDIC

Buffers

I to VConverter

RelayGND

VDD

INPUTS

OUTPUTS

ContactDUT socket