Testability in EOCHL (and beyond…)
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Testability in EOCHL (and beyond…)
Vladimir ZivkovicNational Institute for Subatomic Physics (Nikhef),
Amsterdam, The Netherlands
FEI4_A review, 2-3rd November 2009 CERN, Geneve
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Outline
• Introduction• DfT Architecture• DfT Flow• Back-end Test Development• Future Work
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Functional vs Structural Testing Functional testing verifies that a circuit fulfils the desired
spec. Functional testing not feasible for exhaustive tests.
Example: 32-bit adder requires 265 ≈ 3.7*1019 test vectors Structural test focuses rather on the circuit structure and
can cover manufacturing defects that otherwise may not have been detected by functional testing. Power or ground shorts Open interconnect on the die (caused by dust particles) Short circuited source or drain on the transistor, (caused by
metal spike through)
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Scan Chain DfT Principle
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Outline
• Introduction• DfT Architecture• DfT Flow• Back-end Test Development• Future Work
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Digital Testing Framework
• Stimulus and response calculated by Automatic Test Pattern Generator (ATPG) based on fault models
• Computed on the whole device or on parts of the design, so-called embedded IP’s (cores)
• Access to embedded terminals of the IP through design for test (DfT) is necessary
Device Under Test
(DUT)
0110100010110001
:0001011110100001
:
comparators fail flagsstimuli
response
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Generic Test Access Architecture
IPsource sink
1. Test Pattern Source and Sink
wrapper
3. Core Test Wrapper
IPTAM
2. Test Access Mechanism (TAM)
TAMTestRail TestRail
[ Zorian, Marinissen, Dey - ITC’98 ]
IP = {EOCHL, CMD, DOB, EODCL}
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Wrapper Isolation OverviewWrapper
functioninputs function
outputs
IP
TestRailinputs
TestRailoutputs
bypa
ssby
pass
MandatoryWrapper cells providing function access and test controllability + observability at IP’s data terminals
TestRail access to wrapper cells (‘surround chains’) and IP flip flops (‘scan chains’)
OptionalBypass register for all TestRail chains
Wrapper Control Block+ anti-skew element
Wrapper Control Block
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How does this reflect to our situation?
IC LEVEL
CMD
scan chain 0 (3000 FFs)scan chain 1 (600 FFs)
Wrapper Control BlockWrapper EOCHL
Wrapper Control BlockWrapper CMD
EOCHL
scan chain 0 (1700 FFs)scan chain 1 (400 FFs)
Top level Test Control
TRI_cmd[0:2]
Inputs from other digital blocks, e.g. EODCL, CFGMEM
TRO_eochl[0:2]
Outputs to other digital blocks, e.g. EODCL, CFGMEM
Insert wrappers around EOCHL, CMD and other blocks with scan chains (DOB, EODHL)
Inputs from other digital blocks, e.g. EODCL, CFGMEM
TRO_cmd[0:2] TRI_eochl[0:2]Primary
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Wrapper + Top Level Control
• Blocks will be scan-tested independently, i.e. in isolation of each other• Top-level test control (scan enable, test mode selection) have to be implemented for each block
Courtesy of M. Garcia-Sciveres *
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Wrapper Isolation Cells
Provide the application of the test stimuli at the embedded IP inputs as well as the observability at the embedded IP outputs
s1
r2
m 1
inte rconnectionresponse
IP teststim ulus
d_ in 0
1
r1
m 2
inte rconnectionstim ulus
IP testresponse
d_out
0
1s2IP
Te s t S h e ll
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Wrapper Cells in the Nutshell
Input isolation Output isolation
0d _ in
s tc ks c ane n a b le
F Fs ca n_ in
s ca n_ o u t
IP inp u t
Test Shells c i
D
0
sco
d_outIP output
Test Shell
stckscan enable
s c a n _ i n F F s c a n _ o u t
D
Note: Only the combinatorial inputs require isolation
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Outline
• Introduction• DfT Architecture• DfT Flow• Back-end Test Development• Future Work
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Two-pass Synthesis or mapped flowRead Netlist, Libraries
and CTL files
Create Scan Protocols,Specify Scan Path
Pre-ScanDfTCheck
PreviewDfT
Insert Scan Path
Post-ScanDfT Check
Handoff Design
Violations ?Violations ?
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Synopsys DfT Compiler
Synopsys DfT CompilerLibrary
Test Constraints(.tcl)
Netlist(.v)
Control Script(.tcl)
Listings Scannable Netlist(.v) STIL/CTL
test protocol
Synopsys Internal databasel
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DfT Procedures in the nutshell• PROC_dft_insert_init
– Global setup for dft insertion• PROC_read_design
– Reads netlists and libraries and builds the design
• PROC_create_protocol_for_test– Invokes the test constraints and builds the test protocols
• PROC_insert_scan– Insert scan chains (preview_dft and insert_dft)
• PROC_handoff_design– Write result to verilog, db, and test model (STIL/CTL) files
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Scan Chain reports for the EOCHL
• 1 scan chain, length= 2927• Standard DfT signals: si, so, se• Clocked with an additional test clock (tck) –clock
gating with functional clocks performed at the top level of the IP
• Additional DfT signal tm (to enable the test clock)
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This flow has to be executed at the design level containing EOCHL, CMD and wrapper isolation
A plan is to use Synopsys TetraMax ATPG tool
ATPG flow
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Test Patterns
• Continuity test patterns– To check the scan chain structures themsleves, typically
11101000 sequence is shifted through• Scan chain patterns for stuck-at faults
Optionally:• IDDQ patterns• Transition/Path delay fault patterns • Bridge patterns
The TetraMax ATPG is expected to generate the following:
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Outline
• Introduction• DfT Architecture• DfT Flow• Back-end Test Development• Future Work
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Test Assembly ProcessThe main purpose is to:• Assemble the test patterns of the IP(s) in the IC• Convert these patterns into the real test vectors• Generate the test bench for the simulation with both stimuli and response• Include the timing and wave information
WaveForm {
Pin = rzClocks;
Drive = RZ, t1, t2;
}
WaveForm {Pin = outputs;Expect = SB, t1, t2;
}
WaveForm {
Pin = inputs;
Drive = NR, tdel;
}
tdel
vector
waveform
tdel
t
period
t1
vector
waveform
t2
t
period
t1
vector
waveform
t2
t
period
t1 t2
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Back-End Test Development Flow
behavior models
Test patterns
TestAssembly
tester specific vectors
test bench
Simulator
netlist
DfT
Abstractions
test lib
•waveform generation•functional test
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Test Setup
DUT
Wafer Test
ATE, Test Setup
Lab Setup
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Future Work concerning the test development flow with scan chains
• Create the Wrapper around CMD and EOCHL blocks• Run the ATPG at this level• Back-end test development
– Link to lab setup– Link to tester vectors running at tester platform (Verigy?
Teradyne? Or … ?)• Mixed-Signal Test