Test structures for the evaluation of TowerJazz 180 nm CMOS Imaging Sensor technology
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Transcript of Test structures for the evaluation of TowerJazz 180 nm CMOS Imaging Sensor technology
Test structures for the evaluation of TowerJazz 180 nm CMOS Imaging Sensor technology
ALICE ITS microelectronics team - CERN
TID_TJ180 layout3.7 mm
2.2
mm
CMOS test structures CMOS test structureswith Deep p-well
Breakdown diodes
ALICE ITS microelectronics team - CERN
Tower Jazz 0.18 um CMOS Imaging Sensor
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CMOS test structures
2.0 mm
1.2 mm
16 x 8 pad matrix = 128 padsPad opening size: 76 μm x 76 μm
Each block has an individual power supply and it can be tested individually.
Block A
Block B
Block C
Block D
16
7 μ
m,
10
0 μ
m,
16
7 μ
m,
12
5 μ
m,
16
7 μ
m,
10
0 μ
m,
16
7 μ
m
125 μm
ALICE ITS microelectronics team - CERN
125 μm horizontal pitch100 μm, 125 μm, 167 μm vertical pitch
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MOS devicesGate oxide option Threshold Voltage (Vt) option
Thickness tox (nm) MOS voltage Zero Vt Standard Vt Medium Vt High Vt
3.0NMOS 1.8 V nmos_native nmos_18 - n18hvtPMOS 1.8 V - pmos_18 - p18hvt
7.0NMOS 3.3 V nmos_native_33 nmos_33 n33mvt -PMOS 3.3 V - pmos_33 p33mvt -
* Low Vt transistors cannot be used in a design with High Vt transistors
• 78 MOS with different sizes and tox and Vth options
Layout examples
NMOS in a Triple Well (Deep N-Well)for P-well isolation and noise immunity
NMOS
Enclosed Layout NMOS
PMOS
1 mm
ALICE ITS microelectronics team - CERN4
MOS test structures arrays
ALICE ITS microelectronics team - CERN
• Extraction of effective L.• Radiation effect dependency on the gate length.
L array:W = 10 mm, different L
• Extraction of effective W.• Study of the Radiation Induced Narrow Channel
Effect (RINCE).
W array:L = 0.18 mm, different W
• Study of the transistor behaviour as a function of the size.W/L = 10
• Noise measurement. (NMOS in triple well)W/L = 600
Array Purpose
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Other devices
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6 FOXFETs, W = 200 µm Nwell/Nwell (polysilicon gate) L=1.40(min) mm, 2.10 mm
N+diff/N+diff (alluminium gate) L=0.44(min) mm, 0.66 mm
N+diff/Nwell (alluminium gate) L=0.43(min) mm, 0.64 mm
2 ResistorsHigh ohmic P-type unsilicided poly resistor, W = 1 mm
L = 10 mm (11.0 kW), 20 mm (21.6 kW)
2 Diodes p+ in N-Well, Area = 2025 mm2 1350 mm x 1.5 mm, 45 mm x 45 mm
4 Capacitors Metal Insulator Metal : 960 x (5 mm x 5 mm) = 0.24 mm2 28.0 pF (single), 55.1 pF (double stack)
Nwell accumulation: 126 x (5 mm x 5 mm) = 0.35 mm2 28.9 pF (1.8 V), 16.0 pF (3.3 V)
Breakdown diodes
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Cross section nwell diode
nwell with deep pwell in the between
Measurements: Breakdown voltage and depletion layer capacitance
depletedvolume
depletedvolume
p+ : -30 V; n+ : 0 V
NW width: 1 µm or 2 µm NW with DPW width: up to 3.40 µm
Single Event Effects evaluation test chip
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SP_RAM
DP_RAM
SHIFTREGISTER
MUX
DATA_IN[15:0]
CONTROLSIGNALS
ADDRESS[14:0]
SP_RAM DATA_OUT
[15:0]
DP_RAM DATA_OUT
[15:0]
SRDATA_OUT
[15:0]
MULTIPLEXERSELECTOR
[1:0]
DATA_OUTPUT[15:0]
CLOCK
- SP RAM: 16 macro blocks, 1024 x 16 bit- DP RAM: 8 macro blocks, 2048 x 16 bit- 16 bit 32 K stages D-Flip-Flop shift register
ALICE_ITS_TJ180_T1
SEU_TJ180 layout
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4872 µm
4454 µm
SP_RAM
DP_RAMShift Register