Test Results for the CT Sigma-Delta Modulator
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Test Results for the CT Sigma-Delta Modulator Yi Zhang Advisor: Prof. Gabor Temes June 6, 2014 1
description
Test Results for the CT Sigma-Delta Modulator. Yi Zhang Advisor: Prof. Gabor Temes June 6, 2014. Block Diagram. Reference switching ELD compensation [1] Multi-bit FIR Feedback. Test Setup. Die Microphotograph. Measured Output Spectrum. # of FFT: 65536 15 averages. DWA on vs. DWA off. - PowerPoint PPT Presentation
Transcript of Test Results for the CT Sigma-Delta Modulator
Test Results for the CT Sigma-Delta Modulator
Yi Zhang
Advisor: Prof. Gabor Temes
June 6, 2014
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Block Diagram• Reference switching ELD compensation [1]
• Multi-bit FIR Feedback
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1
S
k
sT2
S
k
sT
3
S
k
sT
F(z) C(z)
Reference switching
VIN
VOUT2-bit QTZ
DAC1
DAC2 DAC3
2ffk
1ffkfk
resk
DWA
3
4z
1
2z
Test Setup
3
BPF
CLKIN
LVDS
Logic Analyzer
VREF
RC Tuning
data/clk o/p
AWG
RF Src.
Balun
CTDSMADC 100
Synchronization
Control
Power Box
6062A
E4433B
TLA7012
Allen Avionics
Die Microphotograph
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Measured Output Spectrum
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105
106
107
108
-120
-100
-80
-60
-40
-20
0
AD
C O
utp
ut
PS
D [
dB
]
Frequency [Hz]
PSD of a 3rd-Order Multibit FIR CTSDM (detail)
Ain = -1.58dBFSFin = 500kHz
SNDR = 74.3dBSNR = 77.3dB
SFDR = 80.4dB
BW=15MHz
# of FFT: 6553615 averages
DWA on vs. DWA off
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105
106
107
108
-100
-80
-60
-40
-20
0
AD
C O
utp
ut
PS
D [
dB
]
Frequency [Hz]
DWA onDWA off
106
-110
-105
-100
-95
-90
-85
AD
C O
utp
ut
PS
D [
dB
]
Frequency [Hz]
non-linear ISI error1.3 dB degraded when DWA on
[Karthik, 2014]
Cont’d
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105
106
107
108
-120
-100
-80
-60
-40
-20
0PSD of a 3rd-Order Multibit FIR CTSDM (detail)
AD
C O
utp
ut
PS
D [
dB
]
Frequency [Hz]
Ain = -1.9dBFSFin = 1000kHz
SNDR = 74.2dBSNR = 77.2dB
SFDR = 80.9dB
Cont’d
8
105
106
107
108
-120
-100
-80
-60
-40
-20
0PSD of a 3rd-Order Multibit FIR CTSDM (detail)
AD
C O
utp
ut
PS
D [
dB
]
Frequency [Hz]
Ain = -2.1dBFSFin = 2000kHz
SNDR = 74.2dBSNR = 76.3dB
SFDR = 82.2dB
Cont’d
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105
106
107
108
-120
-100
-80
-60
-40
-20
0PSD of a 3rd-Order Multibit FIR CTSDM (detail)
AD
C O
utp
ut
PS
D [
dB
]
Frequency [Hz]
Ain = -2.0dBFSFin = 3900kHz
SNDR = 73.7dBSNR = 76.4dB
SFDR = 78.9dB
SNDR/SNR vs. Input Amplitude
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-10 -5 066
68
70
72
74
76
78
Input Amplitude [dBFS]
SN
DR
, SN
R [
dB
]
SNR, 500kHzSNDR, 500kHzSNDR, 1MHzSNDR, 2MHzSNDR, 3.9MHz
-80 -60 -40 -20 0-10
0
10
20
30
40
50
60
70
80
Input Amplitude [dBFS]
SN
DR
, SN
R [
dB
]
SNR, 500kHzSNDR, 500kHz
Input Amplitude [dBFS] Input Amplitude [dBFS]
-5 00-20-40-60-80-10
0
10
20
30
40
50
60
70
80
SN
DR
, SN
R [
dB
]
SN
DR
, SN
R [
dB
]
78
76
74
72
70
68
-10DR = 79.4 dB
On-Chip Tuning
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0 1 2 3 4 5 6 756
58
60
62
64
66
68
70
72
74
76
On-Chip Cap. Tuning Bit
SN
DR
[d
B]
000 001 010 011 100 101 110 111
FoMxx = Power/(2(xx-1.76)/6.02 x 2 BW)
Performance Comparison
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[2] [3] [4] [5] [6]
ISSCC2006
ISSCC2009
ISSCC2010
ISSCC2012
ISSCC2013
Technology 130nm 65nm 65nm 90nm 28nm
Area (mm2) 1.2 0.15 0.07 0.12 0.08
VDD (V) 1.2 1.2/1.3 n/a 1.2 1.2/1.5
Fs (MHz) 640 250 1152 3600 640
BW (MHz) 20 20 18 25 18
Fin (MHz) 1 4 3.7 3.9 1 10 0.625
SNR (dB) 77.2 76.4 73 62 76 80.2 75.4
SNDR (dB) 74.1 73.7 74 60 73 73.3 73.6
DR (dB) 78.8 78.1 80.0 68.0 n/a 86.0 78.1
ENOB 12.0 12.0 12.0 9.7 11.8 11.9 11.9
FoM1SNDR (fJ) 56.0 58.6 122.1 321.2 129.4 79.4 27.7
FoM1SNR (fJ) 39.2 43.0 137.0 255.2 91.6 35.9 22.5
FoM1DR (fJ) 32.6 35.3 61.2 127.9 n/a 18.4 16.5
FoM2Schreier
(dB)172.1 171.4 170.0 160.8 n/a 178.2 174.7
1200
This Work
65nm
0.16
1.0
0.5
Power (mW) 6.96
4.31 (Ana.)
20 17 3.92.18 (Dig.)
0.47 (Ref.)
15
1510.5
30.4
172.7
77.3
74.3
79.4
12.0
38.7
54.7
[2] Mitteregger 06[3] Dhanasekaran 09[4] Taylor 10[5] Shettigar 12[6] Shu 13
FoMSchreier = DR + 10 x log10(BW/P)
Test PCB Board
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Test Environment
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Reference
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1. Y. Zhang, C-H Chen, and G. Temes.: “Efficient technique for excess loop delay compensation in continuous-time ∆Σ modulators”, Electron. Lett., vol. 49, no. 24,pp. 1522-1523, 2013
2. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 14b 20mW 640MHz CMOS CT ∆Σ ADC with 20MHz Signal Bandwidth and 12b ENOB,” ISSCC Dig. Tech. Papers, pp. 131-140, Feb. 2006
3. V. Dhanasekaran, et al., “ A 20 MHz BW 68 dB DR CT sigma delta ADC based on a multi-bit time-domain quantizer and feedback element,” ISSCC Dig. Tech. Papers, pp. 174-175, Feb. 2009
4. G. Taylor and I. Galton, “ A Mostly Digital Variable-Rate Continuous Time ADC ∆Σ Modulator,” ISSCC Dig. Tech. Papers, pp. 298-299, Feb. 2010
5. P. Shettigar and S. Pavan, “A 15mW 3.6GS/s CT-∆Σ ADC with 36MHz Bandwidth and 83dB DR in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 156-157, Feb. 2012.
6. Y. Shu, J. Tsai, P. Chen, T. Lo, P. Chiu, “A 28fJ/conv-step CT ∆Σ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer,” ISSCC Dig. Tech. Papers, pp 268-269, Feb 2013.
Thank You
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