Tessent FastScan Silicon Test and Yield Analysis
2
D A T A S H E E T www.mentor.com Silicon Test and Yield Analysis Tessent FastScan Advanced Automatic Test Pattern Generation Industry Leading ATPG Mentor Graphics Tessent ™ FastScan ™ is an automatic test pattern generation (ATPG) solution with a wide range of fault models, comprehensive design rule checks, extensive clocking support, and innovative algorithms for performance- oriented pattern compaction. It simplifies the process of generating high-coverage test sets. Its ability to be applied to most any type of design makes it the most versatile ATPG solution available. At-Speed Testing Current fabrication processes result in a population of speed-related failures that require detection through advanced test techniques. A comprehensive at-speed test solution is critical to ensure high-quality test. Tessent FastScan’s at-speed solu- tion includes transition, multiple detect transition, timing-aware, and critical path testing. Transition testing looks for delays on nodes at each gate, targeting the entire design for speed-related defects. Tessent FastScan’s critical-path analysis capabili- ties generate robust sequential patterns to detect defects along a design’s critical paths. Timing-aware patterns are similar to transition patterns but they use SDF timing information to target faults along the longest paths. Key Benefits • Delivers high performance ATPG for designs with struc- tured scan. • Reduces run time with no effect on coverage or pattern count using distributed ATPG. • Maximizes test coverage by minimizing the impact of Xs caused by false and multi- cycle paths. • Identifies testability problems early using comprehensive design rule checking. • Reduces test validation time with automatic simulation mismatch debugging. • Ensures shorter time to market with integration into all design flows and foundry support. • Mentor Graphics award- winning customer support. ensures success. Key Features • Extensive fault model support, including stuck-at, IDDQ, transition, path delay and bridge. • On-chip PLL support for accurate at-speed test. • MacroTest option automates testing small embedded memo- ries and cores with scan. • Supported in the Tessent SoCScan hierarchical silicon test environment. Interface for viewing and correcting testability problems.
Transcript of Tessent FastScan Silicon Test and Yield Analysis
D A T A S H E E T
www.mentor.com
Silicon Test and Yield AnalysisTessent FastScan Advanced Automatic Test Pattern Generation
Industry Leading ATPGMentor Graphics Tessent™ FastScan™ is an automatic test pattern generation (ATPG) solution with a wide range of fault models, comprehensive design rule checks, extensive clocking support, and innovative algorithms for performance-oriented pattern compaction. It simplifies the process of generating high-coverage test sets. Its ability to be applied to most any type of design makes it the most versatile ATPG solution available.
At-Speed TestingCurrent fabrication processes result in a population of speed-related failures that require detection through advanced test techniques. A comprehensive at-speed test solution is critical to ensure high-quality test. Tessent FastScan’s at-speed solu-tion includes transition, multiple detect transition, timing-aware, and critical path testing.
Transition testing looks for delays on nodes at each gate, targeting the entire design for speed-related defects. Tessent FastScan’s critical-path analysis capabili-ties generate robust sequential patterns to detect defects along a design’s critical paths. Timing-aware patterns are similar to transition patterns but they use SDF timing information to target faults along the longest paths.
Key Benefits
• DelivershighperformanceATPG for designs with struc-tured scan.
• Reducesruntimewithnoeffect on coverage or pattern count using distributed ATPG.
• MaximizestestcoveragebyminimizingtheimpactofXscaused by false and multi-cycle paths.
• Identifiestestabilityproblemsearly using comprehensive design rule checking.
• Reducestestvalidationtimewith automatic simulation mismatch debugging.
• Ensuresshortertimetomarketwith integration into all design flows and foundry support.
• MentorGraphicsaward- winning customer support. ensures success.
Key Features
• Extensivefaultmodelsupport,including stuck-at, IDDQ, transition, path delay and bridge.
• On-chipPLLsupportfor accurate at-speed test.
• MacroTestoptionautomatestesting small embedded memo-ries and cores with scan.
• SupportedintheTessent SoCScan hierarchical silicon test environment.
Interface for viewing and correcting testability problems.
10-09-MGC 1027510
Visit our website at www.mentor.comCopyright © 2009 Mentor Graphics Corporation. Mentor products and processes are registered trademarks of Mentor Graphics Corporation.All other trademarks mentioned in this document are trademarks of their respective owners.
Corporate HeadquartersMentor Graphics Corporation8005 S.W. Boeckman RoadWilsonville, Oregon 97070-7777Phone: 503-685-7000Fax: 503-685-1204
Sales and Product InformationPhone: 800-547-3000
Silicon ValleyMentor Graphics Corporation1001 Ridder Park DriveSan Jose, California 95131 USAPhone: 408-436-1500Fax: 408-436-1501
North American Support CenterPhone: 800-547-4303
Europe Mentor Graphics Deutschland GmbHArnulfstrasse 20180634 MunichGermanyPhone: +49.89.57096.0Fax: +49.89.57096.400
Pacific Rim Mentor Graphics TaiwanRoom 1001, 10F, International Trade BuildingNo. 333, Section 1, Keelung RoadTaipei, Taiwan, ROCPhone: 886-2-87252000Fax: 886-2-27576027
Japan Mentor Graphics Japan Co., Ltd.Gotenyama Garden7-35, Kita-Shinagawa 4-chomeShinagawa-Ku, Tokyo 140 -0001JapanPhone: 81-3-5488-3033Fax: 81-3-5488-3004
Tessent FastScan supports the use of on-chipPLLsfordeliveringaccurateat-speed clock edges. With input on the clockingproceduresforthePLL,itcangenerate accurate at-speed tests using the design’s on-chip clocks.
Tessent FastScan reduces the effect that unknownstates(Xs)haveontestcover-age by intelligently handling false and multicycle paths.
Test Pattern CompactionTessent FastScan is known for delivering high-coverage, compact test sets. How-ever, with the growing need to improve test quality and with at-speed patterns becoming a standard, the amount of test data can still be an issue. In cases where test data volumes exceed automatic test equipment limits or vendor requirements, Tessent TestKompress® and embedded deterministic test (EDT)offerauniquesolution.Becausebothproductssharethe same efficient ATPG engine, the migration to compres-sion is simplified.
Testability Analysis and Debug A visual debug utility is integrated within Tessent FastScan for viewing and correcting testability problems. Visual-izerpresentsthedesigninvariousviewssuchasschematic,design structure, waveform, library, data, hierarchy, and ad-ditional views to facilitate viewing and troubleshooting.
TheintuitiveinterfacebuiltintoVisualizeralsoallowsview-ing of the session transcript which includes active links for design rule violations, logic displays, file editing, documen-tation, and gate callouts. ATPG statistics reporting provides detailed analysis of untestable faults and classifies them into recognizablecategoriesthatsimplifythedebuggingoflowtest coverage issues.
Hierarchical Logic Test Strategy with Tessent SoCScanTessent FastScan can be used with Tessent SoCScan to take advantage of the Mentor Graphics automated hierarchical test integration and test generation flow. Tessent SoCScan makes use of shared isolation and capture-by-domain tech-nologies to deliver independent core-level ATPG and chip-level pattern reuse. Tessent SoCScan also provides access to BurstModetechnologyforhigherat-speedtestcoverageandimproved power managment.
Tessent Silicon Test and Yield Analysis SolutionsTessent FastScan is part of the Mentor Graphics industry- and technology-leading tool suite for silicon test and yield analysis. The Tessent suite includes integrated solutions for test insertion; automatic test pattern generation (ATPG); on-chip compression; memory, logic, and mixed-signal built-in self-test(BIST);siliconbring-up,anddiagnosis-drivenyieldanalysis.AllTessenttoolsareavailableonUNIXandLinux.For more information, visit www.mentor.com.
MacroTest creates tests for small embedded register arrays without adding additional memory test logic around the array.
