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•

DEPARTMENT OF COMMUNICATION SKILLS

Certificate

 This is to Certify that this project report on ‘VLSI’ is

the bonafide work of 

BANGERA CHANDAN 

who carried out the project work successfully under my supervision.

Signature Signature

Mr. KHEDEKAR Mr. Ganesh Shinde

Information Technology Dept. of Communication

Skills

GIT, Lavel GIT, Lavel

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ACKNOWLEDGEMENT

It gives us a great a pleasure to present our project report on ‘VLSI’ as

per the requirement of the course Second Year Electronics And

 Telecommunication (Sem-III) from the University of Mumbai at the Gharda

Institute of Technology, Lavel.

First of all we are hearty thankful to our project conductor and guide

Mr. Ganesh Shinde for selecting this project.

We express thanks to Mr. Ganesh Shinde, lecturer, Department of 

Communication Skills for his time-to-time help, support and guidance tocomplete this project report successfully.

We would also like to thanks Mr. Khedekar, H.O.D. of Electronics And

 Telecommunication and our Principal Mr. Ajoy Kumar of our college.

Lastly we would like to thanks all the staff members of Gharda Institute

of Technology for their help to provide information to complete this project

report.

 

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TABLE OF CONTENTS

CHAPTERNO.

TITLE PAGENO.

Acknowledgement

List of ContentsList of IllustrationsAbstract

1. Introduction2. Very Large Scale Integration3. Invention

4. Generation5. Advanced Tools For Design6. Global Expansion7. Manufacturing8. Notable IC’s11. Conclusion12. References13. Appendix14. Glossary

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LIST OF ILLUSTRATIONS

Figure No. Name of the Diagram PageNo.

1. Integrated Circuit 52. Atmel Diopsis 740 53. EPROM 64. VLSI IC die 75.  Jack Kilby's original integrated circuit 96. Upper interconnect layers on an Intel 80486DX2

microprocessor die.11

7. Early WSI attempt by Trilogy Systems 138. AMD Geode is an x86 compatible system-on-a-

chip14

9. Microcontroller-based System-on-a-Chip 1510. System-on-a-Chip Design Flow 1611. A VLSI VL82C106 Super I/O chip 1812. NASA's Glenn Research Center cleanroom. 2213. Synthetic detail of a standard cell through four

layers of planarized copper interconnect, down tothe polysilicon (pink), wells (greyish) andsubstrate (green).

25

14. Fabrication 2815. Schematic structure of a CMOS chip, as built in

the early 2000s.29

16. Early USSR-made integrated circuit 3017. Intel 4004, the first general-purpose, commercial

microprocessor33

18. Atmel AT90S2333 microcontroller 3519 Atmel ATMEGA32 microcontroller 35

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Introduction

Synthetic detail of an integrated circuit through four

layers of planarized copper interconnect, down to the

polysilicon (pink), wells (greyish), and substrate

(green).

Integrated circuits were made possible by experimental discoveries which showed thatsemiconductor devices could perform the functions of vacuum tubes and by mid-20th-centurytechnology advancements in semiconductor device fabrication. The integration of large numbersof tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using electronic components. The integrated circuit's mass production capability,reliability, and building-block approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete transistors.

There are two main advantages of ICs over discrete circuits: cost and performance. Cost is low because the chips, with all their components, are printed as a unit by photolithography and notconstructed as one transistor at a time. Furthermore, much less material is used to construct a

circuit as a packaged IC die than as a discrete circuit. Performance is high since the componentsswitch quickly and consume little power (compared to their discrete counterparts) because thecomponents are small and close together. As of 2006, chip areas range from a few squaremillimeters to around 350 mm2, with up to 1 million transistors per mm2.

Integrated circuit

Integrated circuit of Atmel Diopsis 740 System on

Chip showing memory blocks, logic and input/output

pads around the periphery

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Figure 1: Integrated Circuit

Figure 2:Atmel Diopsis 740

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Figure 3:EPROM

Microchips (EPROM memory) with a transparent window, showing the integrated

circuit inside. Note the fine silver-colored wires that connect the integrated circuit to

the pins of the package. The window allows the memory contents of the chip to be

erased, by exposure to strong ultraviolet light in an eraser device.

In electronics, an integrated circuit (also known as IC, microcircuit, microchip, silicon chip,or chip) is a miniaturized electronic circuit (consisting mainly of semiconductor devices, as wellas passive components) that has been manufactured in the surface of a thin substrate of semiconductor material. Integrated circuits are used in almost all electronic equipment in usetoday and have revolutionized the world of electronics. Computers, cellular phones, and other digital appliances are now inextricable parts of the structure of modern societies, made possible by the low cost of production of integrated circuits.

A hybrid integrated circuit is a miniaturized electronic circuit constructed of individualsemiconductor devices, as well as passive components, bonded to a substrate or circuit board. Amonolithic integrated circuit is made of devices manufactured by diffusion of trace elements intoa single piece of semiconductor substrate, a chip.

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Very-large-scale integration

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combiningthousands of transistors into a single chip. VLSI began in the 1970s when complexsemiconductor and communication technologies were being developed. The microprocessor is aVLSI device. The term is no longer as common as it once was, as chips have increased incomplexity into billions of transistors.

The first semiconductor chips held two transistors each.

Subsequent advances added more and more transistors, and,as a consequence, more individual functions or systemswere integrated over time. The first integrated circuits heldonly a few devices, perhaps as many as ten diodes,transistors, resistors and capacitors, making it possible tofabricate one or more logic gates on a single device. Nowknown retrospectively as  small-scale integration (SSI),improvements in technique led to devices with hundreds of 

logic gates, known as medium-scale integration (MSI). Further improvements led to large-scaleintegration (LSI), i.e. systems with at least a thousand logic gates. Current technology has movedfar past this mark and today's microprocessors have many millions of gates and billions of 

individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale integrationabove VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot.Terms suggesting greater than VLSI levels of integration are no longer in widespread use. EvenVLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSIor better.

As of early 2008, billion-transistor processors are commercially available. This is expected to become more commonplace as semiconductor fabrication moves from the current generation of 

65 nm processes to the next 45 nm generations (while experiencing new challenges such asincreased variation across process corners). Another notable example is Nvidia's 280 series GPU.This GPU is unique in the fact that almost all of its 1.4 billion transistors are used for logic, incontrast to the Itanium, whose large transistor count is largely due to its 24 MB L3 cache.Current designs, as opposed to the earliest devices, use extensive design automation andautomated logic synthesis to lay out the transistors, enabling higher levels of complexity in theresulting logic functionality. Certain high-performance logic blocks like the SRAM(StaticRandom Access Memory) cell, however, are still designed by hand to ensure the highest

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Figure 4: VLSI IC die

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efficiency (sometimes by bending or breaking established design rules to obtain the last bit of  performance by trading stability).

VLSI Technology

VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drivein San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of theapplication-specific integrated circuit (ASIC) business, which accelerated the push of powerfulembedded systems into affordable products.

The company was founded in 1979 by a trio from Fairchild Semiconductor  by way of Synertek -Jack Balletto, Dan Floyd, Gunnar Wetlesen - and by Doug Fairbairn of Xerox PARC andLambda (later VLSI Design) magazine.

Alfred J. Stein became the CEO of the company in 1982. Subsequently VLSI built its first fab inSan Jose; eventually a second fab was built in San Antonio, Texas.

VLSI had its initial public offering in 1983, and was listed on the stock market as( NASDAQ: VLSI).

The company was later acquired by Royal Philips and survives to this day as part of  NXPSemiconductors.

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Invention

Early developments of the integrated circuit go back to 1949, when the German engineer Werner Jacobi (Siemens AG) filed a patent for an integrated-circuit-like semiconductor amplifyingdevice showing five transistors on a common substrate arranged in a 2-stage amplifier arrangement. Jacobi discloses small and cheap hearing aids as typical industrial applications of his patent. A commercial use of his patent has not been reported.

The idea of the integrated circuit was conceived by a radar scientist working for the Royal Radar Establishment of the British Ministry of Defence, Geoffrey W.A. Dummer (1909–2002), who published it at the Symposium on Progress in Quality Electronic Components in Washington,D.C. on May 7, 1952. He gave many symposia publicly to propagate his ideas. Dummer unsuccessfully attempted to build such a circuit in 1956.

A precursor idea to the IC was to create small ceramic squares (wafers), each one containing asingle miniaturized component. Components could then be integrated and wired into a bidimensional or tridimensional compact grid. This idea, which looked very promising in 1957,was proposed to the US Army by Jack Kilby, and led to the short-lived Micromodule Program(similar to 1951's Project Tinkertoy). However, as the project was gaining momentum, Kilbycame up with a new, revolutionary design: the IC.

Robert Noyce credited Kurt Lehovec of Sprague Electric for the principle of  p-n junction

isolation caused by the action of a biased p-n junction (the diode) as a key concept behind the IC.

Jack Kilby recorded his initial ideas concerning theintegrated circuit in July 1958 and successfullydemonstrated the first working integrated circuit onSeptember 12, 1958. In his patent application of February 6,1959, Kilby described his new device as “a body of semiconductor material ... wherein all the components of the electronic circuit are completely integrated.” Kilby wonthe 2000 Nobel Prize in Physics for his part of the invention

of the integrated circuit.

Robert Noyce also came up with his own idea of an integrated circuit half a year later than Kilby. Noyce's chip solved many practical problems that Kilby's had not. Noyce's chip, made atFairchild Semiconductor , was made of silicon, whereas Kilby's chip was made of germanium.

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Figure 5:Jack Kilby's originalintegrated circuit

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Generations

SSI, MSI and LSI

The first integrated circuits contained only a few transistors. Called "Small-Scale Integration"(SSI), digital circuits containing transistors numbering in the tens provided a few logic gates for example, while early linear ICs such as the Plessey SL201 or the Philips TAA320 had as few astwo transistors. The term Large Scale Integration was first used by IBM scientist Rolf Landauer when describing the theoretical concept, from there came the terms for SSI, MSI, VLSI, andULSI.

SSI circuits were crucial to early aerospace projects, and vice-versa. Both the Minuteman missileand Apollo program needed lightweight digital computers for their inertial guidance systems; theApollo guidance computer led and motivated the integrated-circuit technology, while theMinuteman missile forced it into mass-production. The Minuteman missile program and variousother Navy programs accounted for the total $4 million integrated circuit market in 1962, and by1968, U.S. Government space and defense spending still accounted for 37% of the $312 milliontotal production. The demand by the U.S. Government supported the nascent integrated circuitmarket until costs fell enough to allow firms to penetrate the industrial and eventually theconsumer markets. The average price per integrated circuit dropped from $50.00 in 1962 to$2.33 in 1968. Integrated Circuits began to appear in consumer products by the turn of thedecade, a typical application being FM inter-carrier sound processing in television receivers.

The next step in the development of integrated circuits, taken in the late 1960s, introduceddevices which contained hundreds of transistors on each chip, called "Medium-Scale

Integration" (MSI).

They were attractive economically because while they cost little more to produce than SSIdevices, they allowed more complex systems to be produced using smaller circuit boards, lessassembly work (because of fewer separate components), and a number of other advantages.

Further development, driven by the same economic factors, led to "Large-Scale Integration"(LSI) in the mid 1970s, with tens of thousands of transistors per chip.

Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors, that began to be manufactured in moderate quantities in the early 1970s, had under 4000 transistors.

True LSI circuits, approaching 10000 transistors, began to be produced around 1974, for computer main memories and second-generation microprocessors.

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The final step in the development process, starting in the1980s and continuing through the present, was "very large-scale integration" (VLSI). The development started withhundreds of thousands of transistors in the early 1980s, andcontinues beyond several billion transistors as of 2009.

Multiple developments were required to achieve thisincreased density. Manufacturers moved to smaller rules andcleaner fabs, so that they could make chips with moretransistors and maintain adequate yield. The path of processimprovements was summarized by the InternationalTechnology Roadmap for Semiconductors (ITRS). Design

tools improved enough to make it practical to finish these designs in a reasonable time. The moreenergy efficient CMOS replaced NMOS and PMOS, avoiding a prohibitive increase in power consumption. Better texts such as the landmark textbook by Mead and Conway helped schoolseducate more designers, among other factors.

In 1986 the first one megabit RAM chips were introduced, which contained more than onemillion transistors. Microprocessor chips passed the million transistor mark in 1989 and the billion transistor mark in 2005. The trend continues largely unabated, with chips introduced in2007 containing tens of billions of memory transistors.

ULSI, WSI, SOC and 3D-IC

To reflect further growth of the complexity, the term ULSI that stands for "ultra-large-scaleintegration" was proposed for chips of complexity of more than 1 million transistors.

Wafer-scale integration (WSI) is a system of building very-large integrated circuits that uses anentire silicon wafer to produce a single "super-chip". Through a combination of large size andreduced packaging, WSI could lead to dramatically reduced costs for some systems, notablymassively parallel supercomputers. The name is taken from the term Very-Large-ScaleIntegration, the current state of the art when WSI was being developed.

A system-on-a-chip (SoC or SOC) is an integrated circuit in which all the components neededfor a computer or other system are included on a single chip. The design of such a device can becomplex and costly, and building disparate components on a single piece of silicon maycompromise the efficiency of some elements. However, these drawbacks are offset by lower manufacturing and assembly costs and by a greatly reduced power budget: because signalsamong the components are kept on-die, much less power is required (see Packaging).

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Figure 6:Upper interconnectlayers on an Intel 80486DX2

microprocessor die.

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A three-dimensional integrated circuit (3D-IC) has two or more layers of active electroniccomponents that are integrated both vertically and horizontally into a single circuit.Communication between layers uses on-die signaling, so power consumption is much lower thanin equivalent separate circuits. Judicious use of short vertical wires can substantially reduceoverall wire length for faster operation.

Wafer-scale integration

Wafer-scale integration, WSI for short, is a yet-unused system of building very-large integrated circuit networks that use an entire silicon wafer to produce a single "super-chip". Through acombination of large size and reduced packaging, WSI could lead to dramatically reduced costsfor some systems, notably massively parallel supercomputers. The name is taken from the termvery-large-scale integration, the current state of the art when WSI was being developed.

The concept

To understand WSI, one has to consider the normal chip-making process. A single largecylindrical crystal of silicon is produced and then cut into disks known as wafers. The wafers arethen cleaned and polished in preparation for the fabrication process. A photographic process isused to pattern the surface where material ought to be deposited on top of the wafer and wherenot to. The desired material is deposited and the photographic mask is removed for the nextlayer. From then on the wafer is repeatedly processed in this fashion, putting on layer after layer of circuitry on the surface.

Multiple copies of these patterns are deposited on the wafer in a grid fashion across the surfaceof the wafer. After all the possible locations are patterned, the wafer surface appears like a sheet

of graph paper, with grid lines delineating the individual chips. Each of these grid locations istested for manufacturing defects by automated equipment. Those locations that are found to bedefective are recorded and marked with a dot of paint. The wafer is then sawed apart to cut outthe individual chips. Those defective chips are thrown away, or recycled, while the workingchips are placed into packaging and re-tested for any damage that might occur during the packaging process.

Flaws on the surface of the wafers and problems during the layering/depositing process areimpossible to avoid, and cause some of the individual chips to be defective. The revenue fromthe remaining working chips has to pay for the entire cost of the wafer and its processing,including those discarded defective chips. Thus, the higher number of working chips or higher 

 yield , the lower the cost of each individual chip. In order to maximize yield one wants to makethe chips as small as possible, so that a higher number of working chips can be obtained per wafer.

The vast majority of the cost of fabrication (typically 30%-50%) is related to testing and packaging the individual chips. Further cost is associated with connecting the chips into anintegrated system (usually via a printed circuit board). Wafer-scale integration seeks to reduce

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this cost, as well as improve performance, by building larger chips in a single package – in principle, chips as large as a full wafer.

Of course this is not easy, since given the flaws on the wafers a single large design printed onto awafer would almost always not work. It has been an ongoing goal to develop methods to handle

faulty areas of the wafers through logic, as opposed to sawing them out of the wafer. Generally,this approach uses a grid pattern of sub-circuits and "rewires" around the damaged areas usingappropriate logic. If the resulting wafer has enough working sub-circuits, it can be used despitefaults.

Production attempts

Many companies attempted to develop WSI productionsystems in the 1970s and 80s, but all failed. TI and ITT bothsaw it as a way to develop complex pipelinedmicroprocessors and re-enter a market where they werelosing ground, but neither released any products.

Gene Amdahl also attempted to develop WSI as a method of making a supercomputer, starting Trilogy Systems in 1980

and garnering investments from Groupe Bull, Sperry Rand and Digital Equipment Corporation, 

who (along with others) provided an estimated $230 million in financing. The design called for a2.5" square chip with 1200 pins on the bottom.

The effort was plagued by a series of disasters, including floods which delayed the constructionof the plant and later ruined the clean-room interior. After burning through about 1/3rd of thecapital with nothing to show for it, Amdahl eventually declared the idea would only work with a99.99% yield, which wouldn't happen for 100 years. He used Trilogy's remaining seed capital to buy Elxsi in 1985, a maker of VAX-compatible machines. The Trilogy efforts were eventuallyended and "became" Elxsi.

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Figure 7:Early WSI attempt byTrilogy Systems

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System-on-a-chip

System-on-a-chip or system on chip (SoC or SOC) refersto integrating all components of a computer or other electronic system into a single integrated circuit (chip). Itmay contain digital, analog, mixed-signal, and often radio-frequency functions – all on a single chip substrate. Atypical application is in the area of embedded systems.

The contrast with a microcontroller is one of degree.Microcontrollers typically have under 100K of RAM (often just a few KBytes) and often really are single-chip-systems;whereas the term SoC is typically used with more powerful processors, capable of running software such as Windows or Linux, which need external memory chips (flash, RAM) to

 be useful, and which are used with various external peripherals. In short, for larger systemsSystem-on-a-chip is hyperbole, indicating technical direction more than reality: increasing chipintegration to reduce manufacturing costs and to enable smaller systems. Many interestingsystems are too complex to fit on just one chip built with a process optimized for just one of the

system's tasks.

When it is not feasible to construct an SoC for a particular application, an alternative is a systemin package (SiP) comprising a number of chips in a single package. In large volumes, SoC is believed to be more cost effective than SiP since it increases the yield of the fabrication and because its packaging is simpler.

Another option, as seen for example in higher end cell phones and on the Beagle Board, is package on package stacking during board assembly. The SoC chip includes processors andnumerous digital peripherals, and comes in a ball grid package with lower and upper connections. The lower balls connect to the board and various peripherals, with the upper balls in

a ring holding the memory busses used to access NAND flash and DDR2 RAM. Memory packages could come from multiple vendors.

•

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Figure 8:AMD Geode is an x86compatible system-on-a-chip

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Structure

A typical SoC consists of:

• One microcontroller, microprocessor or DSP core(s). Some SoCs – called

multiprocessor System-on-Chip (MPSoC) – include more than one processorcore.

• Memory blocks including a selection of ROM, RAM, EEPROM and flash.•  Timing sources including oscillators and phase-locked loops.• Peripherals including counter-timers, real-time timers and power-on reset 

generators.• External interfaces including industry standards such as USB, FireWire,

Ethernet, USART, SPI.• Analog interfaces including ADCs and DACs.• Voltage regulators and power management circuits.

These blocks are connected by either a proprietary or industry-standard bus such as the AMBA  bus from ARM. DMA controllers route data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC.

Design flow

An SoC consists of both the hardware 

described above, and the software thatcontrols the microcontroller , microprocessor  or DSP cores, peripherals and interfaces. Thedesign flow for an SoC aims to develop thishardware and software in parallel.

Most SoCs are developed from pre-qualifiedhardware blocks for the hardware elementsdescribed above, together with the softwaredrivers that control their operation. Of  particular importance are the protocol stacks 

that drive industry-standard interfaces likeUSB. The hardware blocks are put together using CAD tools; the software modules areintegrated using a software developmentenvironment.

A key step in the design flow is emulation: the hardware is mapped onto an emulation

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Figure 9:Microcontroller-based System-on-a-Chip

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 platform based on a field programmable gate array (FPGA) that mimics the behavior of the SoC,and the software modules are loaded into the memory of the emulation platform. Once programmed, the emulation platform enables the hardware and software of the SoC to be testedand debugged at close to its full operational speed. (Emulation is generally preceded byextensive software simulation. In fact, sometimes the FPGAs are used primarily to speed up

some parts of the simulation work.)

After emulation the hardware of the SoC follows the place and route phase of the design of anintegrated circuit before it is fabricated.

Chips are verified for logical correctness before being sent to foundry. This process is calledfunctional verification, and it accounts for a significant portion of the time and energy expendedin the chip design life cycle (although the often quoted figure of 70% is probably anexaggeration). Verilog and VHDL are typical hardware description languages used for verification. With the growing complexity of chips, hardware verification languages likeSystemVerilog, SystemC, e, and OpenVera are also being used. Bugs found in the verification

stage are reported to the designer.

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Figure 10:System-on-a-Chip Design Flow

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Fabrication

SoCs can be fabricated by several technologies, including:

• Full custom• Standard cell• FPGA

SoC designs usually consume less power and have a lower cost and higher reliability than themulti-chip systems that they replace. And with fewer packages in the system, assembly costs arereduced as well.

However, like most VLSI designs, the total cost is higher for one large chip than for the samefunctionality distributed over several smaller chips, because of lower yields and higher NRE 

costs.

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Advanced tools for VLSI design

The original business plan was to be a contract wafer fabricationcompany, but the venture investors wanted the company todevelop IC design tools to help fill the foundry.

Thanks to its Caltech and UC Berkeley students, VLSI was animportant pioneer in the electronic design automation industry. Itoffered a sophisticated package of tools, originally based on the

'lambda-based' design style advocated by Carver Mead and LynnConway.

VLSI became an early vendor of standard cell (cell-basedtechnology) to the merchant market in the early 80s where the other ASIC-focused company,LSI Logic, was a leader in gate arrays. Prior to VLSI's cell-based offering, the technology had been primarily available only within large vertically integrated companies with semiconductor units such as AT&T and IBM.

VLSI's design tools eventually included not only design entry and simulation but eventually cell- based routing (chip compiler), a datapath compiler, SRAM and ROM compilers, and a state

machine compiler. The tools were an integrated design solution for IC design and not just pointtools, or more general purpose system tools. A designer could edit transistor-level polygonsand/or logic schematics, then run DRC and LVS, extract parasitics from the layout and run Spicesimulation, then back-annotate the timing or gate size changes into the logic schematic database.Characterization tools were integrated to generate FrameMaker Data Sheets for Libraries. VLSIeventually spun off the CAD and Library operation into Compass Design Automation  but itnever reached IPO before it was purchased by Avanti Corp.

VLSI's physical design tools were critical not only to its ASIC business, but also in setting the bar for the commercial EDA industry. When VLSI and its main ASIC competitor, LSI Logic,were establishing the ASIC industry, commercially-available tools could not deliver the

 productivity necessary to support the physical design of hundreds of ASIC designs each year without the deployment of a substantial number of layout engineers. The companies'development of automated layout tools was a rational "make because there's nothing to buy"decision. The EDA industry finally caught up in the late 1980s when Tangent Systems releasedits TanCell and TanGate products. In 1989, Tangent was acquired by Cadence Design Systems(founded in 1988).

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Figure 11:A VLSIVL82C106 Super I/O chip

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Unfortunately, for all VLSI's initial competence in design tools, they were not leaders insemiconductor manufacturing technology. VLSI had not been timely in developing a 1.0 µmmanufacturing process as the rest of the industry moved to that geometry in the late 80s. VLSIentered a long-term technology parthership with Hitachi and finally released a 1.0 µm processand cell library (actually more of a 1.2 µm library with a 1.0 µm gate).

As VLSI struggled to gain parity with the rest of the industry in semiconductor technology, thedesign flow was moving rapidly to a Verilog HDL and synthesis flow. Cadence acquiredGateway, the leader in Verilog hardware design language (HDL) and Synopsys was dominatingthe exploding field of design synthesis. As VLSI's tools were being eclipsed, VLSI waited toolong to open the tools up to other fabs and Compass Design Automation was never a viablecompetitor to industry leaders.

Meanwhile, VLSI entered the merchant high speed static RAM SRAM market as they needed a product to drive the semiconductor process technology development. All the large semiconductor companies built high speed SRAMs with cost structures VLSI could never match. VLSI

withdrew once it was clear that the Hitachi process technology partnership was working.

ARM Ltd was formed in 1990 as a semiconductor intellectual property licensor, backed byAcorn, Apple and VLSI. VLSI became a licensee of the powerful ARM processor and ARMfinally funded processor tools. Initial adoption of the ARM processor was slow. Few applicationscould justify the overhead of an embedded 32 bit processor. In fact, despite the addition of further licensees, the ARM processor enjoyed little market success until they developed thenovel 'thumb' extensions. Ericsson adopted the ARM processor in a VLSI chipset for its GSMhandset designs in the early 1990s. It was the GSM boost that is the foundation of ARM thecompany/technology that it is today.

Only in PC chipsets, did VLSI dominate in the early 90s. This product was developed by fiveengineers using the 'Megacells" in the VLSI library that led to a business unit at VLSI thatalmost equaled its ASIC business in revenue. VLSI eventually ceded the market to Intel becauseIntel was able to package-sell its processors, chipsets, and even board level products together.

VLSI also had an early partnership with PMC, a design group that had been nurtured of BritishColumbia Bell. When PMC wanted to divest its semiconductor intellectual property venture,VLSI's bid was beaten by a creative deal by Sierra Semiconductor. The telecom business unitmanagement at VLSI opted to go it alone. PMC Sierra  became one of the most importanttelecom ASSP vendors.

Scientists and innovations from the 'design technology' part of VLSI found their way to CadenceDesign Systems (by way of Redwood Design Automation). Compass Design Automation(VLSI's CAD and Library spin-off) was sold to Avant! Corporation, which itself was acquired bySynopsys.

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Global expansion

VLSI maintained operations throughout the USA, and in Britain, France, Germany, Italy, Japan,Singapore and Taiwan. One of its key sites was in Tempe, Arizona, where a family of highlysuccessful chipsets was developed for the IBM PC.

In 1990, VLSI Technology, along with Acorn Computers and Apple Computer  were thefounding investing partners in ARM Ltd.

Ericsson of Sweden, after many years of fruitful collaboration, was by 1998 VLSI's largestcustomer, with annual revenue of $120 million. VLSI's datapath compiler (VDP) was the value-added differentiator that opened the door at Ericsson in 1987/8. The silicon revenue and GPMenabled by VDP must make it one of the most successful pieces of customer-configurable, non-memory silicon intellectual property (SIP) in the history of the industry. Within the WirelessProducts division, based at Sophia-Antipolis in France, VLSI developed a range of algorithmsand circuits for the GSM standard and for cordless standards such as the European DECT and theJapanese PHS. Stimulated by its growth and success in the wireless handset IC area, PhilipsElectronics acquired VLSI in June 1999, for about $1 billion. The former components survive tothis day as part of Philips spin-off  NXP Semiconductors.

Challenges

As microprocessors become more complex due to technology scaling, microprocessor designershave encountered several challenges which force them to think beyond the design plane, andlook ahead to post-silicon:

• Power usage/Heat dissipation – As threshold voltages have ceased to scale withadvancing process technology, dynamic power dissipation has not scaled proportionally.Maintaining logic complexity when scaling the design down only means that the power dissipation per area will go up. This has given rise to techniques such as dynamic voltageand frequency scaling (DVFS) to minimize overall power.

• Process variation – As photolithography techniques tend closer to the fundamental lawsof optics, achieving high accuracy in doping concentrations and etched wires is becomingmore difficult and prone to errors due to variation. Designers now must simulate acrossmultiple fabrication process corners  before a chip is certified ready for production.

• Stricter design rules – Due to lithography and etch issues with scaling, design rules for layout have become increasingly stringent. Designers must keep ever more of these rules

in mind while laying out custom circuits. The overhead for custom design is nowreaching a tipping point, with many design houses opting to switch to electronic designautomation (EDA) tools to automate their design process.

• Timing/design closure – As clock frequencies tend to scale up, designers are finding itmore difficult to distribute and maintain low clock skew between these high frequencyclocks across the entire chip. This has led to a rising interest in multicore andmultiprocessor  architectures, since an overall speedup can be obtained by lowering theclock frequency and distributing processing.

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• First-pass success – As die sizes shrink (due to scaling), and wafer  sizes go up (to lower manufacturing costs), the number of dies per wafer increases, and the complexity of making suitable photomasks goes up rapidly. A mask set for a modern technology cancost several million dollars. This non-recurring expense deters the old iterative philosophy involving several "spin-cycles" to find errors in silicon, and encourages first-

 pass silicon success. Several design philosophies have been developed to aid this newdesign flow, including design for manufacturing (DFM), design for test (DFT), andDesign for X

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Manufacturing

Semiconductor device fabrication

Figure 12:NASA's Glenn Research Center cleanroom.

Semiconductor device fabrication is the process used tocreate the integrated circuits (silicon chips) that are present in everyday electrical and electronic devices. It isa multiple-step sequence of photographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of puresemiconducting material. Silicon is the most commonly used semiconductor material today,along with various compound semiconductors.

The entire manufacturing process, from start to packaged chips ready for shipment, takes six toeight weeks and is performed in highly specialized facilities referred to as fabs.

•

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Semiconductor

manufacturing

processes

• 10 µm — 1971• 6 µm — 1974• 3 µm — 1975•

2 µm — 1979• 1.5 µm — 1982• 1 µm — 1985• 800 nm (0.80 µm) —

1989• 600 nm (0.60 µm) —

1994• 350 nm (0.35 µm) —

1995• 250 nm (0.25 µm) —

1998• 180 nm (0.18 µm) —

1999• 130 nm (0.13 µm) —

2000• 90 nm — 2002• 65 nm — 2006• 45 nm — 2008• 32 nm — 2010• 22 nm — approx. 2011• 16 nm — approx. 2013

• 11 nm — approx. 2015

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History

When feature widths were far greater than about 10 micrometres, purity was not the issue that itis today in device manufacturing. As devices became more integrated, cleanrooms became evencleaner. Today, the labs are pressurized with filtered air to remove even the smallest particles,which could come to rest on the wafers and contribute to defects. The workers in asemiconductor fabrication facility are required to wear cleanroom suits to protect the devicesfrom human contamination.

In an effort to increase profits, semiconductor device manufacturing has spread from Texas andCalifornia in the 1960s to the rest of the world, such as Europe, Israel, and Asia. It is a global business today.

The leading semiconductor manufacturers typically have facilities all over the world. Intel, the

world's largest manufacturer, has facilities in Europe and Asia as well as the U.S. Other topmanufacturers include STMicroelectronics (Europe), Analog Devices (US), Integrated DeviceTechnology (US), Atmel (US/Europe), Freescale Semiconductor (US), Samsung (Korea), TexasInstruments (US), GlobalFoundries (Germany, Singapore, future New York fab in construction),Toshiba (Japan), NEC Electronics (Japan), Infineon (Europe), Renesas (Japan), TaiwanSemiconductor Manufacturing Company (Taiwan), Fujitsu(Japan/US), NXP Semiconductors(Europe), Micron Technology (US), Hynix (Korea) and SMIC (China).

Wafers

A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots ( boules) up to 300 mm (slightly less than 12 inches) in diameter using theCzochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polishedto obtain a very regular and flat surface.

Once the wafers are prepared, many process steps are necessary to produce the desiredsemiconductor integrated circuit. In general, the steps can be grouped into two areas: [1]

• Front-end processing• Back-end processing

Processing

In semiconductor device fabrication, the various processing steps fall into four generalcategories: deposition, removal, patterning, and modification of electrical properties.

• Deposition is any process that grows, coats, or otherwise transfers a materialonto the wafer. Available technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD),

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molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.

• Removal processes are any that remove material from the wafer either inbulk or selectively and consist primarily of etch processes, either wet etching or dry etching. Chemical-mechanical planarization (CMP) is also a removalprocess used between levels.

• Patterning covers the series of processes that shape or alter the existingshape of the deposited materials and is generally referred to as lithography.For example, in conventional lithography, the wafer is coated with a chemicalcalled a photoresist . The photoresist is exposed by a stepper , a machine thatfocuses, aligns, and moves the mask, exposing select portions of the wafer toshort wavelength light. The unexposed regions are washed away by adeveloper solution. After etching or other processing, the remainingphotoresist is removed by plasma ashing.

• Modification of electrical properties has historically consisted of dopingtransistor sources and drains originally by diffusion furnaces and later by ionimplantation. These doping processes are followed by furnace anneal or inadvanced devices, by rapid thermal anneal (RTA) which serve to activate theimplanted dopants. Modification of electrical properties now also extends toreduction of dielectric constant in low-k insulating materials via exposure toultraviolet light in UV processing (UVP).

Many modern chips have eight or more levels produced in over 300 sequenced processing steps.

Front-end processing

 Front-end processing refers to the formation of the transistors directly on the silicon. The rawwafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer throughepitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are

 performed to improve the performance of the transistors to be built. One method involvesintroducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) isdeposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretchedsomewhat, resulting in improved electronic mobility. Another method, called silicon on

insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistorswith reduced parasitic effects.

Gate oxide and implants

Front-end surface engineering is followed by: growth of the gate dielectric, traditionally silicon

dioxide (SiO2), patterning of the gate, patterning of the source and drain regions, and subsequentimplantation or diffusion of dopants to obtain the desired complementary electrical properties. Inmemory devices, storage cells, conventionally capacitors, are also fabricated at this time, either into the silicon surface or stacked above the transistor.

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Back-end processing

Metal layers

Once the various semiconductor devices have been created they must be interconnected to form

the desired electrical circuits. This back end of line (BEOL, the latter portion of the wafer fabrication, not to be confused with back end of chip fabrication which refers to the package andtest stages) involves creating metal interconnecting wires that are isolated by insulatingdielectrics. The insulating material was traditionally a form of SiO2 or a silicate glass, butrecently new low dielectric constant materials are being used. These dielectrics presently take theform of SiOC and have dielectric constants around 2.7 (compared to 3.9 for SiO2), althoughmaterials with constants as low as 2.2 are being offered to chipmakers.

Interconnect 

Figure 13:Synthetic detail of a standard cell through four layers of planarized copperinterconnect, down to the polysilicon (pink), wells (greyish) and substrate (green).

Historically, the metal wires consisted of aluminium. In this approach to wiring often called subtractive aluminium, blanket films of aluminium are deposited first, patterned, and thenetched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. Thevarious metal layers are interconnected by etching holes, called vias, in the insulating materialand depositing tungsten in them with a CVD technique. This approach is still used in thefabrication of many memory chips such as dynamic random access memory (DRAM) as thenumber of interconnect levels is small, currently no more than four.

More recently, as the number of interconnect levels for logic has substantially increased due tothe large number of transistors that are now interconnected in a modern microprocessor , thetiming delay in the wiring has become significant prompting a change in wiring material fromaluminium to copper and from the silicon dioxides to newer low-K material. This performanceenhancement also comes at a reduced cost via damascene processing that eliminates processing

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steps. In damascene processing, in contrast to subtractive aluminium technology, the dielectricmaterial is deposited first as a blanket film, and is patterned and etched leaving holes or trenches.In single damascene processing, copper is then deposited in the holes or trenches surrounded bya thin barrier film resulting in filled vias or wire lines respectively. In dual damascene

technology, both the trench and via are fabricated before the deposition of copper resulting in

formation of both the via and line simultaneously, further reducing the number of processingsteps. The thin barrier film, called copper barrier seed (CBS), is necessary to prevent copper diffusion into the dielectric. The ideal barrier film is as thin as possible. As the presence of excessive barrier film competes with the available copper wire cross section, formation of thethinnest continuous barrier represents one of the greatest ongoing challenges in copper  processing today.

As the number of interconnect levels increases, planarization of the previous layers is required toensure a flat surface prior to subsequent lithography. Without it, the levels would becomeincreasingly crooked and extend outside the depth of focus of available lithography, interferingwith the ability to pattern. CMP (chemical mechanical planarization) is the primary processing

method to achieve such planarization although dry etch back is still sometimes employed if thenumber of interconnect levels is no more than three.

Wafer test

The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. Wafer test metrology equipment is used to verify that thewafers haven't been damaged by previous processing steps up until testing. If the number of dies —the integrated circuits that will eventually become chips— etched on a wafer exceeds a failurethreshold (ie. too many failed dies on one wafer), the wafer is scrapped rather than investing infurther processing.

Device test

Once the front-end process has been completed, the semiconductor devices are subjected to avariety of electrical tests to determine if they function properly. The proportion of devices on thewafer found to perform properly is referred to as the yield.

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the

chip. The machine marks each bad chip with a drop of dye. The fab charges for test time; the prices are on the order of cents per second. Chips are often designed with “testability features”such as " built-in self-test" to speed testing, and reduce test costs.

Good designs try to test and statistically manage corners: extremes of silicon behavior caused byoperating temperature combined with the extremes of fab processing steps. Most designs copewith more than 64 corners.

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Die preparation

Once tested, a wafer is typically reduced in thickness

 before the wafer is scored and then broken into individual die -- wafer dicing.

Only the good, unmarked chips go on to be packaged.

Packaging

Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins onthe package, and sealing the die. Tiny wires are used to connect pads to the pins. In the old days,wires were attached by hand, but now purpose-built machines perform the task. Traditionally, thewires to the chips were gold, leading to a “lead frame” (pronounced “leed frame”) of copper, thathad been plated with solder, a mixture of tin and lead. Lead is poisonous, so lead-free “lead

frames” are now mandated by ROHS.

Chip-scale package (CSP) is another packaging technology. A plastic dual in-line package, likemost packages, is many times larger than the actual die hidden inside, whereas CSP chips arenearly the size of the die. CSP can be constructed for each die before the wafer is diced.[2]

The packaged chips are retested to ensure that they were not damaged during packaging and thatthe die-to-pin interconnect operation was performed correctly. A laser etches the chip’s nameand numbers on the package.

List of steps

This is a list of processing techniques that are employed numerous times in a modern electronicdevice and do not necessarily imply a specific order.

• Wafer processingo Wet cleanso Photolithographyo Ion implantation (in which dopants are embedded in the wafer creating

regions of increased (or decreased) conductivity)o Dry etchingo Wet etching

o Plasma ashingo  Thermal treatments

Rapid thermal anneal Furnace anneals  Thermal oxidation

o Chemical vapor deposition (CVD)o Physical vapor deposition (PVD)o Molecular beam epitaxy (MBE)o Electrochemical Deposition (ECD). See Electroplating

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o Chemical-mechanical planarization (CMP)o Wafer testing (where the electrical performance is verified)o Wafer backgrinding (to reduce the thickness of the wafer so the

resulting chip can be put into a thin device like a smartcard or PCMCIAcard.)

• Die preparation o Wafer mountingo Die cutting

• IC packaging o Die attachmento IC Bonding

Wire bonding  Thermosonic Bonding Flip chip  Tab bonding

o IC encapsulation  Baking

Plating Lasermarking  Trim and form

• IC testing

Hazardous materials

Many toxic materials are used in the fabrication process. These include:

• poisonous elemental dopants such as arsenic, antimony and phosphorus• poisonous compounds like arsine, phosphine and silane•

highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuricacid and hydrofluoric acid

It is vital that workers not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure of thissort. Most fabrication facilities employ exhaust management systems, such as wet scrubbers,combustors, heated absorber cartridges etc, to control the risk to workers and also theenvironment if these toxic materials are released into the atmosphere.

Fabrication

Rendering of a small standard cell with three metal

layers (dielectric has been removed). The sand-

colored structures are metal interconnect, with the

vertical pillars being contacts, typically plugs of 

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tungsten. The reddish structures are polysilicon gates, and the solid at the bottom is

the crystalline silicon bulk.

Schematic structure of a CMOS chip, as built in the

early 2000s. The graphic shows LDD-MISFET's on an

SOI substrate with five metallization layers and

solder bump for flip-chip bonding. It also shows the

section for FEOL (front-end of line), BEOL (back-end

of line) and first parts of back-end process.

The semiconductors of the periodic table of the chemicalelements were identified as the most likely materials for a solid state vacuum tube. Starting with copper oxide, proceeding to germanium, then silicon, the materials weresystematically studied in the 1940s and 1950s. Today,silicon monocrystals are the main substrate used for integrated circuits (ICs) although some III-V compounds of the periodic table such as gallium arsenide are used for specialized applications like LEDs, lasers, solar cells and thehighest-speed integrated circuits. It took decades to perfectmethods of creating crystals without defects in the

crystalline structure of the semiconducting material.

Semiconductor ICs are fabricated in a layer process which includes these key process steps:

• Imaging• Deposition• Etching

The main process steps are supplemented by doping and cleaning.

Mono-crystal silicon wafers (or for special applications, silicon on sapphire or gallium arsenidewafers) are used as the substrate. Photolithography is used to mark different areas of thesubstrate to be doped or to have polysilicon, insulators or metal (typically aluminium) tracksdeposited on them.

• Integrated circuits are composed of many overlapping layers, each definedby photolithography, and normally shown in different colors. Some layersmark where various dopants are diffused into the substrate (called diffusionlayers), some define where additional ions are implanted (implant layers),some define the conductors (polysilicon or metal layers), and some define theconnections between the conducting layers (via or contact layers). Allcomponents are constructed from a specific combination of these layers.

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• In a self-aligned CMOS process, a transistor is formed wherever the gate layer(polysilicon or metal) crosses a diffusion layer.

• Capacitive structures, in form very much like the parallel conducting plates of a traditional electrical capacitor, are formed according to the area of the"plates", with insulating material between the plates. Capacitors of a widerange of sizes are common on ICs.

• Meandering stripes of varying lengths are sometimes used to form on-chipresistors, though most logic circuits do not need any resistors. The ratio of the length of the resistive structure to its width, combined with its sheetresistivity, determines the resistance.

• More rarely, inductive structures can be built as tiny on-chip coils, orsimulated by gyrators.

Since a CMOS device only draws current on the transition between logic states, CMOS devices

consume much less current than bipolar devices.

A random access memory is the most regular type of integrated circuit; the highest densitydevices are thus memories; but even a microprocessor will have memory on the chip. (See theregular array structure at the bottom of the first image.) Although the structures are intricate – with widths which have been shrinking for decades – the layers remain much thinner than thedevice widths. The layers of material are fabricated much like a photographic process, althoughlight waves in the visible spectrum cannot be used to "expose" a layer of material, as they would be too large for the features. Thus photons of higher frequencies (typically ultraviolet) are usedto create the patterns for each layer. Because each feature is so small, electron microscopes areessential tools for a process engineer who might be debugging a fabrication process.

Each device is tested before packaging using automated test equipment (ATE), in a processknown as wafer testing, or wafer probing. The wafer is then cut into rectangular blocks, each of which is called a die. Each good die (plural dice, dies, or die) is then connected into a packageusing aluminium (or gold) bond wires which are welded and/or Thermosonic Bonded to pads,usually found around the edge of the die. After packaging, the devices go through final testing onthe same or similar ATE used during wafer probing. Test cost can account for over 25% of thecost of fabrication on lower cost products, but can be negligible on low yielding, larger, and/or higher cost devices.

As of 2005, a fabrication facility (commonly known as a semiconductor lab) costs over $1

 billion to construct, because much of the operation is automated. The most advanced processesemploy the following techniques:

•  The wafers are up to 300 mm in diameter (wider than a common dinnerplate).

• Use of 65 nanometer or smaller chip manufacturing process. Intel, IBM, NEC,and AMD are using 45 nanometers for their CPU chips. IBM and AMD are indevelopment of a 45 nm process using immersion lithography.

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• Copper interconnects where copper wiring replaces aluminium forinterconnects.

• Low-K dielectric insulators.• Silicon on insulator (SOI)• Strained silicon in a process used by IBM known as strained silicon directly on

insulator (SSDOI)

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Packaging

The earliest integrated circuits were packaged in ceramicflat packs, which continued to be used by the military for their reliability and small size for many years. Commercialcircuit packaging quickly moved to the dual in-line package (DIP), first in ceramic and later in plastic. In the 1980s pincounts of VLSI circuits exceeded the practical limit for DIP packaging, leading to pin grid array (PGA) and leadless chipcarrier (LCC) packages. Surface mount packaging appearedin the early 1980s and became popular in the late 1980s,

using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by small-outline integrated circuit -- a carrier which occupies an area about 30 – 50% less than anequivalent DIP, with a typical thickness that is 70% less. This package has "gull wing" leads protruding from the two long sides and a lead spacing of 0.050 inches.

In the late 1990s, PQFP and TSOP packages became the most common for high pin countdevices, though PGA packages are still often used for high-end microprocessors. Intel and AMDare currently transitioning from PGA packages on high-end microprocessors to land grid array(LGA) packages.

Ball grid array (BGA) packages have existed since the 1970s. Flip-chip Ball Grid Array 

 packages, which allow for much higher pin count than other package types, were developed inthe 1990s. In an FCBGA package the die is mounted upside-down (flipped) and connects to the package balls via a package substrate that is similar to a printed-circuit board rather than bywires. FCBGA packages allow an array of input-output signals (called Area-I/O) to bedistributed over the entire die rather than being confined to the die periphery.

Traces out of the die, through the package, and into the printed circuit board have very differentelectrical properties, compared to on-chip signals. They require special design techniques andneed much more electric power than signals confined to the chip itself.

When multiple dies are put in one package, it is called SiP, for System In Package. When

multiple dies are combined on a small substrate, often ceramic, it's called an MCM, or Multi-Chip Module. The boundary between a big MCM and a small printed circuit board is sometimesfuzzy.

Chip labeling and manufacture date

Most integrated circuits large enough to include identifying information include four commonsections: the manufacturer's name or logo, the part number, a part production batch number 

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Figure 14:Early USSR-madeintegrated circuit

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and/or serial number, and a four-digit code that identifies when the chip was manufactured.Extremely small surface mount technology parts often bear only a number used in amanufacturer's lookup table to find the chip characteristics.

The manufacturing date is commonly represented as a two-digit year followed by a two-digit

week code, such that a part bearing the code 8341 was manufactured in week 41 of 1983, or approximately in October 1983.

Legal protection of semiconductor chip layouts

Prior to 1984, it was not necessarily illegal to produce a competing chip with an identical layout.As the legislative history for the Semiconductor Chip Protection Act of 1984, or SCPA,explained, patent and copyright protection for chip layouts, or topographies, were largelyunavailable. This led to considerable complaint by U.S. chip manufacturers—notably, Intel,which took the lead in seeking legislation, along with the Semiconductor Industry Association(SIA)--against what they termed "chip piracy."

A 1984 addition to US law, the SCPA, made all so-called mask works (i.e., chip topographies) protectable if registered with the U.S. Copyright Office. Similar rules apply in most other countries that manufacture ICs. (This is a simplified explanation - see SCPA for legal details.)

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Notable ICs

Microprocessor

A microprocessor incorporates most or all of the functionsof a computer 's central processing unit (CPU) on a singleintegrated circuit (IC, or microchip). The firstmicroprocessors emerged in the early 1970s and were usedfor electronic calculators, using binary-coded decimal (BCD) arithmetic in 4-bit words. Other embedded uses of 4- bit and 8-bit microprocessors, such as terminals,  printers,various kinds of automation etc., followed soon after.Affordable 8-bit microprocessors with 16-bit addressing alsoled to the first general-purpose microcomputers from themid-1970s on.

During the 1960s, computer processors were oftenconstructed out of small and medium-scale ICs containing from tens to a few hundred transistors.The integration of a whole CPU onto a single chip greatly reduced the cost of processing power.From these humble beginnings, continued increases in microprocessor capacity have renderedother forms of computers almost completely obsolete (see history of computing hardware), withone or more microprocessors used in everything from the smallest embedded systems andhandheld devices to the largest mainframes and supercomputers.

Since the early 1970s, the increase in capacity of microprocessors has been a consequence of Moore's Law, which suggests that the number of transistors that can be fitted onto a chip doublesevery two years. Although originally calculated as a doubling every year, Moore later refined the period to two years.

In the late 1990s, and in the high-performance microprocessor segment, heat generation (TDP),due to switching losses, static current leakage, and other factors, emerged as a leadingdevelopmental constraint.

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•

Figure 15:Intel 4004, the firstgeneral-purpose, commercial

microprocessor

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Net income ▼-$27.2 million USD (2008)

Employees 6,000

Website www.atmel.com

 

Figure 16:Atmel AT90S2333 microcontroller Figure 17:Atmel ATMEGA32microcontroller

Atmel Corporation ( NASDAQ: ATML) is a manufacturer of semiconductors, founded in 1984.Its focus is on system-level solutions built around flash microcontrollers. Its products includemicrocontrollers (including 8051 derivatives and AT91SAM and AT91CAP ARM-based

micros), and its own Atmel AVR and AVR32 architectures, radio frequency (RF) devices,EEPROM and Flash memory devices (including DataFlash-based memory), and a number of application-specific products. Atmel supplies its devices as standard products, ASICs, or ASSPs depending on the requirements of its customers. In some cases it is able to offer system on chipsolutions.

Atmel serves a range of application segments including consumer , communications, computer networking, industrial, medical, automotive, aerospace and military. It is an industry leader insecure systems, notably for the smart card market.

The President and CEO of Atmel is Steven Laub.

Atmel owns four semiconductor facilities:

• Fab5 in Colorado Springs (USA)• Fab6 in Heilbronn (Germany) (Sold)• Fab7 in Rousset (France) (Sold)• Fab9 in North Tyneside (England) (Sold)

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CONCLUSION

• Speed - the time required for a signal to travel between the functional

circuit blocks in a system (delay) reduced.

 –  Delay depends on resistance/capacitance of interconnections

 –  resistance proportional to interconnection length

• Noise - “unwanted disturbances on a useful signal” [Al-sarawi]

 –  reflection noise (varying impedance along interconnect)

 –  crosstalk noise (interference between interconnects)

 –  electromagnetic interference (EMI) (caused by current in pins)

• 3D chips

 –  fewer, shorter interconnects

 –  fewer pins

• Power consumption

 –  power used charging an interconnect capacitance

• P = fCV2 

 –  power dissipated through resistive material

• P = V2/R 

 –  capacitance/resistance proportional to length

 –  reduced interconnect lengths will reduce power

• Interconnect capacity (connectivity)

 –  more connections between chips

 –  increased functionality, ease of design

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• Printed circuit board size/weight

 –  planar size of PCB reduced with negligible IC height increase

 –  weight reduction due to more circuitry per package/smaller PCBs

 –  estimated 40-50 times reduction in size/weight

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APPENDIX

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REFERENCES

We used the following web resources as reference for our project report:

1. www.wikipedia.org

2. www.howstuffworks.com

3. www.infoworld.com

4. www.vlsi.com

5. www.authorstream.net

6.

We also referred the following books:

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GLOSSARY