ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Telecom Requirements for the Validation of Pb-Free Solder

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

♦ High Availability (Five Nines)

The Carrier Class Challenge

♦ 20 Year Life♦ Diverse Operating Environments♦ Hot Swap-able Plug and Play

2

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Higher Circuit Pack Layer Counts (>18)The Circuit Pack Challenge

• Push the Pb-Free Solder Process Envelope• Require Leading-Edge Laminate Performance• Stress VIA Technology

3

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Over the last three (3) years telecommunications service providers and manufactures have worked to define acceptance criteria that will allow for the qualified introduction of Pb-Free Solder into Carrier Class telecommunications equipment.

Standards Background

4

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Augment, not replace, Reliability Due Diligence

Intent of Telecom Pb-Free Solder Standards

Daisy-Chained Components on Representative PCBs

5

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

This presentation will focus on:1. Alliance for Telecommunications Industrial Solutions

Validation Test Requirements

2. Verizon Qualification Test Requirements

Telecom Pb-Free Solder Standards

6

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Sub-Assembly

Telecom Requirements for the Validation of Pb-Free Solder

Validation Testing LevelsCircuit Pack Product

7

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Subassembly – ATIS-0600019.2009

ATIS Standards Background

Circuit Pack – ATIS-0600020.2010Product Level – ATIS-0600021.XXXX (Draft)

Assembly Level Specific

8

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Circuit Pack SpecificCovers “Printed Board Assemblies (PBAs) manufactured with ‘lead-free’ solders that are intended for use in Telecommunications Equipment purchased by Verizon.”

Verizon Standards Background

9

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

♦ ATIS develops standards and solutions addressing a wide range of industry issues in a manner that allocates and coordinates industry resources and produces the greatest return for communications companies.

About ATIS

♦ ATIS is accredited by the American National Standards Institute (ANSI)

♦ Over 600 industry professionals from more than 250 communications companies actively participate in ATIS committees and incubator solutions programs.

10

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Pb-free Working Group

ATIS PWG Mission

Proposes

Additionally Recommends

Develops Recommends

Standards and Technical Reports relating to the use of lead or the restriction of lead in solder used in the manufacturing of telecommunications network equipment.

Positions on matters, within its scope of expertise, under consideration by other national, regional and international standards development organizations.

11

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

The subjects of the PWG Standards and Technical Reports include, but are not limited to:

ATIS PWG Scope

1. Use and Restriction2. Stress Tolerance3. Environmental Impact of lead

Use of alternative materials and methodologies Mechanical Design Layout of telecommunications network equipment

printed circuit assemblies and the components that are used in their construction.

12

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Requires Compliance to Industrial Standards & Validation Testing♦ IPC/JEDEC J-STD-020

Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices ♦ IPC/JEDEC J-STD-075

Classification of Non-IC Electronic Components for Assembly Processes♦ JEDEC JESD-201

Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface Finishes♦ IPC/JEDEC JP002

Current Tin Whisker Theory and Mitigation Practices Guideline♦ EU Directive 2002/95/EC

EU Directive for Restriction of Hazardous Substances (RoHS)♦ GR-78-CORE

Generic Requirements for the Physical Design and Manufacture of Telecommunications Products and Equipment♦ IPC 9701

Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments♦ IEC 60068–2–27

Basic Environmental Testing Procedures Part 2, Test Ea and Guidance, Shock♦ IPC/JEDEC J-STD-609

Marking and Labeling of Components, PCBs and PCBAs to Identify Lead (Pb), Pb-Free and Other Attributes

ATIS Approach

13

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Sub-Assembly Validation Testing

Minimum Sample: 3 Sub-Assemblies1. Thermal Aging

(750 hours at 125°C or 2000 hours at 85°C)2. Mechanical Shock

(JEDEC JESD22-B104, service condition A) 3. Pre/Post Functional Testing4. Solder Joint Cross-Section & SEM Examination

(largest BGA/SMT component)

14

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Circuit Pack Validation Testing

Minimum Sample: 3 Circuit Packs1. In Circuit Test – 5X 2. Thermal Aging3. Mechanical Shock4. Functional Test5. Selected Destructive Tests

Shear\Pull\Dye & Pry\Micro-Section

15

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Circuit Pack Validation Testing 1. In Circuit Test: 5 Sequential Rounds

16

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Circuit Pack Validation Testing 2. Thermal Aging:

125ºC for 240 Hours (10 days)/480 hours at 85°C

17

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Circuit Pack Validation Testing 3. Mechanical Shock: IEC 60068–2–27 (30g, Half-Sine, 10 ms)

18

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Circuit Pack Validation Testing

Functional Test: Over Operating Temperature Extremes

19

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Circuit Pack Validation Testing Functional Testing: Over TemperatureThe product is tested continually during the thermal excursions, and must demonstrate full functionality throughout the duration of the testIndoor Products (i.e. Central Office)Temperature extremes: -5°C to 50°CRamp rate: 2°C/minute (minimum) to 20°C/minute (maximum)Dwell time: 60 minutes (at both extremes)Total number of cycles to be run: 10Outdoor ProductsTemperature extremes: -40°C to 70°CRamp rate: 2°C/minute (minimum) to 20°C/minute (maximum)Dwell time: 60 minutes (at both extremes)Total number of cycles to be run: 25

20

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Circuit Pack Validation Testing

Selected Destructive Tests:

Shear Pull Dye & Pry Micro-Section

Figure 2: Example of Pad Cratering

21

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Product Validation Testing (Draft)

AST Alternative Test SequenceThis draft standard provides an AST product level alternative to the environmental test sequence found in the ATIS Sub-Assembly and Circuit Pack Pb-Free test requirements. It’s intended to rapidly evaluate the performance of Pb-Free sub-assemblies and circuit packs in their final product application.

22

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Sub-Assembly Environmental Test Sequence

Thermal Aging

Mechanical Shock

Functional Test

Functional Test

23

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Circuit Pack Environmental Test Sequence

ICT Test – 5X

Thermal Aging

Mechanical Shock

Functional Test Over

TemperatureSelected

Destructive Tests

Shear\Pull\Dye &Pry\

Micro-Section

Functional Test

24

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Draft Product Validation Testing

ICT Test – 5X

Thermal Aging

Mechanical Shock

Functional Test Over

TemperatureSelected

Destructive Tests

Shear\Pull\Dye &Pry\

Micro-Section

Functional Test

Replaced by AST Alternative

Environmental Test Sequence

25

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Draft Product Validation Testing AST Alternative Test Sequence Two (2) part Sequential Test

1. Solder Defect PrecipitationTargeted at precipitating cumulative solder joint fatigue

2. Operational DetectReduced thermal extremes allow for operational detection of intermittent connections while serving to further develop patent defects

Performed in a HALT chamber Uses the product’s standard mounting orientation

26

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Draft AST Alternative Test Sequence

First Exposure: Solder Defect Precipitation Three (100˚C, -20˚C, -60˚C)10 min plateaus/thermal cycle 60˚C/minute transition rates Vibration stepped from 5-40 gRMS at 5 gRMS/thermal cycle Total exposure time is approximately 4.5 hours Product is non-operational during this exposure The product is functionally tested pre and post exposure Pre and post exposure idle operating current captured

27

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: AST Alternative Test SequenceSolder Defect Percipetation Exposure

-80

-60

-40

-20

0

20

40

60

80

100

120

0.0 0.3 0.6 0.8 1.1 1.4 1.7 1.9 2.2 2.5 2.8 3.1 3.3 3.6 3.9 4.2 4.4

Time (Hours)

Tem

pera

ture

(C)

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

45.0

g RM

S Z A

xis

Air TempTable Vib Level

28

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: Draft AST Alternative Test SequenceSecond Exposure: Operational Functional & operating current monitored Two thermal cycles between -5˚C↔ 50˚C 2.0˚C/minute transition rate 10 minutes plateaus at each temperature extreme Total exposure time ~3 hours Vibration cycling 0-50 gRMS during thermal transitions Vibration held at 5 gRMS at each thermal plateau

Thermal extremes modified to mimic end application

29

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

ATIS: AST Alternative Test Sequence

Operational Detect Exposure: Indoor products (i.e. Central Office)

-10

0

10

20

30

40

50

60

0.00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8

Time (Hours)

Tem

pera

ture

(C

)

0

10

20

30

40

50

60

gR

MS Z

-Axis

Air TempTable Vib Level

Operational Detect Exposure: Outdoor Products (i.e. Outside Plant)

-60

-40

-20

0

20

40

60

80

0.00.10.20.30.40.50.60.70.80.91.01.11.21.31.41.51.61.71.81.92.02.12.22.32.42.52.62.72.82.93.03.13.23.33.43.53.63.73.83.94.04.14.24.34.44.54.6

Time (Hours)

Tem

pera

ture

(C

)

0

10

20

30

40

50

60

gR

MS Z

-Axis

Air TempTable Vib Level

30

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

“Verizon NEBSTM Compliance: Qualification Requirements for Printed Board Assemblies Manufactured with Lead-Free Solder for use in Telecommunications Equipment”

Verizon Technical Purchasing Requirements VZ.TPR.9307 “ , Issue 4, August 2010

31

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

32

APPLICABILITYApplies to equipment installed in environmentally controlled and uncontrolled facilities and spaces, and Optical Network Terminals installed at customer premises. The qualification tests specified in this document apply to all components, assemblies and PBAs containing lead-free solder alloys.

EXEMPTIONSComponents, assemblies and PBAs manufactured with traditional tin-lead solder alloy (i.e., 60/40 percentage composition) are exempt. Set Top Boxes, Broadband Home Routers and DSL Modems installed at customer premises are exempt. Measurement and Test Equipment used to configure, provision, monitor and/or repair network equipment is exempt. Small Form-factor Pluggable (SFP) and mini Gigabit Interface Converter (GBIC) hot-swappable transceivers are exempt.

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

Specifies Compliance & Qual TestsGR-63-CORENEBSTM Requirements: Physical ProtectionGR-78-COREGeneric Physical Design Requirements for Telecommunications Products and EquipmentGR-357-COREGeneric Requirements for Assuring the Reliability of Components Used in Telecommunications EquipmentVZ.TPR.9306NEBS Requirements for the Physical Design and Manufacture of Telecommunication Products and Equipment IEC/MIL/etc.Various reference test methods and procedures

33

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

“The number of PBA samples used is selected to ensure a minimum of 3891 solder joints are used for each test with an accept number of 1 (LTPD of 0.1%).”

Circuit Pack Minimum

34

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

35

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

36

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

37

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

38

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

39

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

40

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

41

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

42

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

43

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Verizon: Circuit Pack Qualification

44

ASTR 2010 (October 6 – 8 )Denver, CoGary Hazard

Telecom Requirements for the Validation of Pb-Free Solder

Thanks For Your Time

45