620 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 3, MARCH 1998

Technology for AdvancedHigh-Performance MicroprocessorsMark T. Bohr, Senior Member, IEEE, and Youssef A. El-Mansy,Fellow, IEEE

(Invited Paper)

Abstract—This paper describes the development of logic tech-nologies that meet the density, performance, power, and man-ufacturing requirements for advanced high-performance micro-processors. Aggressive scaling of MOS transistor dimensionsalong with reduced power supply provide devices with highperformance, low power, and good reliability. Multiple layersof planarized aluminum interconnect with high aspect ratiosare used to address the increasing importance of interconnectdensity and performance. Static RAM test vehicles with small6-transistor cell sizes are used to develop these logic technologiesand to provide early demonstrations of yield and performancecapabilities. The manufacturing strategy includes developmentgroup ownership of the technology from inception to early man-ufacturing ramp, extensive reuse of prior generation processequipment and modules, and a “copy exactly” methodology toensure successful process startup and ramp in multiple facilities.

I. INTRODUCTION

A DVANCED microprocessors continue to depend on tran-sistor scaling to meet density and performance targets.

Total chip power dissipation is growing at an intolerable ratedue to increases in transistor count and operating frequency.More so than in the past, transistor feature size scalingmust be accompanied by supply voltage scaling to main-tain reasonable power dissipation levels. Whereas transistorscaling provides simultaneous improvements in both densityand performance, interconnect scaling improves interconnectdensity but generally at the cost of degraded interconnectdelay. On older technologies, interconnect delay representedonly a small fraction of the microprocessor clock cycle timeand was a small factor in overall chip performance. Advancedmicroprocessors have grown larger and operate at much higherfrequencies. Interconnect delay is now a significant fractionof clock cycle time and interconnect scaling can have asignificant impact on overall chip performance. As a result,more interconnect layers are needed to be able to meet bothdensity and performance requirements. Aggressive transistorscaling and an increased number of interconnect layers canquickly increase the cost and complexity of manufacturingadvanced microprocessors. To address this, a manufacturingstrategy is needed to ensure that these products can be quicklybrought to market, produced in high volume, and made atreasonable cost. This paper describes a family of CMOS logic

Manuscript received March 13, 1997; revised May 28, 1997. The reviewof this paper was arranged by Editor Y. Nishi.

The authors are with Portland Technology Development, RA1-204, IntelCorporation, Hillsboro, OR 97124-6497 USA.

Publisher Item Identifier S 0018-9383(98)01665-7.

Fig. 1. Supply voltage and gate oxide thickness trends for Intel logictechnologies.

technologies and the manufacturing strategy used to meet thedensity, performance, power, and production requirements ofhigh-performance microprocessor products.

II. TRANSISTORS

MOS transistor scaling has been the key to continual im-provements in integrated circuit density and performanceover the past 30 years. For most of this period, supplyvoltages remained constant to maintain compatibility withother integrated circuits and the systems they were a partof. As gate oxides scaled, electric fields increased. At the0.6- m generation, the electric fields in the gate dielectricbegan to approach reliability limits and supply voltages neededto scale along with gate oxide thickness (Fig. 1). In addition tomaintaining gate oxide reliability, scaling of supply voltagesis helping to reduce overall chip power. Transistor drive cur-rents have continued to increase despite reductions in supplyvoltage, but the rate of increase is slowing (Fig. 2). Even witha slower increase in drive current, transistor performance isimproving through decreases in voltage swing and reductionsin parasitic capacitance.

Fig. 3 illustrates the structure of the MOS transistors andisolations used on both 0.35- and 0.2-m generation logictechnologies [1], [2]. The transistor process flow starts with

epi wafers followed by the formation of shallowtrench isolation and well regions. Shallow trench isolationis used instead of traditional LOCOS isolation because itprovides tighter isolation design rules and improved surfaceplanarity [3]. Aggressive scaling of gate oxides is key to

0018–9383/98$10.00 1998 IEEE

BOHR AND EL-MANSY: TECHNOLOGY FOR ADVANCED HIGH-PERFORMANCE MICROPROCESSORS 621

Fig. 2. NMOS and PMOS drive current trends for Intel logic technologies.

Fig. 3. Schematic cross section of NMOS and PMOS transistors.

improving transistor performance and facilitating a reductionin supply voltage to reduce chip power consumption. Twoversions of the 0.35-m technology were developed using7.0- and 6.0-nm gate oxides optimized for 3.3 and 2.5 Vsupply voltages, respectively. A 4.5-nm gate oxide was usedon the 0.25-m generation which was optimized for a 1.8 Vsupply voltage. Complementary-doped polysilicon gates areused to form surface channel NMOS and PMOS transistors.The surface channel PMOS device is preferred over buriedchannel devices for low voltage applications because of thereduced subthreshold slope and ability to target a lowerthreshold voltage. Gate sidewall spacers are formed withSi N Self-aligned TiSi (salicide) is formed on polysiliconand source-drain regions with a sheet resistance of5 sqThe low resistance TiSilayer reduces signal delay on longpolysilicon lines and provides low contact resistance to source-drain regions. The source-drain structures have both deep andshallow extension regions. The shallow extensions need tobe abrupt to provide good short-channel characteristics andlow gate overlap capacitance, but must not increase seriesresistance. The deep regions are optimized for low junctionleakage, low junction capacitance and low interface resistanceto the TiSi layer, but must be designed so as not to overrunthe shallow extensions or degrade diffusion-diffusion isolation.

Many factors are important in optimizing MOS transis-tor performance. Gate oxide thickness should be as thin aspossible to improve short-channel characteristics, maximizethe drain current , and facilitate reduced supply volt-

Fig. 4. A 0.25-�m generation NMOS transistor threshold voltage versusphysical gate length.

Fig. 5. A 0.25-�m generation PMOS transistor threshold voltage versusphysical gate length.

age for reduced power. However, the minimum gate oxidethickness is dictated by reliability, defect density, and gatecapacitance considerations. Threshold voltage must beset low to maximize and to facilitate reduced supplyvoltage, but not so low as to increase off current andstandby power to unacceptable levels or to result in functionalfailure of dynamic circuits [4]. Transistor development usuallybegins with determining the worse-case target neededto meet product power and circuit functionality requirements.The targeted for minimum gate length devices is a functionof the worse-case requirements, subthreshold slope,gate length variation and short-channel effects such as draininduced barrier lowering (DIBL). Figs. 4 and 5 are examplesof NMOS and PMOS threshold voltage versus gate lengthcharacteristics from the 0.25-m generation technology. Short-channel effects have a significant impact on, butis maintained at 250 mV down to physical gate lengthsof 0.18 m, and NMOS and PMOS devices have closelymatched characteristics. In addition to meeting and

requirements, minimum gate length transistors must alsobe well controlled to ensure stable operation. One measureof transistor control is subthreshold slope. MOS transistorsubthreshold slopes are typically in the range of 80–100mV/decade and Fig. 6 shows an example from the 0.25-m

622 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 3, MARCH 1998

Fig. 6. A 0.25-�m MOS transistor subthreshold slope versus physical gatelength, jVDSj = 1:8 V.

Fig. 7. NMOS CV/I gate delay versus physical gate length for publisheddevices.

generation technology of how subthreshold slopes are con-trolled at 85 mV/decade down to a physical gate length of0.18 m

A simple transistor performance metric that can be appliedto CMOS devices is the CV/I metric [5]. Figs. 7 and 8show NMOS and PMOS transistor gate delays estimated withthe CV/I metric for a large number of published deviceswith physical gate lengths of 0.4m and below [2]. Onlyreasonably well controlled devices were included in this com-parison, namely those with subthreshold slopes of less than100 mV/decade. The expected correlation between gate delayand is apparent in these graphs. With lithographycapability being the primary limiting factor to introducing newgenerations of integrated circuit technology, it is advantageousto develop transistors that get the maximum performancefor a given minimum feature size. The two most recentgenerations of Intel logic technology demonstrate superiortransistor performance by being below the gate delay trend linefor their respective gate lengths. The excellent performance isachieved by aggressive gate oxide scaling along with carefuloptimization of well and source-drain formation.

The primary source of power consumption on high-performance microprocessors is CVf power. The energy usedin MOSFET gate transitions can be estimated byA transistor metric that comprehends both power and speed

Fig. 8. PMOS CV/I gate delay versus physical gate length for publisheddevices.

Fig. 9. NMOS energy delay product versus physical gate length for pub-lished devices.

is the energy delay product Fig. 9 shows theestimated NMOS energy delay product for a large number ofpublished devices [2]. For this metric it is assumed that channelwidths scale along with gate lengths andthat The energy delay product has beenreduced significantly as a function of due to featuresize reduction and supply voltage scaling. The transistors onthe 0.25- m generation technology demonstrate about areduction in energy delay product compared to the 0.35-mgeneration, an important measure of how both performanceand power requirements are addressed.

III. I NTERCONNECTS

Interconnect scaling is a growing concern in the design anddevelopment of advanced logic technologies [6]. As shownin Fig. 10, interconnect RC delay increases as interconnectpitch (line width space) decreases due to the increase inline resistance. This is in stark contrast to MOS transistorscaling where gate delay decreases as feature sizes are scaled(see Figs. 7 and 8). Interconnect pitches need to be scaledwith every technology generation to keep pace with densityrequirements. One way to deal with interconnect density andperformance requirements is to add more metal layers. Addingmore interconnect layers can help density without havingto scale pitch aggressively. Increasing metal aspect ratios,

BOHR AND EL-MANSY: TECHNOLOGY FOR ADVANCED HIGH-PERFORMANCE MICROPROCESSORS 623

Fig. 10. Interconnect RC delay versus interconnect pitch and length foraluminum/SiO2 interconnects with a constant metal aspect ratio of 2.

Fig. 11. Number of metal layers and average metal pitch trend for Intellogic technologies.

where aspect ratio is defined as thickness/pitch, is anotherway of maintaining good interconnect performance whilescaling pitch. Higher metal aspect ratios help to reduce lineresistance, but do result in slightly higher line-line capacitance.Increased aspect ratio produces a net performance advantageup to aspect ratios of 2 [6]. Figs. 11 and 12 show howinterconnects have evolved over the last six generations ofIntel logic technologies to meet density and performancerequirements. The total number of metal layers has increasedfrom 2 to 5. The average metal pitch (defined as the sumof the minimum pitch allowed on each layer divided by thetotal number of layers) has reduced from 5.5 to 1.3m Theaverage metal thickness has remained constant at1 m,resulting in an increase in average metal aspect ratio from

0.4 to 1.7. Despite the increase in number of layersand increase in aspect ratio, the RC delay of an averagemetal line with constant length is getting slightly worse witheach generation. At the same time microprocessor operatingfrequency is increasing and clock cycle time is decreasing.As a result, interconnect delay is becoming a larger fractionof clock cycle time (see Fig. 13). The problem is even moreacute when considering that leading edge microprocessordie sizes are growing and the average interconnect lengthsare increasing. For these reasons greater attention is beingplaced on interconnects to ensure continuance of historicimprovements in microprocessor performance.

Fig. 12. Average metal thickness and average metal aspect ratio trend forIntel logic technologies.

Fig. 13. Trend of microprocessor clock cycle time and interconnect RC delayfor 10-mm interconnect lengths with average pitch and thickness for the lastsix generations of Intel logic technology.

The 0.25- m technology generation uses five layers ofaluminum interconnects with high aspect ratios to addressdensity and performance requirements. The metal stack isTi/Al-Cu/Ti/TiN which provides low line resistance, goodelectromigration properties and low via resistance. The inter-level dielectric between polysilicon and metal 1 is BPSG pla-narized by chemical-mechanical polish. The inter-level dielec-tric formed between the metal layers is a plasma-TEOS oxideformed by sequential dep-etch and planarized by chemical-mechanical polish. Contacts and vias are all filled with tung-sten plugs formed by blanket tungsten deposition followed bychemical-mechanical polish. The extensive use of chemical-mechanical polishing provides for a high degree of planaritywhich ensures good metal step coverage over contacts andvias and facilitates patterning of tight interconnect dimensionswith wide process latitude. The metal 1 layer has a tight pitchfor optimal density as a local interconnect and for a smallSRAM cell size. Metal 2 and 3 layers use an intermediatepitch to optimize both density and performance. Metal 4 and5 layers use increased pitches and thicknesses to optimize forsignal propagation and power routing. A cross section of theinterconnects is shown in Fig. 14.

IV. SRAM TEST VEHICLE

Static RAM’s with 6-transistor memory cells have been usedas the initial circuit vehicle for developing these technologies

624 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 3, MARCH 1998

Fig. 14. Cross section of five-layer interconnect technology used on 0.25-�mgeneration.

and for early identification of yield, reliability and performancelimiters. For the 0.35-m generation both 1 and 4 MbitSRAM’s were designed and built with a cell area of 20.5mFor the 0.25- m generation a 4 Mbit SRAM was used with acell area of 10.26 m A 6-T cell was chosen as opposedto poly load or thin film transistor cells because the 6-Tcell architecture and process flow are more compatible withhigh-performance logic requirements. A dense SRAM cell isimportant to microprocessor products, but the process flowand design rules were selected with high-performance logicrequirements as the first consideration.

Three layers of metal are needed to make the SRAM cell:metal 1 for internal hook-ups and strapping, metal 2for internal hook-ups and strapping and wordline, andmetal 3 for bitlines [Fig. 15(a)]. An alternate layout withsimilar cell area uses metal 1 for internal hook-ups, metal2 for bitlines and strapping, and metal 3 for wordlinestrapping [Fig. 15(b)]. Metals 4 and 5 are added to the cell asredundant and wordline straps to make the SRAMan appropriate development vehicle for a 4- or 5-metal layerlogic technology. The intent is to use the SRAM vehicle toexercise all of the critical design rules and to make the cellsensitive to all the normal defect modes. By being a sensitive“defect catcher” the SRAM can accelerate yield learning earlyin the development cycle. The SRAM incorporates testabilityfeatures such as direct bit access and bit margin test to facilitateyield analysis. SRAM die can be processed and tested insufficient numbers to provide an early reliability data baseand burn-in failure modes are relatively easy to trace with therasterable array. The SRAM is also used to provide an initialverification of circuit performance models and to quantifyperformance improvements as the process matures. As anearly demonstration of performance capability, the 4-MbitSRAM done on the 0.25-m technology operates at 560 MHz(1.79 ns cycle) at 1.8 V and 25 C and has a bandwidth of4.5 GByte/s [7].

V. MANUFACTURING STRATEGY

The development strategy for the technology centers aroundbuilding wide margins in individual unit processes, utilizing

(a)

(b)

Fig. 15. (a) 6T SRAM cell layout for 0.25-�m generation using metal 3bitlines. (b) 6T SRAM cell layout for 0.25-�m generation using metal 2bitlines.

as many of the previous generation process steps as possibleand achieving high yields and reliability at the early stagesof development. Advanced SRAM’s with built-in testabilityand defect detection features are used as the primary develop-ment and technology qualification vehicles. The developmentgroup maintains complete ownership of the technology frominception through the early stages of manufacturing ramp andmature yields. In fact, that group ramps the technology in thedevelopment facility, transfers responsibility to a manufactur-ing group and moves to a new facility to develop the nextgeneration technology. Over multiple generations, the learningwas enhanced and these transitions have become seamless. Along term die yield trend for 0.35- and 0.25-m generationsdone in multiple facilities is depicted in Fig. 16, where thereis little evidence of the fab transitions that occurred duringthat time frame.

BOHR AND EL-MANSY: TECHNOLOGY FOR ADVANCED HIGH-PERFORMANCE MICROPROCESSORS 625

Fig. 16. Overall process defect density trend based on SRAM and micro-processor yields for 0.35- and 0.25-�m generations done in multiple factories.

Two key elements have contributed to the success of execut-ing these multiple transitions and simultaneous high-volumeramps in multiple manufacturing facilities. These are thehigh percentage of equipment reuse from one generation tothe next and the “copy exactly” methodology used duringthe transfer from the development facility to the manufac-turing facilities. The basic philosophy on introducing newprocess equipment is driven by enabling and obsolescence.Process tools are replaced only if they cannot meet or de-liver the technology targets, as in patterning for example.Tools are also replaced if a supplier obsoletes a particulartool. A target of 70% equipment reuse has been established;in fact, 75% and 85% reuse levels have been achieved inthe 0.35- and 0.25-m technologies, respectively. A “copyexactly” methodology is practiced and is strictly enforcedduring the technology transfer from the development facil-ity to the high volume manufacturing facility. Equipmentconfiguration, installation and layout, process recipes andspecifications are exactly copied. Facilities running the sametechnology actually use the same operating specifications ina shared mode. Joint teams are formed to enhance sharedlearning and enforce exact procedures. The outcome hasbeen rewarding as the results from newer facilities wereindistinguishable from those of the more mature developmentfacility.

VI. CONCLUSION

The challenges of producing high-performance micropro-cessors in high volume are considerable but can be met.Transistor density, performance and power requirements arebeing met through the use of aggressive transistor featuresize scaling coupled with supply voltage scaling. Interconnectdensity and performance requirements are a growing consider-ation and are being met through the use of more metal layerswith higher aspect ratios. The manufacturing strategy used toensure high-volume production at reasonable cost includes theearly use of SRAM development vehicles, extensive reuseof equipment and modules, a “copy exactly” methodology,and overall ownership by the development organization fromtechnology inception through early high-volume ramp.

REFERENCES

[1] M. Bohr, S. U. Ahmed, L. Brigham, R. Chau, R. Gasser, R. Green,W. Hargrove, E. Lee, R. Natter, S. Thompson, K. Weldon, and S.Yang, “A high-performance 0.35-�m logic technology for 3.3 and 2.5V operation,” in IEDM Tech. Dig., 1994, pp. 273–276.

[2] M. Bohr, S. S. Ahmed, S. U. Ahmed, M. Bost, T. Ghani, J. Greason,R. Hainsey, C. Jan, P. Packan, S. Sivakumar, S. Thompson, J. Tsai, andS. Yang, “A high-performance 0.25-�m logic technology optimized for1.8 V operation,” inIEDM Tech. Dig., 1996, pp. 847–850.

[3] A. Bryant W. Hansch, and T. Mii, “Characteristics of CMOS deviceisolation for the ULSI age,” inIEDM Tech. Dig., 1994, pp. 671–674.

[4] S. Thompson, I. Young, J. Greason, and M. Bohr, “Dual thresholdvoltages and substrate bias: Keys to high-performance, low-power, 0.1-�m logic designs,” inSymp. VLSI Technol. Dig., 1997, pp. 69–70.

[5] M. Bohr, “MOS transistors: scaling and performance trends,”Semicon-duct. Int., vol. 18, no. 6, pp. 75–80, 1995.

[6] , “Interconnect scaling—The real limiter to high-performanceULSI,” in IEDM Tech. Dig., 1995, pp. 241–244.

[7] J. Greason, D. Buehler, J. Kolousek, Y.-G. Ng, K. Sarkez, P. Shay, andA. Waizman, “A 4.5 megabit, 560 MHz, 4.5 Gbytes/s high bandwidthSRAM,” in Symp. VLSI Circuits Dig., 1997, pp. 15–16.

Mark T. Bohr (M’93–SM’95) was born in Chicago,IL, in 1953. He received the B.S. degree in industrialengineering in 1976 and the M.S. degree in electricalengineering in 1978, both from the University ofIllinois, Champaign-Urbana.

He joined Intel’s Portland Technology Develop-ment Group in 1978 and has been responsible forprocess integration and device design on a variety ofDRAM, SRAM, and logic technologies, includingIntel’s first CMOS technology in 1981, the world’sfirst CMOS DRAM technology in 1983, Intel’s first

BiCMOS logic technology in 1992, and recent 0.35- and 0.25-�m logictechnologies used to make Pentium and PentiumPro microprocessors. Heis an Intel Fellow and Director of Process Architecture and Integration, and iscurrently directing development activities on 0.18- and 0.13-�m technologies.

Mr. Bohr has served on paper selection committees for the InternationalElectron Devices Meeting and for the Symposium on VLSI Technology.

Youssef A. El-Mansy (S’71–M’74–SM’85–F’90)was born in Egypt in 1945. He received the B.S.and M.S. degrees in electrical engineering fromAlexandria University, Egypt, in 1966 and 1970,respectively, and the Ph.D. degree in electrical en-gineering from Carlton University, Ottawa, Ont.,Canada, in 1974.

After graduation, he was with Bell NorthernResearch, Ottawa. In 1979, he joined Intel Corpo-ration, Portland, OR, as Manager of TechnologyEvaluation in Portland Technology Development,

where he was responsible for the assessment of competitor technologiesand evaluation of future and promising technology trends. Over the past13 years, he has been managing and guiding various aspects of technologydevelopment from DRAM’s to microprocessors. The positions he has heldinclude: Manager of the Technology Evaluation Group (1979–1980); ProgramManager 64K DRAM (1981–1983); Program Manager for the industry’sfirst 1-Mb CMOS DRAM (1983–1985); and Engineering Manager, LogicTechnologies (1985–1990). Since 1985, his organization has developed andtransferred to manufacturing the leading edge microprocessor technologiesand designs for successive generations of the Intel architecture. In 1990, hewas promoted to Vice President in Intel’s Technology and ManufacturingGroup and Director of Portland Technology Development and was appointeda group Vice President in 1993. He is responsible for managing a state-of-the-art manufacturing facility, design center, and technology development groupsspanning generations of technology.

Dr. El-Mansy is an active member in various organizations of the IEEE,including the Executive VLSI Committee, the Electron Devices ExecutiveCommittee, and the VLSI Symposium.