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Leading at the edgeTECHNOLOGY AND MANUFACTURING DAY
TECHNOLOGY AND MANUFACTURING DAY
10 nm technology leadershipKAIZAD MISTRYCorporate Vice President, Technology and Manufacturing GroupCo-Director, Logic Technology Development
TECHNOLOGY AND MANUFACTURING DAY
Intel Technology and Manufacturing Day 2017 occurs during Intel’s “Quiet Period,” before Intel announces its 2017 firstquarter financial and operating results. Therefore, presenters will not be addressing first quarter information duringthis year’s program.
Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statementsthat involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,”“believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “would,” “should,” “could,” and variations of such words andsimilar expressions are intended to identify such forward-looking statements. Statements that refer to or are based onprojections, uncertain events or assumptions also identify forward-looking statements. Such statements are based onmanagement’s expectations as of March 28, 2017, and involve many risks and uncertainties that could cause actualresults to differ materially from those expressed or implied in these forward-looking statements. Important factors thatcould cause actual results to differ materially from the company’s expectations are set forth in Intel’s earnings releasedated January 26, 2017, which is included as an exhibit to Intel’s Form 8-K furnished to the SEC on such date.Additional information regarding these and other factors that could affect Intel’s results is included in Intel’s SEC filings,including the company’s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting ourInvestor Relations website at www.intc.com or the SEC’s website at www.sec.gov.
Disclosures
TECHNOLOGY AND MANUFACTURING DAY
Intel’s 10 nm process technology has the world’s tightest transistor & metal pitches along with hyper scaling features for leadership density
Intel’s 10 nm technology is a full generation ahead of other “10 nm” technologies
Enhanced versions of Intel 10 nm provide improved power/performance within the 10 nm process family
Hyper scaling extracts the full value of multi-patterning schemes and allows Intel to continue the benefits of Moore’s Law economics
Key messages
Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Intel 10 nm Features
Intel 10 nm Hyper Scaling
Enhanced Versions of Intel 10 nm
Hyper Scaling Redux
AGENDA
TECHNOLOGY AND MANUFACTURING DAY
10 nm Hyper Scaling
10 nm features aggressive pitch scaling - world’s first Self-Aligned Quad Patterning
Fin Pitch Min Metal Pitch Cell Height Gate Pitch42 nm 34 nm 52 nm 36 nm 399 nm 272 nm 70 nm 54 nm
.81x .69x .68x .78x
14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
10 nm Hyper Scaling
10 nm aggressive scaling & new features deliver 2.7x transistor density improvement
Fin Pitch Min Metal Pitch Cell Height Gate Pitch Dummy Gate Gate Contact42 nm 34 nm 52 nm 36 nm 399 nm 272 nm 70 nm 54 nm Double Single Std COAG
.81x .69x .68x .78x
14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm
Contact
Contact
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
100.8
3.3
7.5
15.3
37.5
MTr / mm2
Logic Transistor density
Intel 10 nm hyper scaling features result in Transistor Density above 100MTr/mm2
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
10 nm
3rd Generation FinFETs
14 nm22 nm
10 nm Fins are ~25% taller and ~25% more closely spaced than 14 nm
TECHNOLOGY AND MANUFACTURING DAY
10 nm
3rd Generation FinFETs
14 nm22 nm
Intel’s 10 nm technology features a Fin Pitch of 34 nm, Fin Height of 53 nm
53 nm
34 nm
TECHNOLOGY AND MANUFACTURING DAY
0
20
40
60
80
100
120
140
160
180
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
TransistorGate Pitch
(nm)
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
Intel’s 10 nm technology features 54 nm gate pitch
Transistor gate pitch scaling
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
0
20
40
60
80
100
120
140
160
180
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
TransistorGate Pitch
(nm)
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
45/40nm
14/16nm
28/32nm28nm
Others(measured)
20nm
10nm(est.)
Intel 10 nm Gate Pitch is the tightest in the industry
Transistor gate pitch trend
Source: Amalgamation of analyst data and Intel analysis. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Interconnect Pitch(nm)
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
Intel 10 nm technology features a minimum metal pitch of 36 nm World’s first Self-Aligned Quad Patterning
Metal pitch scaling
36 nm Pitch
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Interconnect Pitch(nm)
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
45/40nm
14/16nm
28/32nm28nm
Others(measured)
20nm
10nm(est.)
Intel 10 nm technology has the tightest minimum metal pitch in the industry
Metal pitch SCALING trend
36 nm Pitch
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Contact over active gate is a revolutionary feature for another ~10% area scaling
Transistor
Contact
Contact Over Active gate
Transistor
FinsContact
TECHNOLOGY AND MANUFACTURING DAY
Single dummy Gate
14 nm 10 nmSingle
Dummy Gate
Active Gate
Active Gate
Dummy Gate
Process innovations enable denser single dummy gate at cell borders
TECHNOLOGY AND MANUFACTURING DAY
Single dummy gate
2-Input NAND Cell Complex Scan Flip-Flop Logic Cell
Cell Width
Cell Width
Single dummy gate at cell borders provides ~20% effective area scaling benefit
TECHNOLOGY AND MANUFACTURING DAY
Intel 10 nm Features
Intel 10 nm Hyper Scaling
Enhanced Versions of Intel 10 nm
Hyper Scaling Redux
AGENDA
TECHNOLOGY AND MANUFACTURING DAY
Fin pitch and metal pitch scaling allow cell height to scale 0.68x from 14 nm
14 nm399nmHeight 10 nm
272nmHeight(0.68x)
Cell Height
Gate Pitch Gate Pitch
Cell Height
Library Height Scaling
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel 10 nm Logic Density scaling
Cell height and gate pitch scaling provides traditional area reduction of ~0.5x
0.0
0.2
0.4
0.6
0.8
1.0
Cell Height Gate Pitch COAG Single DG
Traditional Scaling
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel 10 nm Logic Density scaling
Intel 10 nm hyper scaling features further improve area scaling to 0.37x
0.0
0.2
0.4
0.6
0.8
1.0
Cell Height Gate Pitch COAG Single DG
Traditional Scaling
Hyper ScalingFeatures
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
0.01
0.1
1
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
LogicArea
(relative)
HVM Wafer Start Date
45nm
22nm
14nm
32nm
.37x
.49x
.45x
10nm
.37x
Logic area scaling
10 nm hyper scaling features provides better-than-normal 0.37x logic area scaling
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
2.7x
2.5x
2.1x
2.3x
Logic Transistor density
Intel 10 nm hyper scaling features provide ~2.7x transistor density improvement
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
Logic Transistor density
Hyper scaling maintains the rate of Moore’s Law density scaling
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
45/40nm
14/16nm
28/32nm28nm
Others(measured)
20nm
10nm(est.)
~2x
Logic Transistor density
Intel 10 nm is a full generation ahead of other “10 nm” technologies
Source: Amalgamation of analyst data and Intel analysis. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
0.01
0.1
45nm 32nm 22nm 14nm 10nm 7nm
SRAM Cell Area
(um2)HP .0441LV .0367HD .0312
um2
10 nm offers a range of SRAM cells for density and power/performanceSRAM cell area scaled ~0.6x from 14 nm
SRAM AREA SCALING
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Microprocessor die area scaling
Hyper scaling delivers better microprocessor die area scaling than the normal trend
100 mm2
45 nm 32 nm 22 nm 14 nm 10 nm
62 mm2
17.7 mm27.6 mm2
0.62x
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
0.43x
0.46x0.62x
Area
38.4 mm2
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel 10 nm Features
Intel 10 nm Hyper Scaling
Enhanced Versions of Intel 10 nm
Hyper Scaling Redux
AGENDA
TECHNOLOGY AND MANUFACTURING DAY
2007 2009 2011 2013 2015 2017 2019 2021
Tran
sist
orPe
rform
ance
(log
scal
e)
Process Readiness Date
45nm
22nm
14nm
10nm
32nm
10++
10+
HigherPerformance
14++
14+
2007 2009 2011 2013 2015 2017 2019 2021
Dyn
amic
Cap
acita
nce
(log
scal
e)
Process Readiness Date
45nm
22nm
14nm
10nm
32nm
10+ 10++LowerPower
14+ 14++
Technology enhancements
10 nm enhancements improve performance and extend technology life
Source: Intel. 2017-2021 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
10 nm technology continues trend of power/performance improvements
Technology enhancements
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.4 0.6 0.8 1.0 1.2
Activ
e Po
wer
(nor
m/f
in)
Performance (norm)
14nm10nm
matched leakage/[email protected]
25%
0.55x
Source: Intel estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
10++ enhancements offer improved power/performance within 10 nm generation
Technology enhancements
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.4 0.6 0.8 1.0 1.2
Activ
e Po
wer
(nor
m/f
in)
Performance (norm)
14nm10nm10++
matched leakage/[email protected]
15%
0.7x
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.4 0.6 0.8 1.0 1.2
Activ
e Po
wer
(nor
m/f
in)
Performance (norm)
14nm10nm
matched leakage/[email protected]
0.55x
25%
Source: Intel estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Intel’s 10 nm technology family has features for a broad range of products
Technology enhancements
Low Cost Dense High Perf
High Voltage FinFETs
High Q Inductors
High Res Substrates Precision Resistors
Interconnect Options
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel 10 nm Features
Intel 10 nm Hyper Scaling
Enhanced Versions of Intel 10 nm
Hyper Scaling Redux
AGENDA
TECHNOLOGY AND MANUFACTURING DAY
Hyper scaling allows Intel to continue the economics of Moore’s Law More than 2X logic transistor density increase but with longer than 2 year cadence Same rate of transistor density increase as traditional Moore’s Law scaling Same rate of Cost per Transistor improvement as traditional Moore’s Law scaling Power/performance enhancements within each process node
Why hyper scaling? Multi-pass patterning adds to the cost of lithography Hyper scaling extracts the full cost per transistor benefit of advanced patterning schemes
Hyper scaling would not be possible without Self-Aligned Dual and Self-Aligned Quad Patterning along with other 10 nm hyper scaling innovations
Hyper scaling
TECHNOLOGY AND MANUFACTURING DAY
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
$ / mm2
(normalized)
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
$ / Transistor(normalized)
x =
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
mm2 / Transistor(normalized)
Log
Scal
e
Log
Scal
e
Log
Scal
e
Cost per transistor
Hyper scaling allows the economics of Moore’s Law to continue
Source: Intel estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Intel’s 10 nm process technology has the world’s tightest transistor & metal pitches along with hyper scaling features for leadership density
Intel’s 10 nm technology is a full generation ahead of other “10 nm” technologies
Enhanced versions of Intel 10 nm provide improved power/performance within the 10 nm process family
Intel’s 10nm process technology is on track to commence manufacturing in 2H’17
Hyper scaling extracts the full value of multi-patterning schemes and allows Intel to continue the economic benefits of Moore’s Law
CONCLUSIONS
Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information.
Leading at the edgeTECHNOLOGY AND MANUFACTURING DAY