Team Antelope

Progress Report

Antelope Team Progress

Finished:ShifterRegister FileMultiplierMultiply AccumulateALUCLZ

Still Working On:CacheInstruction DecodeIntegration

Memory system

Cache Unit

Cache Specs

• 16 bytes wide

• 9 bit line address

• Write-back

• data + instr caches– Check for dirty blocks in data cache on writes

• Clock stalls during main memory interaction

32-Bit Barrel Shifter

Carry In / Carry Out

-Carry in only used in RRX (rotate right extended) operations

-Carry out always computed, even though not needed in rotate operations

Carry Out Logic: Two Options

• Separate logic computes Cout early using input and shift amount

Pros:

-Cout signal ready much earlier, no need for propagation

-Simpler bit shifter designs

Cons:

-Many more gates needed

Carry Out Logic: Two Options

• Individual bit shifters compute and propagate Cout signal

Pros:

-Simpler overall design

-Fewer logic gates

Cons:

-Takes longer for Cout to be ready (propagation delay)

-More complicated bit shifters

Conclusion

• Went ahead and implemented Cout logic in the bit shifters

-Don’t really need the signal to be ready any earlier than the rest of the shifter output, especially not at the addition gate cost

-Each shifter computes Cout for its own shift amount and passes it on, or leaves Cout alone if it is disabled

Result propagated through bit shifters

Added 32-bit Shifters

Barrel Shifter

16 Bit-Right Shifter

• 32 additions in parallel

• Logarithmic time result

• 25 = 32, so time equals 5 adds

• Multiply w/accumulate inserted at the end with a multiplexor

Multiplier (MUL/MLA)

Multiplier (MUL/MLA)

Multiplier (MUL/MLA)

Multiplier (MUL/MLA)

Multiplier (MUL/MLA)

Multiplier (MUL/MLA)

• Output equals number of leading zeros on the input (Ex: 00010110 00000011)

• First step: 00010110 00011111

• Then, add one: 00011111 00100000

• Lastly, convert to binary. With a 32-bit input, output will have a 6-digit maximum.

Count leading zeros (CLZ)

Count leading zeros (CLZ)

Count leading zeros (CLZ)

Count leading zeros (CLZ)

Count leading zeros (CLZ)

CLZ Timing

• Time equals:

2x 16-bit OR gate

1x 2-bit OR gate

1x 2-bit XOR gate

•Perhaps faster than an addition!

Register File Complete

• 37 total registers

• 4 outputs Register1 out, Register2 out, CPSR out, and PC out

• 7 inputs: ReadSelect1, ReadSelect2, Mode, WriteEnable, Clk, PC, CPSR

Integration Status

• Most components are complete

• Ready to start running most instructions

• Need to make stage buffers

• Most importantly, need to start figuring out the control structure