TDCB status and Firmware updates
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TDCB status and Firmware updates
TDAQ working group meeting
24.03.2010
Andrea Burato (INFN Pisa)On behalf of TDCB working group
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Summary / Outline
Status of the TDC Board TDCB firmware funtionalities
and features Firmware updates:
TDC / FPGA comunication Periodic-trigger mode Registers manual
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Status of TDC Board
Brief reminder:
• New FPGA Cyclone III and new PCB with some correction and improvement
• Layout made at CERN on December ‘09
• 20 PCB produced and 2 board assembled for testing
Cost 956 € all included
Worst case including T.V.A. (not present in production) and withorders of very small components volume for prototypes
After testing some other boards can be assembled. Ask now!!
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Status of TDC Board
Cables for preliminary TDCB V3 testing:
Two amphenol cables • skewclear• 34 couples• high performance• halogen free
Not final solution too good and too expensive
Cost 230 €(prototype)
• Started market survey: twisted-pair cable + VHDCI connector• Investigation for a home-made solution (Pisa)
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TDCB firmware
• TDC / FPGA interface
Main features:
• TDCB-FPGA / TELL1 (PP-FPGA) interface
• Trigger functionality
• jtag TDC configuration settings• data transfer from TDC to FPGA
• I2C comunication for slow control• data transfer from FPGA to TELL1
In previous test TDCB-FPGA were not used and TDCsspoke directly to TELL1 through FPGA, now it changes
TDCB Firmware
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TDCB firmware
TDC / FPGA interface
• Data transfer from TDC buffer into FPGA internal FIFO (new feature)
• TDC configuration via jtag
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TDCB firmware
TDCB-FPGA / TELL1 (PP-FPGA) interface
• I2C comunication to write an read TDCB-FPGA registers• data transfer from FPGA internal FIFOs to PP FIFOs (new feature)
TDCB:• One FIFO of 32x256 words for each TDC• One read-out buffer for each FIFO
PP sees the FIFO like a TDC
PP-firmware remains the same
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TDCB firmware
Complete read-out scheme:
• Possibility to make pre-processing using RAM equipped on TDCB• Possibility to inject data for testing• Monitoring
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TDCB firmware
Trigger functionality
Before: TDC continuously reading (triggerless mode)
Now: TDC used in trigger mode with a periodic trigger from FPGA
• TDC sends data belonging to a changeable time window
• Each TDC red independently on a different bus (40 Mhz) but same trigger
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Firmware UpdatesPeriodic-trigger mode
Ttrg range: 0.4 - 38.4 µs with step of 0.4 µs
• A periodic trigger is sent from the FPGA to TDC
TDC side
• TDC load in readout buffer all data that match a specific time window
• Each data packet, send to FPGA, concerns a trigger
• In periodic trigger mode the time window is equal to trigger period
All data are sending to FPGA
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Firmware UpdatesPeriodic-trigger mode
FPGA side
• Adds Time Stamp (TS) at the beginning of data packet from TDC
TS ID: Time Stamp identification code
Course count: LSB 0.4 µs range from 0.4 µs to100 s
• Transfers data into internal FPGA FIFO (one for each TDC)
• Adds to data packet a final word with words count
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Conclusions
• 20 PCB ready• 2 board assembled and ready for test
• 2 Amphenol prototype cables
• New firmware feature: periodic trigger mode
To do list:
• Test new card• Measure clock jitter / time resolution
• Test again TDC rate limits
• Firmware improvements
After testing some other boards can be assembled. Ask now!!
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