7th Sem, VLSI Lab Manual LEONARDO SPECTRUM CONSTRAINTS 2011-12

Dept. of E&C, CEC 1 SKLN, RCVK

sync_counter.tcl load_library tsmc018_typ.syn read -format verilog sync_counter.v set input2register 2.00 set input2output 3.00 set register2output 3.00 set register2register 3.20 clock_cycle 3.2 clock set_attribute -name ARRIVAL_TIME -value "0.4" -port reset set_attribute -name ARRIVAL_TIME -value "0.4" -port down set_attribute -name ARRIVAL_TIME -value "0.4" -port up optimize write -format verilog sync_counter_netlist.v write -format sdf sync_counter.sdf report_delay > delay.rpt report_area > area.rpt Async_counter.tcl load_library tsmc018_typ.syn read -format verilog Async_counter.v elaborate set input2register 2.00 set input2output 3.00 set register2output 3.00 set register2register 3.20 clock_cycle 3.2 Clock set_attribute -name ARRIVAL_TIME -value "0.4" -port Reset optimize write -format verilog Async_counter_netlist.v write -format sdf Async_counter.sdf report_delay > delay.rpt report_area > area.rpt dflipflop.tcl load_library tsmc018_typ.syn read -format verilog dflipflop.v optimize write -format verilog dflipflop_netlist.v write -format sdf dflipflop.sdf master_slave.tcl load_library tsmc018_typ.syn read -format verilog dflipflop.v read -format verilog masterslave_flipflop.v clock_cycle 1 clock_i set input2register 0.5 set register2register 1 set register2output 0.5 optimize write -format verilog master_slave_netlist.v write -format sdf masterslave.sdf rsflipflop.tcl load_library tsmc018_typ.syn read -format verilog dflipflop.v read -format verilog rsflipflop.v synthesize optimize write -format verilog rsflipflop_netlist.v write -format sdf rsflipflop.sdf

tflipflop.tcl load_library tsmc018_typ.syn read -format verilog tflipflop.v clock_cycle 1 clock_i set input2register 0.5 set register2register 1 set register2output 0.5 optimize write -format verilog tflipflop_netlist.v write -format sdf tflipflop.sdf buffer.tcl load_library tsmc018_typ.syn read -format verilog buffer.v set input2output 0.6 optimize write -format verilog buffer_netlist.v write -format sdf buffer.sdf serial_adder.tcl load_library tsmc018_typ.syn read -format verilog full_adder.v read -format verilog serial_adder_4bit.v set input2output 1 optimize write -format verilog serialadder_netlist.v write -format sdf serialadder.sdf sar.tcl load_library tsmc018_typ.syn read -format verilog sar.v set input2register 2.00 set input2output 3.00 set register2output 3.00 set register2register 3.20 clock_cycle 3.2 clock_i optimize write -format verilog sar_netlist.v write -format sdf sar.sdf report_delay > delay.rpt report_area > area.rpt parllel_adder.tcl load_library tsmc018_typ.syn read -format verilog parllel_adder.v set input2output 1 optimize write -format verilog parlleladder_netlist.v write -format sdf parlleladder.sdf tgate.tcl load_library tsmc018_typ.syn read -format verilog tgate.v optimize write -format verilog tgate_netlist.v write -format sdf tgate.sdf

7th Sem, VLSI Lab Manual LEONARDO SPECTRUM CONSTRAINTS 2011-12

Dept. of E&C, CEC 2 SKLN, RCVK

inverter_syn.tcl load_library tsmc018_typ.syn read -format verilog inverter.v set input2output 0.5 optimize write -format verilog inverter_netlist.v write -format sdf inverter.sdf basic_gate.tcl load_library tsmc018_typ.syn read -format verilog and.v present_design set input2output 1 optimize write -format verilog basic_gates_and.v write -format sdf basic_gates_and.sdf report_delay > and_delay.rpt read -format verilog or.v present_design set input2output 1 optimize write -format verilog basic_gates_or.v write -format sdf basic_gates_or.sdf report_delay > or_delay.rpt read -format verilog nand.v present_design set input2output 1 optimize write -format verilog basic_gates_nand.v write -format sdf basic_gates_nand.sdf report_delay > nand_delay.rpt read -format verilog nor.v present_design set input2output 1 optimize write -format verilog basic_gates_nor.v write -format sdf basic_gates_nor.sdf report_delay > nor_delay.rpt read -format verilog xor.v present_design set input2output 1 optimize write -format verilog basic_gates_xor.v write -format sdf basic_gates_xor.sdf report_delay > xor_delay.rpt read -format verilog xnor.v present_design set input2output 1 optimize write -format verilog basic_gates_xnor.v write -format sdf basic_gates_xnor.sdf report_delay > xnor_delay.rpt

Steps: 1. Create Mainmodule Verilog

$ vi sync_counter.v 2. Check Syntax error of Only Mainmodule Verilog

$ vlog sync_counter.v 3. Create Testbench to test Mainmodule Verilog

$ vi sync_counter_testbench.v 4. Check Syntax error of Only Testbench

$ vlog sync_counter_testbench.v 5. Check compatibility of both Top/Mainmodule and

Testbench together to obtain Top-module name $ vlog sync_counter.v sync_counter_testbench.v

6. Simulate Testbench in Text mode using Top-module name in Vsim $ vsim –c sync_counter_testbench –novopt run -all

7. Simulate Testbench in GUI/Graphical mode in Modelsim $ vsim sync_counter_testbench –novopt

8. Generate SDF and Netlist file from Spectrum using constraints provided $ spectrum

<leonardo 1> load_library tsmc018_typ.syn <leonardo 2> read -format verilog sync_counter.v <leonardo 3> set input2register 2.00 <leonardo 4> set input2output 3.00 <leonardo 5> set register2output 3.00 <leonardo 6> set register2register 3.20 <leonardo 7> clock_cycle 3.2 clock <leonardo 8> set_attribute -name ARRIVAL_TIME -value "0.4" -port reset <leonardo 9> set_attribute -name ARRIVAL_TIME -value "0.4" -port down <leonardo 10> set_attribute -name ARRIVAL_TIME -value "0.4" -port up <leonardo 11> optimize <leonardo 12> write -format verilog sync_counter_netlist.v <leonardo 13> write -format sdf sync_counter.sdf <leonardo 14> report_delay > delay.rpt <leonardo 15> report_area > area.rpt <leonardo 16> exit

9. Create Gatelevel Testbench to test Mainmodule Verilog using 180 nm Technology $ vi sync_counter_gatetestbench.v

10. Check Syntax error of Only Gatelevel Testbench $ vlog sync_counter_gatetestbench.v

11. Check compatibility of Netlistfile, Gatelevel Testbench and adk.v library together to obtain Top-module name w.r.t. 180 nm Technology

$ vlog sync_counter_netlist.v sync_counter_gatetestbench.v adk.v 12. Simulate Gatelevel Testbench in Text mode using

Top-module name in Vsim $ vsim –c sync_counter_gatetestbench –novopt run -all

13. Simulate Gatelevel Testbench in GUI/Graphical mode in Modelsim using Top-module name $ vsim sync_counter_gatetestbench –novopt